From: Geert Uytterhoeven <geert@linux-m68k.org>
Remove superfluous whitespace that hurts my eyes with `let c_space_errors=1'
in vim. This includes correcting trailing whitespace and spaces in front of
tabs. `diff -urNbB' shows no difference before/after.
---
25-akpm/arch/m68k/Kconfig | 8
25-akpm/arch/m68k/Makefile | 2
25-akpm/arch/m68k/amiga/amisound.c | 2
25-akpm/arch/m68k/amiga/chipram.c | 2
25-akpm/arch/m68k/amiga/config.c | 14
25-akpm/arch/m68k/apollo/config.c | 64
25-akpm/arch/m68k/apollo/dma.c | 2
25-akpm/arch/m68k/apollo/dn_debug.c | 4
25-akpm/arch/m68k/apollo/dn_ints.c | 4
25-akpm/arch/m68k/atari/ataints.c | 24
25-akpm/arch/m68k/atari/atasound.c | 2
25-akpm/arch/m68k/atari/config.c | 28
25-akpm/arch/m68k/atari/debug.c | 24
25-akpm/arch/m68k/atari/stdma.c | 2
25-akpm/arch/m68k/atari/stram.c | 38
25-akpm/arch/m68k/atari/time.c | 38
25-akpm/arch/m68k/bvme6000/rtc.c | 4
25-akpm/arch/m68k/defconfig | 2
25-akpm/arch/m68k/fpsp040/README | 4
25-akpm/arch/m68k/fpsp040/bindec.S | 116 -
25-akpm/arch/m68k/fpsp040/binstr.S | 4
25-akpm/arch/m68k/fpsp040/bugfix.S | 68 -
25-akpm/arch/m68k/fpsp040/decbin.S | 24
25-akpm/arch/m68k/fpsp040/do_func.S | 56
25-akpm/arch/m68k/fpsp040/fpsp.h | 26
25-akpm/arch/m68k/fpsp040/gen_except.S | 78 -
25-akpm/arch/m68k/fpsp040/get_op.S | 82 -
25-akpm/arch/m68k/fpsp040/kernel_ex.S | 60
25-akpm/arch/m68k/fpsp040/res_func.S | 154 +-
25-akpm/arch/m68k/fpsp040/round.S | 106 -
25-akpm/arch/m68k/fpsp040/sacos.S | 16
25-akpm/arch/m68k/fpsp040/sasin.S | 10
25-akpm/arch/m68k/fpsp040/satan.S | 22
25-akpm/arch/m68k/fpsp040/satanh.S | 8
25-akpm/arch/m68k/fpsp040/scale.S | 22
25-akpm/arch/m68k/fpsp040/scosh.S | 6
25-akpm/arch/m68k/fpsp040/setox.S | 28
25-akpm/arch/m68k/fpsp040/sgetem.S | 14
25-akpm/arch/m68k/fpsp040/sint.S | 30
25-akpm/arch/m68k/fpsp040/skeleton.S | 52
25-akpm/arch/m68k/fpsp040/slog2.S | 34
25-akpm/arch/m68k/fpsp040/slogn.S | 38
25-akpm/arch/m68k/fpsp040/smovecr.S | 12
25-akpm/arch/m68k/fpsp040/srem_mod.S | 18
25-akpm/arch/m68k/fpsp040/ssin.S | 26
25-akpm/arch/m68k/fpsp040/ssinh.S | 8
25-akpm/arch/m68k/fpsp040/stan.S | 58
25-akpm/arch/m68k/fpsp040/stanh.S | 10
25-akpm/arch/m68k/fpsp040/sto_res.S | 8
25-akpm/arch/m68k/fpsp040/stwotox.S | 28
25-akpm/arch/m68k/fpsp040/tbldo.S | 10
25-akpm/arch/m68k/fpsp040/util.S | 70 -
25-akpm/arch/m68k/fpsp040/x_bsun.S | 4
25-akpm/arch/m68k/fpsp040/x_fline.S | 8
25-akpm/arch/m68k/fpsp040/x_operr.S | 26
25-akpm/arch/m68k/fpsp040/x_ovfl.S | 16
25-akpm/arch/m68k/fpsp040/x_snan.S | 26
25-akpm/arch/m68k/fpsp040/x_store.S | 44
25-akpm/arch/m68k/fpsp040/x_unfl.S | 34
25-akpm/arch/m68k/fpsp040/x_unimp.S | 8
25-akpm/arch/m68k/fpsp040/x_unsupp.S | 18
25-akpm/arch/m68k/hp300/hp300map.map | 90 -
25-akpm/arch/m68k/hp300/ints.c | 16
25-akpm/arch/m68k/ifpsp060/CHANGES | 26
25-akpm/arch/m68k/ifpsp060/MISC | 6
25-akpm/arch/m68k/ifpsp060/README | 4
25-akpm/arch/m68k/ifpsp060/TEST.DOC | 14
25-akpm/arch/m68k/ifpsp060/fplsp.doc | 6
25-akpm/arch/m68k/ifpsp060/fpsp.doc | 20
25-akpm/arch/m68k/ifpsp060/fskeleton.S | 26
25-akpm/arch/m68k/ifpsp060/ilsp.doc | 16
25-akpm/arch/m68k/ifpsp060/iskeleton.S | 18
25-akpm/arch/m68k/ifpsp060/isp.doc | 18
25-akpm/arch/m68k/ifpsp060/os.S | 78 -
25-akpm/arch/m68k/ifpsp060/src/fplsp.S | 358 ++---
25-akpm/arch/m68k/ifpsp060/src/fpsp.S | 1826 ++++++++++++++--------------
25-akpm/arch/m68k/ifpsp060/src/ftest.S | 16
25-akpm/arch/m68k/ifpsp060/src/ilsp.S | 106 -
25-akpm/arch/m68k/ifpsp060/src/isp.S | 540 ++++----
25-akpm/arch/m68k/ifpsp060/src/itest.S | 8
25-akpm/arch/m68k/ifpsp060/src/pfpsp.S | 1304 +++++++++----------
25-akpm/arch/m68k/kernel/bios32.c | 2
25-akpm/arch/m68k/kernel/entry.S | 30
25-akpm/arch/m68k/kernel/head.S | 6
25-akpm/arch/m68k/kernel/ptrace.c | 14
25-akpm/arch/m68k/kernel/setup.c | 30
25-akpm/arch/m68k/kernel/signal.c | 10
25-akpm/arch/m68k/kernel/sun3-head.S | 28
25-akpm/arch/m68k/kernel/sys_m68k.c | 10
25-akpm/arch/m68k/kernel/traps.c | 26
25-akpm/arch/m68k/kernel/vmlinux-std.lds | 14
25-akpm/arch/m68k/kernel/vmlinux-sun3.lds | 28
25-akpm/arch/m68k/lib/ashldi3.c | 2
25-akpm/arch/m68k/lib/ashrdi3.c | 2
25-akpm/arch/m68k/lib/lshrdi3.c | 2
25-akpm/arch/m68k/lib/muldi3.c | 4
25-akpm/arch/m68k/mac/baboon.c | 6
25-akpm/arch/m68k/mac/bootparse.c | 178 +-
25-akpm/arch/m68k/mac/config.c | 64
25-akpm/arch/m68k/mac/debug.c | 24
25-akpm/arch/m68k/mac/iop.c | 18
25-akpm/arch/m68k/mac/macboing.c | 76 -
25-akpm/arch/m68k/mac/macints.c | 14
25-akpm/arch/m68k/mac/misc.c | 12
25-akpm/arch/m68k/mac/oss.c | 10
25-akpm/arch/m68k/mac/psc.c | 6
25-akpm/arch/m68k/mac/via.c | 18
25-akpm/arch/m68k/math-emu/fp_arith.c | 2
25-akpm/arch/m68k/math-emu/fp_cond.S | 8
25-akpm/arch/m68k/math-emu/fp_log.c | 4
25-akpm/arch/m68k/math-emu/fp_scan.S | 8
25-akpm/arch/m68k/math-emu/fp_util.S | 2
25-akpm/arch/m68k/mm/fault.c | 4
25-akpm/arch/m68k/mm/hwtest.c | 10
25-akpm/arch/m68k/mm/init.c | 2
25-akpm/arch/m68k/mm/memory.c | 6
25-akpm/arch/m68k/mm/motorola.c | 6
25-akpm/arch/m68k/mm/sun3kmap.c | 30
25-akpm/arch/m68k/mm/sun3mmu.c | 8
25-akpm/arch/m68k/mvme147/config.c | 14
25-akpm/arch/m68k/mvme16x/mvme16x_ksyms.c | 2
25-akpm/arch/m68k/mvme16x/rtc.c | 4
25-akpm/arch/m68k/q40/Makefile | 2
25-akpm/arch/m68k/q40/README | 48
25-akpm/arch/m68k/q40/config.c | 18
25-akpm/arch/m68k/q40/q40ints.c | 40
25-akpm/arch/m68k/sun3/config.c | 30
25-akpm/arch/m68k/sun3/dvma.c | 8
25-akpm/arch/m68k/sun3/idprom.c | 4
25-akpm/arch/m68k/sun3/intersil.c | 2
25-akpm/arch/m68k/sun3/leds.c | 4
25-akpm/arch/m68k/sun3/mmu_emu.c | 40
25-akpm/arch/m68k/sun3/prom/init.c | 2
25-akpm/arch/m68k/sun3/sun3dvma.c | 66 -
25-akpm/arch/m68k/sun3/sun3ints.c | 30
25-akpm/arch/m68k/sun3x/config.c | 8
25-akpm/arch/m68k/sun3x/dvma.c | 44
25-akpm/arch/m68k/sun3x/prom.c | 6
25-akpm/arch/m68k/sun3x/time.c | 10
25-akpm/include/asm-m68k/amigahw.h | 16
25-akpm/include/asm-m68k/apollodma.h | 10
25-akpm/include/asm-m68k/apollohw.h | 8
25-akpm/include/asm-m68k/atafdreg.h | 2
25-akpm/include/asm-m68k/atari_SCCserial.h | 2
25-akpm/include/asm-m68k/atari_acsi.h | 2
25-akpm/include/asm-m68k/atarihw.h | 82 -
25-akpm/include/asm-m68k/atariints.h | 12
25-akpm/include/asm-m68k/bitops.h | 2
25-akpm/include/asm-m68k/bootinfo.h | 10
25-akpm/include/asm-m68k/cacheflush.h | 6
25-akpm/include/asm-m68k/checksum.h | 2
25-akpm/include/asm-m68k/delay.h | 2
25-akpm/include/asm-m68k/dvma.h | 12
25-akpm/include/asm-m68k/entry.h | 2
25-akpm/include/asm-m68k/floppy.h | 14
25-akpm/include/asm-m68k/hwtest.h | 4
25-akpm/include/asm-m68k/ide.h | 2
25-akpm/include/asm-m68k/intersil.h | 2
25-akpm/include/asm-m68k/io.h | 14
25-akpm/include/asm-m68k/ipc.h | 2
25-akpm/include/asm-m68k/irq.h | 2
25-akpm/include/asm-m68k/mac_asc.h | 8
25-akpm/include/asm-m68k/mac_oss.h | 2
25-akpm/include/asm-m68k/mac_psc.h | 12
25-akpm/include/asm-m68k/mac_via.h | 24
25-akpm/include/asm-m68k/machw.h | 2
25-akpm/include/asm-m68k/macintosh.h | 16
25-akpm/include/asm-m68k/macints.h | 8
25-akpm/include/asm-m68k/md.h | 4
25-akpm/include/asm-m68k/mmu_context.h | 4
25-akpm/include/asm-m68k/motorola_pgtable.h | 2
25-akpm/include/asm-m68k/msgbuf.h | 2
25-akpm/include/asm-m68k/mvme147hw.h | 2
25-akpm/include/asm-m68k/mvme16xhw.h | 2
25-akpm/include/asm-m68k/openprom.h | 88 -
25-akpm/include/asm-m68k/oplib.h | 8
25-akpm/include/asm-m68k/page.h | 6
25-akpm/include/asm-m68k/page_offset.h | 2
25-akpm/include/asm-m68k/q40_master.h | 4
25-akpm/include/asm-m68k/raw_io.h | 2
25-akpm/include/asm-m68k/rtc.h | 2
25-akpm/include/asm-m68k/sembuf.h | 2
25-akpm/include/asm-m68k/serial.h | 6
25-akpm/include/asm-m68k/setup.h | 2
25-akpm/include/asm-m68k/shmbuf.h | 2
25-akpm/include/asm-m68k/sigcontext.h | 2
25-akpm/include/asm-m68k/signal.h | 2
25-akpm/include/asm-m68k/sockios.h | 2
25-akpm/include/asm-m68k/string.h | 4
25-akpm/include/asm-m68k/sun3_pgalloc.h | 10
25-akpm/include/asm-m68k/sun3mmu.h | 4
25-akpm/include/asm-m68k/sun3x.h | 2
25-akpm/include/asm-m68k/sun3xflop.h | 28
25-akpm/include/asm-m68k/termios.h | 2
25-akpm/include/asm-m68k/thread_info.h | 2
25-akpm/include/asm-m68k/tlbflush.h | 10
25-akpm/include/asm-m68k/unaligned.h | 2
25-akpm/include/asm-m68k/user.h | 4
25-akpm/include/asm-m68k/virtconvert.h | 2
199 files changed, 3927 insertions(+), 3927 deletions(-)
diff -puN arch/m68k/amiga/amisound.c~m68k-superfluous-whitespace arch/m68k/amiga/amisound.c
--- 25/arch/m68k/amiga/amisound.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/amiga/amisound.c Thu Apr 22 13:43:13 2004
@@ -88,7 +88,7 @@ void amiga_mksound( unsigned int hz, uns
custom.aud[2].audlen = sizeof(sine_data)/2;
custom.aud[2].audper = (unsigned short)period;
custom.aud[2].audvol = 32; /* 50% of maxvol */
-
+
if (ticks) {
sound_timer.expires = jiffies + ticks;
add_timer( &sound_timer );
diff -puN arch/m68k/amiga/chipram.c~m68k-superfluous-whitespace arch/m68k/amiga/chipram.c
--- 25/arch/m68k/amiga/chipram.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/amiga/chipram.c Thu Apr 22 13:43:13 2004
@@ -42,7 +42,7 @@ void __init amiga_chip_init(void)
chipavail = amiga_chip_size;
}
-
+
void *amiga_chip_alloc(unsigned long size, const char *name)
{
struct resource *res;
diff -puN arch/m68k/amiga/config.c~m68k-superfluous-whitespace arch/m68k/amiga/config.c
--- 25/arch/m68k/amiga/config.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/amiga/config.c Thu Apr 22 13:43:13 2004
@@ -332,7 +332,7 @@ static void __init amiga_identify(void)
case AMI_DRACO:
panic("No support for Draco yet");
-
+
default:
panic("Unknown Amiga Model");
}
@@ -426,7 +426,7 @@ void __init config_amiga(void)
*/
mach_set_clock_mmss = amiga_set_clock_mmss;
- mach_get_ss = amiga_get_ss;
+ mach_get_ss = amiga_get_ss;
#ifdef CONFIG_AMIGA_FLOPPY
mach_floppy_setup = amiga_floppy_setup;
#endif
@@ -679,13 +679,13 @@ static int amiga_set_clock_mmss (unsigne
tod_3000.second2 = real_seconds % 10;
tod_3000.minute1 = real_minutes / 10;
tod_3000.minute2 = real_minutes % 10;
-
+
tod_3000.cntrl1 = TOD3000_CNTRL1_FREE;
} else /* if (AMIGAHW_PRESENT(A2000_CLK)) */ {
int cnt = 5;
tod_2000.cntrl1 |= TOD2000_CNTRL1_HOLD;
-
+
while ((tod_2000.cntrl1 & TOD2000_CNTRL1_BUSY) && cnt--)
{
tod_2000.cntrl1 &= ~TOD2000_CNTRL1_HOLD;
@@ -715,7 +715,7 @@ static unsigned int amiga_get_ss( void )
tod_3000.cntrl1 = TOD3000_CNTRL1_HOLD;
s = tod_3000.second1 * 10 + tod_3000.second2;
tod_3000.cntrl1 = TOD3000_CNTRL1_FREE;
- } else /* if (AMIGAHW_PRESENT(A2000_CLK)) */ {
+ } else /* if (AMIGAHW_PRESENT(A2000_CLK)) */ {
s = tod_2000.second1 * 10 + tod_2000.second2;
}
return s;
@@ -758,7 +758,7 @@ static void amiga_reset (void)
: "a" (jmp_addr));
jmp_addr_label040:
/* disable translation on '040 now */
- __asm__ __volatile__
+ __asm__ __volatile__
("moveq #0,%/d0\n\t"
".chip 68040\n\t"
"movec %%d0,%%tc\n\t" /* disable MMU */
@@ -783,7 +783,7 @@ static void amiga_reset (void)
"1:\n\t"
"reset\n\t"
"jmp %/a0@" : /* Just that gcc scans it for % escapes */ );
-
+
for (;;);
}
diff -puN arch/m68k/apollo/config.c~m68k-superfluous-whitespace arch/m68k/apollo/config.c
--- 25/arch/m68k/apollo/config.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/apollo/config.c Thu Apr 22 13:43:13 2004
@@ -62,19 +62,19 @@ int apollo_parse_bootinfo(const struct b
const unsigned long *data = record->data;
switch(record->tag) {
- case BI_APOLLO_MODEL:
- apollo_model=*data;
+ case BI_APOLLO_MODEL:
+ apollo_model=*data;
break;
default:
unknown=1;
}
-
+
return unknown;
}
void dn_setup_model(void) {
-
+
printk("Apollo hardware found: ");
printk("[%s]\n", apollo_models[apollo_model - APOLLO_DN3000]);
@@ -85,19 +85,19 @@ void dn_setup_model(void) {
break;
case APOLLO_DN3000:
case APOLLO_DN3010:
- sio01_physaddr=SAU8_SIO01_PHYSADDR;
- rtc_physaddr=SAU8_RTC_PHYSADDR;
- pica_physaddr=SAU8_PICA;
- picb_physaddr=SAU8_PICB;
+ sio01_physaddr=SAU8_SIO01_PHYSADDR;
+ rtc_physaddr=SAU8_RTC_PHYSADDR;
+ pica_physaddr=SAU8_PICA;
+ picb_physaddr=SAU8_PICB;
cpuctrl_physaddr=SAU8_CPUCTRL;
timer_physaddr=SAU8_TIMER;
break;
case APOLLO_DN4000:
- sio01_physaddr=SAU7_SIO01_PHYSADDR;
- sio23_physaddr=SAU7_SIO23_PHYSADDR;
- rtc_physaddr=SAU7_RTC_PHYSADDR;
- pica_physaddr=SAU7_PICA;
- picb_physaddr=SAU7_PICB;
+ sio01_physaddr=SAU7_SIO01_PHYSADDR;
+ sio23_physaddr=SAU7_SIO23_PHYSADDR;
+ rtc_physaddr=SAU7_RTC_PHYSADDR;
+ pica_physaddr=SAU7_PICA;
+ picb_physaddr=SAU7_PICB;
cpuctrl_physaddr=SAU7_CPUCTRL;
timer_physaddr=SAU7_TIMER;
break;
@@ -105,11 +105,11 @@ void dn_setup_model(void) {
panic("Apollo model not yet supported");
break;
case APOLLO_DN3500:
- sio01_physaddr=SAU7_SIO01_PHYSADDR;
- sio23_physaddr=SAU7_SIO23_PHYSADDR;
- rtc_physaddr=SAU7_RTC_PHYSADDR;
- pica_physaddr=SAU7_PICA;
- picb_physaddr=SAU7_PICB;
+ sio01_physaddr=SAU7_SIO01_PHYSADDR;
+ sio23_physaddr=SAU7_SIO23_PHYSADDR;
+ rtc_physaddr=SAU7_RTC_PHYSADDR;
+ pica_physaddr=SAU7_PICA;
+ picb_physaddr=SAU7_PICB;
cpuctrl_physaddr=SAU7_CPUCTRL;
timer_physaddr=SAU7_TIMER;
break;
@@ -131,17 +131,17 @@ int dn_serial_console_wait_key(struct co
void dn_serial_console_write (struct console *co, const char *str,unsigned int count)
{
while(count--) {
- if (*str == '\n') {
- sio01.rhrb_thrb = (unsigned char)'\r';
- while (!(sio01.srb_csrb & 0x4))
+ if (*str == '\n') {
+ sio01.rhrb_thrb = (unsigned char)'\r';
+ while (!(sio01.srb_csrb & 0x4))
;
- }
+ }
sio01.rhrb_thrb = (unsigned char)*str++;
while (!(sio01.srb_csrb & 0x4))
;
- }
+ }
}
-
+
void dn_serial_print (const char *str)
{
while (*str) {
@@ -160,7 +160,7 @@ void config_apollo(void) {
int i;
- dn_setup_model();
+ dn_setup_model();
mach_sched_init=dn_sched_init; /* */
mach_init_IRQ=dn_init_IRQ;
@@ -180,24 +180,24 @@ void config_apollo(void) {
conswitchp = &dummy_con;
#endif
#ifdef CONFIG_HEARTBEAT
- mach_heartbeat = dn_heartbeat;
+ mach_heartbeat = dn_heartbeat;
#endif
mach_get_model = dn_get_model;
cpuctrl=0xaa00;
/* clear DMA translation table */
- for(i=0;i<0x400;i++)
+ for(i=0;i<0x400;i++)
addr_xlat_map[i]=0;
-}
+}
irqreturn_t dn_timer_int(int irq, void *dev_id, struct pt_regs *fp) {
volatile unsigned char x;
sched_timer_handler(irq,dev_id,fp);
-
+
x=*(volatile unsigned char *)(timer+3);
x=*(volatile unsigned char *)(timer+5);
@@ -206,7 +206,7 @@ irqreturn_t dn_timer_int(int irq, void *
void dn_sched_init(irqreturn_t (*timer_routine)(int, void *, struct pt_regs *)) {
- /* program timer 1 */
+ /* program timer 1 */
*(volatile unsigned char *)(timer+3)=0x01;
*(volatile unsigned char *)(timer+1)=0x40;
*(volatile unsigned char *)(timer+5)=0x09;
@@ -272,7 +272,7 @@ void dn_dummy_reset(void) {
for(;;);
}
-
+
void dn_dummy_waitbut(void) {
dn_serial_print("waitbut\n");
@@ -291,7 +291,7 @@ static int dn_cpuctrl=0xff00;
static void dn_heartbeat(int on) {
- if(on) {
+ if(on) {
dn_cpuctrl&=~0x100;
cpuctrl=dn_cpuctrl;
}
diff -puN arch/m68k/apollo/dma.c~m68k-superfluous-whitespace arch/m68k/apollo/dma.c
--- 25/arch/m68k/apollo/dma.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/apollo/dma.c Thu Apr 22 13:43:13 2004
@@ -34,7 +34,7 @@ unsigned short dma_map_page(unsigned lon
next_free_xlat_entry+=2;
if(next_free_xlat_entry>125)
next_free_xlat_entry=0;
-
+
#if 0
printk("next_free_xlat_entry: %d\n",next_free_xlat_entry);
#endif
diff -puN arch/m68k/apollo/dn_debug.c~m68k-superfluous-whitespace arch/m68k/apollo/dn_debug.c
--- 25/arch/m68k/apollo/dn_debug.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/apollo/dn_debug.c Thu Apr 22 13:43:13 2004
@@ -14,9 +14,9 @@ int dn_deb_printf(const char *fmt, ...)
i=vsprintf(current_dbg_ptr,fmt,args);
va_end(args);
current_dbg_ptr+=i;
-
+
return i;
}
- else
+ else
return 0;
}
diff -puN arch/m68k/apollo/dn_ints.c~m68k-superfluous-whitespace arch/m68k/apollo/dn_ints.c
--- 25/arch/m68k/apollo/dn_ints.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/apollo/dn_ints.c Thu Apr 22 13:43:13 2004
@@ -40,7 +40,7 @@ void dn_init_IRQ(void) {
dn_irqs[i].dev_id=NULL;
dn_irqs[i].devname=NULL;
}
-
+
}
int dn_request_irq(unsigned int irq, irqreturn_t (*handler)(int, void *, struct pt_regs *), unsigned long flags, const char *devname, void *dev_id) {
@@ -79,7 +79,7 @@ void dn_free_irq(unsigned int irq, void
if(irq<8)
*(volatile unsigned char *)(pica+1)|=(1<<irq);
else
- *(volatile unsigned char *)(picb+1)|=(1<<(irq-8));
+ *(volatile unsigned char *)(picb+1)|=(1<<(irq-8));
dn_irqs[irq].handler=NULL;
dn_irqs[irq].flags=IRQ_FLG_STD;
diff -puN arch/m68k/atari/ataints.c~m68k-superfluous-whitespace arch/m68k/atari/ataints.c
--- 25/arch/m68k/atari/ataints.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/atari/ataints.c Thu Apr 22 13:43:13 2004
@@ -54,14 +54,14 @@
/*
* Atari interrupt handling scheme:
* --------------------------------
- *
+ *
* All interrupt source have an internal number (defined in
* <asm/atariints.h>): Autovector interrupts are 1..7, then follow ST-MFP,
* TT-MFP, SCC, and finally VME interrupts. Vector numbers for the latter can
* be allocated by atari_register_vme_int().
*
* Each interrupt can be of three types:
- *
+ *
* - SLOW: The handler runs with all interrupts enabled, except the one it
* was called by (to avoid reentering). This should be the usual method.
* But it is currently possible only for MFP ints, since only the MFP
@@ -179,16 +179,16 @@ __asm__ (__ALIGN_STR "\n" \
" movew %%d1,%%sr\n" /* set IPL = previous value */ \
" addql #1,%a0\n" \
" lea %a1,%%a0\n" \
-" pea %%sp@\n" /* push addr of frame */ \
+" pea %%sp@\n" /* push addr of frame */ \
" movel %%a0@(4),%%sp@-\n" /* push handler data */ \
-" pea (%c3+8)\n" /* push int number */ \
+" pea (%c3+8)\n" /* push int number */ \
" movel %%a0@,%%a0\n" \
" jbsr %%a0@\n" /* call the handler */ \
" addql #8,%%sp\n" \
" addql #4,%%sp\n" \
" orw #0x0600,%%sr\n" \
" andw #0xfeff,%%sr\n" /* set IPL = 6 again */ \
-" orb #(1<<(%c3&7)),%a4:w\n" /* now unmask the int again */ \
+" orb #(1<<(%c3&7)),%a4:w\n" /* now unmask the int again */ \
" jbra ret_from_interrupt\n" \
: : "i" (&kstat_cpu(0).irqs[n+8]), "i" (&irq_handler[n+8]), \
"n" (PT_OFF_SR), "n" (n), \
@@ -274,7 +274,7 @@ asmlinkage void atari_prio_irq_handler(
void atari_fast_prio_irq_dummy (void) {
__asm__ (__ALIGN_STR "\n"
"atari_fast_irq_handler:\n\t"
- "orw #0x700,%%sr\n" /* disable all interrupts */
+ "orw #0x700,%%sr\n" /* disable all interrupts */
"atari_prio_irq_handler:\n\t"
"addl %3,%2\n\t" /* preempt_count() += HARDIRQ_OFFSET */
SAVE_ALL_INT "\n\t"
@@ -282,13 +282,13 @@ __asm__ (__ALIGN_STR "\n"
/* get vector number from stack frame and convert to source */
"bfextu %%sp@(%c1){#4,#10},%%d0\n\t"
"subw #(0x40-8),%%d0\n\t"
- "jpl 1f\n\t"
+ "jpl 1f\n\t"
"addw #(0x40-8-0x18),%%d0\n"
"1:\tlea %a0,%%a0\n\t"
"addql #1,%%a0@(%%d0:l:4)\n\t"
"lea irq_handler,%%a0\n\t"
"lea %%a0@(%%d0:l:8),%%a0\n\t"
- "pea %%sp@\n\t" /* push frame address */
+ "pea %%sp@\n\t" /* push frame address */
"movel %%a0@(4),%%sp@-\n\t" /* push handler data */
"movel %%d0,%%sp@-\n\t" /* push int number */
"movel %%a0@,%%a0\n\t"
@@ -395,7 +395,7 @@ void __init atari_init_IRQ(void)
be in an atasound_init(), that doesn't exist yet. */
atari_microwire_cmd(MW_LM1992_PSG_HIGH);
}
-
+
stdma_init();
/* Initialize the PSG: all sounds off, both ports output */
@@ -460,7 +460,7 @@ int atari_request_irq(unsigned int irq,
__FUNCTION__, irq, devname);
return -EINVAL;
}
-
+
if (vectors[vector] == bad_interrupt) {
/* int has no handler yet */
irq_handler[irq].handler = handler;
@@ -594,7 +594,7 @@ unsigned long atari_register_vme_int(voi
for(i = 0; i < 32; i++)
if((free_vme_vec_bitmap & (1 << i)) == 0)
break;
-
+
if(i == 16)
return 0;
@@ -641,7 +641,7 @@ int show_atari_interrupts(struct seq_fil
}
if (num_spurious)
seq_printf(p, "spurio.: %10u\n", num_spurious);
-
+
return 0;
}
diff -puN arch/m68k/atari/atasound.c~m68k-superfluous-whitespace arch/m68k/atari/atasound.c
--- 25/arch/m68k/atari/atasound.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/atari/atasound.c Thu Apr 22 13:43:13 2004
@@ -70,7 +70,7 @@ void atari_mksound (unsigned int hz, uns
if (hz) {
/* Convert from frequency value to PSG period value (base
frequency 125 kHz). */
-
+
period = PSG_FREQ / hz;
if (period > 0xfff) period = 0xfff;
diff -puN arch/m68k/atari/config.c~m68k-superfluous-whitespace arch/m68k/atari/config.c
--- 25/arch/m68k/atari/config.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/atari/config.c Thu Apr 22 13:43:13 2004
@@ -7,7 +7,7 @@
* Added setting of time_adj to get a better clock.
*
* 5/14/94 Roman Hodek:
- * gettod() for TT
+ * gettod() for TT
*
* 5/15/94 Roman Hodek:
* hard_reset_now() for Atari (and others?)
@@ -92,7 +92,7 @@ extern void atari_debug_init(void);
* for posterity.
* -- Peter Maydell <pmaydell@chiark.greenend.org.uk>, 05/1998
*/
-
+
#if 0
static int __init
hwreg_present_bywrite(volatile void *regp, unsigned char val)
@@ -100,7 +100,7 @@ hwreg_present_bywrite(volatile void *reg
int ret;
long save_sp, save_vbr;
static long tmp_vectors[3] = { [2] = (long)&&after_test };
-
+
__asm__ __volatile__
( "movec %/vbr,%2\n\t" /* save vbr value */
"movec %4,%/vbr\n\t" /* set up temporary vectors */
@@ -141,14 +141,14 @@ static int __init scc_test( volatile cha
*ctla = 2; MFPDELAY();
*ctla = 0x40; MFPDELAY();
-
+
*ctla = 2; MFPDELAY();
if (*ctla != 0x40) return( 0 );
MFPDELAY();
*ctla = 2; MFPDELAY();
*ctla = 0x60; MFPDELAY();
-
+
*ctla = 2; MFPDELAY();
if (*ctla != 0x60) return( 0 );
@@ -199,7 +199,7 @@ void __init atari_switches_setup( const
p += 3;
ovsc_shift = ATARI_SWITCH_OVSC_SHIFT;
}
-
+
if (strcmp( p, "ikbd" ) == 0) {
/* RTS line of IKBD ACIA */
atari_switches |= ATARI_SWITCH_IKBD << ovsc_shift;
@@ -269,8 +269,8 @@ void __init config_atari(void)
((atari_switches&ATARI_SWITCH_SND6) ? 0x40 : 0) |
((atari_switches&ATARI_SWITCH_SND7) ? 0x80 : 0);
}
-
- /* ++bjoern:
+
+ /* ++bjoern:
* Determine hardware present
*/
@@ -446,7 +446,7 @@ void __init config_atari(void)
: /* no outputs */
: /* no inputs */
: "d0");
-
+
/* allocator for memory that must reside in st-ram */
atari_stram_init ();
@@ -507,7 +507,7 @@ static void atari_heartbeat( int on )
if (atari_dont_touch_floppy_select)
return;
-
+
local_irq_save(flags);
sound_ym.rd_data_reg_sel = 14; /* Select PSG Port A */
tmp = sound_ym.rd_data_reg_sel;
@@ -544,7 +544,7 @@ static void atari_heartbeat( int on )
* address of a C label. No hope to compile this with another compiler
* than GCC!
*/
-
+
/* ++andreas: no need for complicated code, just depend on prefetch */
static void atari_reset (void)
@@ -563,7 +563,7 @@ static void atari_reset (void)
acia.key_ctrl = ACIA_RESET;
if (atari_switches & ATARI_SWITCH_OVSC_MIDI)
acia.mid_ctrl = ACIA_RESET;
-
+
/* processor independent: turn off interrupts and reset the VBR;
* the caches must be left enabled, else prefetching the final jump
* instruction doesn't work. */
@@ -572,7 +572,7 @@ static void atari_reset (void)
("moveq #0,%/d0\n\t"
"movec %/d0,%/vbr"
: : : "d0" );
-
+
if (CPU_IS_040_OR_060) {
unsigned long jmp_addr040 = virt_to_phys(&&jmp_addr_label040);
if (CPU_IS_060) {
@@ -584,7 +584,7 @@ static void atari_reset (void)
".chip 68k"
: : : "d0" );
}
-
+
__asm__ __volatile__
("movel %0,%/d0\n\t"
"andl #0xff000000,%/d0\n\t"
diff -puN arch/m68k/atari/debug.c~m68k-superfluous-whitespace arch/m68k/atari/debug.c
--- 25/arch/m68k/atari/debug.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/atari/debug.c Thu Apr 22 13:43:13 2004
@@ -4,7 +4,7 @@
* Atari debugging and serial console stuff
*
* Assembled of parts of former atari/config.c 97-12-18 by Roman Hodek
- *
+ *
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
@@ -99,7 +99,7 @@ static int ata_par_out (char c)
while( (mfp.par_dt_reg & 1) && --i ) /* wait for BUSY == L */
;
if (!i) return( 0 );
-
+
sound_ym.rd_data_reg_sel = 15; /* select port B */
sound_ym.wd_data = c; /* put char onto port */
sound_ym.rd_data_reg_sel = 14; /* select port A */
@@ -177,7 +177,7 @@ void atari_init_mfp_port( int cflag )
if (baud < B1200 || baud > B38400+2)
baud = B9600; /* use default 9600bps for non-implemented rates */
baud -= B1200; /* baud_table[] starts at 1200bps */
-
+
mfp.trn_stat &= ~0x01; /* disable TX */
mfp.usart_ctr = parity | csize | 0x88; /* 1:16 clk mode, 1 stop bit */
mfp.tim_ct_cd &= 0x70; /* stop timer D */
@@ -204,7 +204,7 @@ void atari_init_mfp_port( int cflag )
for( i = 100; i > 0; --i ) \
MFPDELAY(); \
} while(0)
-
+
#ifndef CONFIG_SERIAL_CONSOLE
static void __init atari_init_scc_port( int cflag )
#else
@@ -214,20 +214,20 @@ void atari_init_scc_port( int cflag )
extern int atari_SCC_reset_done;
static int clksrc_table[9] =
/* reg 11: 0x50 = BRG, 0x00 = RTxC, 0x28 = TRxC */
- { 0x50, 0x50, 0x50, 0x50, 0x50, 0x50, 0x50, 0x00, 0x00 };
+ { 0x50, 0x50, 0x50, 0x50, 0x50, 0x50, 0x50, 0x00, 0x00 };
static int brgsrc_table[9] =
/* reg 14: 0 = RTxC, 2 = PCLK */
- { 2, 2, 2, 2, 2, 2, 0, 2, 2 };
+ { 2, 2, 2, 2, 2, 2, 0, 2, 2 };
static int clkmode_table[9] =
/* reg 4: 0x40 = x16, 0x80 = x32, 0xc0 = x64 */
- { 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0xc0, 0x80 };
+ { 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0xc0, 0x80 };
static int div_table[9] =
/* reg12 (BRG low) */
- { 208, 138, 103, 50, 24, 11, 1, 0, 0 };
+ { 208, 138, 103, 50, 24, 11, 1, 0, 0 };
int baud = cflag & CBAUD;
int clksrc, clkmode, div, reg3, reg5;
-
+
if (cflag & CBAUDEX)
baud += B38400;
if (baud < B1200 || baud > B38400+2)
@@ -248,7 +248,7 @@ void atari_init_scc_port( int cflag )
reg3 = (cflag & CSIZE) == CS8 ? 0xc0 : 0x40;
reg5 = (cflag & CSIZE) == CS8 ? 0x60 : 0x20 | 0x82 /* assert DTR/RTS */;
-
+
(void)scc.cha_b_ctrl; /* reset reg pointer */
SCC_WRITE( 9, 0xc0 ); /* reset */
LONG_DELAY(); /* extra delay after WR9 access */
@@ -267,12 +267,12 @@ void atari_init_scc_port( int cflag )
SCC_WRITE( 14, brgsrc_table[baud] | (div ? 1 : 0) );
SCC_WRITE( 3, reg3 | 1 );
SCC_WRITE( 5, reg5 | 8 );
-
+
atari_SCC_reset_done = 1;
atari_SCC_init_done = 1;
}
-#ifndef CONFIG_SERIAL_CONSOLE
+#ifndef CONFIG_SERIAL_CONSOLE
static void __init atari_init_midi_port( int cflag )
#else
void atari_init_midi_port( int cflag )
diff -puN arch/m68k/atari/stdma.c~m68k-superfluous-whitespace arch/m68k/atari/stdma.c
--- 25/arch/m68k/atari/stdma.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/atari/stdma.c Thu Apr 22 13:43:13 2004
@@ -97,7 +97,7 @@ void stdma_lock(irqreturn_t (*handler)(i
/*
* Function: void stdma_release( void )
*
- * Purpose: Releases the lock on the ST-DMA chip.
+ * Purpose: Releases the lock on the ST-DMA chip.
*
* Inputs: none
*
diff -puN arch/m68k/atari/stram.c~m68k-superfluous-whitespace arch/m68k/atari/stram.c
--- 25/arch/m68k/atari/stram.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/atari/stram.c Thu Apr 22 13:43:13 2004
@@ -52,7 +52,7 @@
/* Pre-swapping comments:
*
* ++roman:
- *
+ *
* New version of ST-Ram buffer allocation. Instead of using the
* 1 MB - 4 KB that remain when the ST-Ram chunk starts at $1000
* (1 MB granularity!), such buffers are reserved like this:
@@ -60,14 +60,14 @@
* - If the kernel resides in ST-Ram anyway, we can take the buffer
* from behind the current kernel data space the normal way
* (incrementing start_mem).
- *
+ *
* - If the kernel is in TT-Ram, stram_init() initializes start and
* end of the available region. Buffers are allocated from there
* and mem_init() later marks the such used pages as reserved.
* Since each TT-Ram chunk is at least 4 MB in size, I hope there
* won't be an overrun of the ST-Ram region by normal kernel data
* space.
- *
+ *
* For that, ST-Ram may only be allocated while kernel initialization
* is going on, or exactly: before mem_init() is called. There is also
* no provision now for freeing ST-Ram buffers. It seems that isn't
@@ -105,7 +105,7 @@
* visible on a TT, where the speed difference between ST- and TT-RAM isn't
* that dramatic, but it should on machines where TT-RAM is really much faster
* (e.g. Afterburner).
- *
+ *
* [1]: __get_free_pages() does a fine job if you only want one page, but if
* you want more (contiguous) pages, it can give you such a block only if
* there's already a free one. The algorithm can't try to free buffers or swap
@@ -318,7 +318,7 @@ void __init atari_stram_reserve_pages(vo
swap_end = swap_start + max_swap_size;
DPRINTK( "atari_stram_reserve_pages: swapping enabled; "
"swap=%p-%p\n", swap_start, swap_end);
-
+
/* reserve some amount of memory for maintainance of
* swapping itself: one page for each 2048 (PAGE_SIZE/2)
* swap pages. (2 bytes for each page) */
@@ -328,7 +328,7 @@ void __init atari_stram_reserve_pages(vo
/* correct swap_start if necessary */
if (swap_start + PAGE_SIZE == swap_data)
swap_start = start_mem - PAGE_SIZE;
-
+
if (!swap_init( start_mem, swap_data )) {
printk( KERN_ERR "ST-RAM swap space initialization failed\n" );
max_swap_size = 0;
@@ -368,13 +368,13 @@ void atari_stram_mem_init_hook (void)
/*
* This is main public interface: somehow allocate a ST-RAM block
* There are three strategies:
- *
+ *
* - If we're before mem_init(), we have to make a static allocation. The
* region is taken in the kernel data area (if the kernel is in ST-RAM) or
* from the start of ST-RAM (if the kernel is in TT-RAM) and added to the
* rsvd_stram_* region. The ST-RAM is somewhere in the middle of kernel
* address space in the latter case.
- *
+ *
* - If mem_init() already has been called and ST-RAM swapping is enabled,
* try to get the memory from the (pseudo) swap-space, either free already
* or by moving some other pages out of the swap.
@@ -383,7 +383,7 @@ void atari_stram_mem_init_hook (void)
* enabled, the only possibility is to try with __get_dma_pages(). This has
* the disadvantage that it's very hard to get more than 1 page, and it is
* likely to fail :-(
- *
+ *
*/
void *atari_stram_alloc(long size, const char *owner)
{
@@ -450,7 +450,7 @@ void atari_stram_free( void *addr )
}
DPRINTK( "atari_stram_free: found block (%p): size=%08lx, owner=%s, "
"flags=%02x\n", block, block->size, block->owner, block->flags );
-
+
#ifdef CONFIG_STRAM_SWAP
if (!max_swap_size) {
#endif
@@ -503,14 +503,14 @@ static int __init swap_init(void *start_
DPRINTK("swap_init(start_mem=%p, swap_data=%p)\n",
start_mem, swap_data);
-
+
/* need at least one page for swapping to (and this also isn't very
* much... :-) */
if (swap_end - swap_start < 2*PAGE_SIZE) {
printk( KERN_WARNING "stram_swap_init: swap space too small\n" );
return( 0 );
}
-
+
/* find free slot in swap_info */
for( p = swap_info, type = 0; type < nr_swapfiles; type++, p++ )
if (!(p->flags & SWP_USED))
@@ -531,7 +531,7 @@ static int __init swap_init(void *start_
fake_dentry.d_name.name = "stram (internal)";
fake_dentry.d_name.len = 16;
fake_vfsmnt.mnt_parent = &fake_vfsmnt;
-
+
p->flags = SWP_USED;
p->swap_file = &fake_dentry;
p->swap_vfsmnt = &fake_vfsmnt;
@@ -706,7 +706,7 @@ static void unswap_vma(struct vm_area_st
} while (start < end);
}
-static void unswap_process(struct mm_struct * mm, swp_entry_t entry,
+static void unswap_process(struct mm_struct * mm, swp_entry_t entry,
struct page *page)
{
struct vm_area_struct* vma;
@@ -799,7 +799,7 @@ static void *get_stram_region( unsigned
unsigned long start, total_free, region_free;
int err;
void *ret = NULL;
-
+
DPRINTK( "get_stram_region(n_pages=%lu)\n", n_pages );
down(&stram_swap_sem);
@@ -874,7 +874,7 @@ static void free_stram_region( unsigned
static int in_some_region(void *addr)
{
BLOCK *p;
-
+
for( p = alloc_list; p; p = p->next ) {
if (p->start <= addr && addr < p->start + p->size)
return( 1 );
@@ -920,7 +920,7 @@ static unsigned long find_free_region(un
/* don't need more free pages... :-) */
goto out;
}
-
+
/* now shift the window and look for the area where as much pages as
* possible are free */
while( tail < max ) {
@@ -1130,7 +1130,7 @@ static BLOCK *add_region( void *addr, un
static BLOCK *find_region( void *addr )
{
BLOCK *p;
-
+
for( p = alloc_list; p; p = p->next ) {
if (p->start == addr)
return( p );
@@ -1145,7 +1145,7 @@ static BLOCK *find_region( void *addr )
static int remove_region( BLOCK *block )
{
BLOCK **p;
-
+
for( p = &alloc_list; *p; p = &((*p)->next) )
if (*p == block) break;
if (!*p)
diff -puN arch/m68k/atari/time.c~m68k-superfluous-whitespace arch/m68k/atari/time.c
--- 25/arch/m68k/atari/time.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/atari/time.c Thu Apr 22 13:43:13 2004
@@ -4,7 +4,7 @@
* Atari time and real time clock stuff
*
* Assembled of parts of former atari/config.c 97-12-18 by Roman Hodek
- *
+ *
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
@@ -25,7 +25,7 @@ atari_sched_init(irqreturn_t (*timer_rou
/* set Timer C data Register */
mfp.tim_dt_c = INT_TICKS;
/* start timer C, div = 1:100 */
- mfp.tim_ct_cd = (mfp.tim_ct_cd & 15) | 0x60;
+ mfp.tim_ct_cd = (mfp.tim_ct_cd & 15) | 0x60;
/* install interrupt service routine for MFP Timer C */
request_irq(IRQ_MFP_TIMC, timer_routine, IRQ_TYPE_SLOW,
"timer", timer_routine);
@@ -34,7 +34,7 @@ atari_sched_init(irqreturn_t (*timer_rou
/* ++andreas: gettimeoffset fixed to check for pending interrupt */
#define TICK_SIZE 10000
-
+
/* This is always executed with interrupts disabled. */
unsigned long atari_gettimeoffset (void)
{
@@ -59,9 +59,9 @@ static void mste_read(struct MSTE_RTC *v
{
#define COPY(v) val->v=(mste_rtc.v & 0xf)
do {
- COPY(sec_ones) ; COPY(sec_tens) ; COPY(min_ones) ;
- COPY(min_tens) ; COPY(hr_ones) ; COPY(hr_tens) ;
- COPY(weekday) ; COPY(day_ones) ; COPY(day_tens) ;
+ COPY(sec_ones) ; COPY(sec_tens) ; COPY(min_ones) ;
+ COPY(min_tens) ; COPY(hr_ones) ; COPY(hr_tens) ;
+ COPY(weekday) ; COPY(day_ones) ; COPY(day_tens) ;
COPY(mon_ones) ; COPY(mon_tens) ; COPY(year_ones) ;
COPY(year_tens) ;
/* prevent from reading the clock while it changed */
@@ -73,9 +73,9 @@ static void mste_write(struct MSTE_RTC *
{
#define COPY(v) mste_rtc.v=val->v
do {
- COPY(sec_ones) ; COPY(sec_tens) ; COPY(min_ones) ;
- COPY(min_tens) ; COPY(hr_ones) ; COPY(hr_tens) ;
- COPY(weekday) ; COPY(day_ones) ; COPY(day_tens) ;
+ COPY(sec_ones) ; COPY(sec_tens) ; COPY(min_ones) ;
+ COPY(min_tens) ; COPY(hr_ones) ; COPY(hr_tens) ;
+ COPY(weekday) ; COPY(day_ones) ; COPY(day_tens) ;
COPY(mon_ones) ; COPY(mon_tens) ; COPY(year_ones) ;
COPY(year_tens) ;
/* prevent from writing the clock while it changed */
@@ -104,14 +104,14 @@ int atari_mste_hwclk( int op, struct rtc
int hour, year;
int hr24=0;
struct MSTE_RTC val;
-
+
mste_rtc.mode=(mste_rtc.mode | 1);
hr24=mste_rtc.mon_tens & 1;
mste_rtc.mode=(mste_rtc.mode & ~1);
if (op) {
/* write: prepare values */
-
+
val.sec_ones = t->tm_sec % 10;
val.sec_tens = t->tm_sec / 10;
val.min_ones = t->tm_min % 10;
@@ -160,8 +160,8 @@ int atari_mste_hwclk( int op, struct rtc
int atari_tt_hwclk( int op, struct rtc_time *t )
{
- int sec=0, min=0, hour=0, day=0, mon=0, year=0, wday=0;
- unsigned long flags;
+ int sec=0, min=0, hour=0, day=0, mon=0, year=0, wday=0;
+ unsigned long flags;
unsigned char ctrl;
int pm = 0;
@@ -170,7 +170,7 @@ int atari_tt_hwclk( int op, struct rtc_t
if (op) {
/* write: prepare values */
-
+
sec = t->tm_sec;
min = t->tm_min;
hour = t->tm_hour;
@@ -178,7 +178,7 @@ int atari_tt_hwclk( int op, struct rtc_t
mon = t->tm_mon + 1;
year = t->tm_year - atari_rtc_year_offset;
wday = t->tm_wday + (t->tm_wday >= 0);
-
+
if (!(ctrl & RTC_24H)) {
if (hour > 11) {
pm = 0x80;
@@ -188,7 +188,7 @@ int atari_tt_hwclk( int op, struct rtc_t
else if (hour == 0)
hour = 12;
}
-
+
if (!(ctrl & RTC_DM_BINARY)) {
BIN_TO_BCD(sec);
BIN_TO_BCD(min);
@@ -199,7 +199,7 @@ int atari_tt_hwclk( int op, struct rtc_t
if (wday >= 0) BIN_TO_BCD(wday);
}
}
-
+
/* Reading/writing the clock registers is a bit critical due to
* the regular update cycle of the RTC. While an update is in
* progress, registers 0..9 shouldn't be touched.
@@ -242,7 +242,7 @@ int atari_tt_hwclk( int op, struct rtc_t
if (!op) {
/* read: adjust values */
-
+
if (hour & 0x80) {
hour &= ~0x80;
pm = 1;
@@ -284,7 +284,7 @@ int atari_mste_set_clock_mmss (unsigned
struct MSTE_RTC val;
unsigned char rtc_minutes;
- mste_read(&val);
+ mste_read(&val);
rtc_minutes= val.min_ones + val.min_tens * 10;
if ((rtc_minutes < real_minutes
? real_minutes - rtc_minutes
diff -puN arch/m68k/bvme6000/rtc.c~m68k-superfluous-whitespace arch/m68k/bvme6000/rtc.c
--- 25/arch/m68k/bvme6000/rtc.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/bvme6000/rtc.c Thu Apr 22 13:43:13 2004
@@ -44,7 +44,7 @@ static int rtc_ioctl(struct inode *inode
volatile RtcPtr_t rtc = (RtcPtr_t)BVME_RTC_BASE;
unsigned char msr;
unsigned long flags;
- struct rtc_time wtime;
+ struct rtc_time wtime;
switch (cmd) {
case RTC_RD_TIME: /* Read the time/date from RTC */
@@ -105,7 +105,7 @@ static int rtc_ioctl(struct inode *inode
if (yrs >= 2070)
return -EINVAL;
-
+
local_irq_save(flags);
/* Ensure clock and real-time-mode-register are accessible */
msr = rtc->msr & 0xc0;
diff -puN arch/m68k/defconfig~m68k-superfluous-whitespace arch/m68k/defconfig
--- 25/arch/m68k/defconfig~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/defconfig Thu Apr 22 13:43:13 2004
@@ -101,7 +101,7 @@ CONFIG_INET=y
# CONFIG_ATM is not set
#
-#
+#
#
# CONFIG_IPX is not set
# CONFIG_ATALK is not set
diff -puN arch/m68k/fpsp040/bindec.S~m68k-superfluous-whitespace arch/m68k/fpsp040/bindec.S
--- 25/arch/m68k/fpsp040/bindec.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/bindec.S Thu Apr 22 13:43:13 2004
@@ -19,7 +19,7 @@
|
| Algorithm:
|
-| A1. Set RM and size ext; Set SIGMA = sign of input.
+| A1. Set RM and size ext; Set SIGMA = sign of input.
| The k-factor is saved for use in d7. Clear the
| BINDEC_FLG for separating normalized/denormalized
| input. If input is unnormalized or denormalized,
@@ -29,15 +29,15 @@
|
| A3. Compute ILOG.
| ILOG is the log base 10 of the input value. It is
-| approximated by adding e + 0.f when the original
-| value is viewed as 2^^e * 1.f in extended precision.
+| approximated by adding e + 0.f when the original
+| value is viewed as 2^^e * 1.f in extended precision.
| This value is stored in d6.
|
| A4. Clr INEX bit.
-| The operation in A3 above may have set INEX2.
+| The operation in A3 above may have set INEX2.
|
| A5. Set ICTR = 0;
-| ICTR is a flag used in A13. It must be set before the
+| ICTR is a flag used in A13. It must be set before the
| loop entry A6.
|
| A6. Calculate LEN.
@@ -59,9 +59,9 @@
| of ISCALE and X. A table is given in the code.
|
| A8. Clr INEX; Force RZ.
-| The operation in A3 above may have set INEX2.
+| The operation in A3 above may have set INEX2.
| RZ mode is forced for the scaling operation to insure
-| only one rounding error. The grs bits are collected in
+| only one rounding error. The grs bits are collected in
| the INEX flag for use in A10.
|
| A9. Scale X -> Y.
@@ -90,11 +90,11 @@
| the mantissa by 10.
|
| A14. Convert the mantissa to bcd.
-| The binstr routine is used to convert the LEN digit
+| The binstr routine is used to convert the LEN digit
| mantissa to bcd in memory. The input to binstr is
| to be a fraction; i.e. (mantissa)/10^LEN and adjusted
| such that the decimal point is to the left of bit 63.
-| The bcd digits are stored in the correct position in
+| The bcd digits are stored in the correct position in
| the final string area in memory.
|
| A15. Convert the exponent to bcd.
@@ -114,7 +114,7 @@
| d2: upper 32-bits of mantissa for binstr
| d3: scratch;lower 32-bits of mantissa for binstr
| d4: LEN
-| d5: LAMBDA/ICTR
+| d5: LAMBDA/ICTR
| d6: ILOG
| d7: k-factor
| a0: ptr for original operand/final result
@@ -131,8 +131,8 @@
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
|BINDEC idnt 2,1 | Motorola 040 Floating Point Software Package
@@ -142,16 +142,16 @@
|section 8
| Constants in extended precision
-LOG2: .long 0x3FFD0000,0x9A209A84,0xFBCFF798,0x00000000
+LOG2: .long 0x3FFD0000,0x9A209A84,0xFBCFF798,0x00000000
LOG2UP1: .long 0x3FFD0000,0x9A209A84,0xFBCFF799,0x00000000
| Constants in single precision
-FONE: .long 0x3F800000,0x00000000,0x00000000,0x00000000
+FONE: .long 0x3F800000,0x00000000,0x00000000,0x00000000
FTWO: .long 0x40000000,0x00000000,0x00000000,0x00000000
-FTEN: .long 0x41200000,0x00000000,0x00000000,0x00000000
+FTEN: .long 0x41200000,0x00000000,0x00000000,0x00000000
F4933: .long 0x459A2800,0x00000000,0x00000000,0x00000000
-RBDTBL: .byte 0,0,0,0
+RBDTBL: .byte 0,0,0,0
.byte 3,3,2,2
.byte 3,2,2,3
.byte 2,3,3,2
@@ -171,7 +171,7 @@ bindec:
| separating normalized/denormalized input. If the input
| is a denormalized number, set the BINDEC_FLG memory word
| to signal denorm. If the input is unnormalized, normalize
-| the input and test for denormalized result.
+| the input and test for denormalized result.
|
fmovel #rm_mode,%FPCR |set RM and ext
movel (%a0),L_SCR2(%a6) |save exponent for sign check
@@ -251,7 +251,7 @@ A3_cont:
subw #0x3fff,%d0 |strip off bias
faddw %d0,%fp0 |add in exp
fsubs FONE,%fp0 |subtract off 1.0
- fbge pos_res |if pos, branch
+ fbge pos_res |if pos, branch
fmulx LOG2UP1,%fp0 |if neg, mul by LOG2UP1
fmovel %fp0,%d6 |put ILOG in d6 as a lword
bras A4_str |go move out ILOG
@@ -261,14 +261,14 @@ pos_res:
| A4. Clr INEX bit.
-| The operation in A3 above may have set INEX2.
+| The operation in A3 above may have set INEX2.
-A4_str:
+A4_str:
fmovel #0,%FPSR |zero all of fpsr - nothing needed
| A5. Set ICTR = 0;
-| ICTR is a flag used in A13. It must be set before the
+| ICTR is a flag used in A13. It must be set before the
| loop entry A6. The lower word of d5 is used for ICTR.
clrw %d5 |clear ICTR
@@ -303,7 +303,7 @@ A4_str:
| L_SCR1:x/x
| L_SCR2:first word of X packed/Unchanged
-A6_str:
+A6_str:
tstl %d7 |branch on sign of k
bles k_neg |if k <= 0, LEN = ILOG + 1 - k
movel %d7,%d4 |if k > 0, LEN = k
@@ -375,13 +375,13 @@ LEN_ng:
| L_SCR1:x/x
| L_SCR2:first word of X packed/Unchanged
-A7_str:
+A7_str:
tstl %d7 |test sign of k
bgts k_pos |if pos and > 0, skip this
cmpl %d6,%d7 |test k - ILOG
blts k_pos |if ILOG >= k, skip this
movel %d7,%d6 |if ((k<0) & (ILOG < k)) ILOG = k
-k_pos:
+k_pos:
movel %d6,%d0 |calc ILOG + 1 - LEN in d0
addql #1,%d0 |add the 1
subl %d4,%d0 |sub off LEN
@@ -395,9 +395,9 @@ k_pos:
bgts no_inf |if false, skip rest
addil #24,%d0 |add in 24 to iscale
movel #24,%d2 |put 24 in d2 for A9
-no_inf:
+no_inf:
negl %d0 |and take abs of ISCALE
-iscale:
+iscale:
fmoves FONE,%fp1 |init fp1 to 1
bfextu USER_FPCR(%a6){#26:#2},%d1 |get initial rmode bits
lslw #1,%d1 |put them in bits 2:1
@@ -425,33 +425,33 @@ not_rp:
leal PTENRM,%a1 |load a1 with RM table base
rmode:
clrl %d3 |clr table index
-e_loop:
+e_loop:
lsrl #1,%d0 |shift next bit into carry
bccs e_next |if zero, skip the mul
fmulx (%a1,%d3),%fp1 |mul by 10**(d3_bit_no)
-e_next:
+e_next:
addl #12,%d3 |inc d3 to next pwrten table entry
tstl %d0 |test if ISCALE is zero
bnes e_loop |if not, loop
| A8. Clr INEX; Force RZ.
-| The operation in A3 above may have set INEX2.
+| The operation in A3 above may have set INEX2.
| RZ mode is forced for the scaling operation to insure
-| only one rounding error. The grs bits are collected in
+| only one rounding error. The grs bits are collected in
| the INEX flag for use in A10.
|
| Register usage:
| Input/Output
- fmovel #0,%FPSR |clr INEX
+ fmovel #0,%FPSR |clr INEX
fmovel #rz_mode,%FPCR |set RZ rounding mode
| A9. Scale X -> Y.
| The mantissa is scaled to the desired number of significant
| digits. The excess digits are collected in INEX2. If mul,
-| Check d2 for excess 10 exponential value. If not zero,
+| Check d2 for excess 10 exponential value. If not zero,
| the iscale value would have caused the pwrten calculation
| to overflow. Only a negative iscale can cause this, so
| multiply by 10^(d2), which is now only allowed to be 24,
@@ -480,7 +480,7 @@ e_next:
| L_SCR1:x/x
| L_SCR2:first word of X packed/Unchanged
-A9_str:
+A9_str:
fmovex (%a0),%fp0 |load X from memory
fabsx %fp0 |use abs(X)
tstw %d5 |LAMBDA is in lower word of d5
@@ -498,9 +498,9 @@ sc_mul:
movel #18,%d3 |load count for busy stack
A9_loop:
clrl -(%a7) |clear lword on stack
- dbf %d3,A9_loop
+ dbf %d3,A9_loop
moveb VER_TMP(%a6),(%a7) |write current version number
- moveb #BUSY_SIZE-4,1(%a7) |write current busy size
+ moveb #BUSY_SIZE-4,1(%a7) |write current busy size
moveb #0x10,0x44(%a7) |set fcefpte[15] bit
movew #0x0023,0x40(%a7) |load cmdreg1b with mul command
moveb #0xfe,0x8(%a7) |load all 1s to cu savepc
@@ -537,7 +537,7 @@ A9_con:
| fp1: 10^ISCALE/Unchanged
| fp2: x/x
-A10_st:
+A10_st:
fmovel %FPSR,%d0 |get FPSR
fmovex %fp0,FP_SCR2(%a6) |move Y to memory
leal FP_SCR2(%a6),%a2 |load a2 with ptr to FP_SCR2
@@ -553,9 +553,9 @@ A10_st:
| routine expects the FPCR value to be in USER_FPCR for
| mode and precision. The original FPCR is saved in L_SCR1.
-A11_st:
+A11_st:
movel USER_FPCR(%a6),L_SCR1(%a6) |save it for later
- andil #0x00000030,USER_FPCR(%a6) |set size to ext,
+ andil #0x00000030,USER_FPCR(%a6) |set size to ext,
| ;block exceptions
@@ -584,13 +584,13 @@ A11_st:
| L_SCR2:first word of X packed/Unchanged
A12_st:
- moveml %d0-%d1/%a0-%a1,-(%a7) |save regs used by sintd0
+ moveml %d0-%d1/%a0-%a1,-(%a7) |save regs used by sintd0
movel L_SCR1(%a6),-(%a7)
movel L_SCR2(%a6),-(%a7)
leal FP_SCR2(%a6),%a0 |a0 is ptr to F_SCR2(a6)
fmovex %fp0,(%a0) |move Y to memory at FP_SCR2(a6)
tstl L_SCR2(%a6) |test sign of original operand
- bges do_fint |if pos, use Y
+ bges do_fint |if pos, use Y
orl #0x80000000,(%a0) |if neg, use -Y
do_fint:
movel USER_FPSR(%a6),-(%a7)
@@ -599,7 +599,7 @@ do_fint:
addl #4,%a7
movel (%a7)+,L_SCR2(%a6)
movel (%a7)+,L_SCR1(%a6)
- moveml (%a7)+,%d0-%d1/%a0-%a1 |restore regs used by sint
+ moveml (%a7)+,%d0-%d1/%a0-%a1 |restore regs used by sint
movel L_SCR2(%a6),FP_SCR2(%a6) |restore original exponent
movel L_SCR1(%a6),USER_FPCR(%a6) |restore user's FPCR
@@ -635,7 +635,7 @@ do_fint:
| L_SCR1:original USER_FPCR/Unchanged
| L_SCR2:first word of X packed/Unchanged
-A13_st:
+A13_st:
swap %d5 |put ICTR in lower word of d5
tstw %d5 |check if ICTR = 0
bne not_zr |if non-zero, go to second test
@@ -646,7 +646,7 @@ A13_st:
movel %d4,%d0 |put LEN in d0
subql #1,%d0 |d0 = LEN -1
clrl %d3 |clr table index
-l_loop:
+l_loop:
lsrl #1,%d0 |shift next bit into carry
bccs l_next |if zero, skip the mul
fmulx (%a1,%d3),%fp2 |mul by 10**(d3_bit_no)
@@ -672,7 +672,7 @@ A13_con:
subql #1,%d6 |subtract 1 from ILOG
movew #1,%d5 |set ICTR
fmovel #rm_mode,%FPCR |set rmode to RM
- fmuls FTEN,%fp2 |compute 10^LEN
+ fmuls FTEN,%fp2 |compute 10^LEN
bra A6_str |return to A6 and recompute YINT
test_2:
fmuls FTEN,%fp2 |compute 10^LEN
@@ -688,7 +688,7 @@ fix_ex:
fmovel #rm_mode,%FPCR |set rmode to RM
bra A6_str |return to A6 and recompute YINT
|
-| Since ICTR <> 0, we have already been through one adjustment,
+| Since ICTR <> 0, we have already been through one adjustment,
| and shouldn't have another; this is to check if abs(YINT) = 10^LEN
| 10^LEN is again computed using whatever table is in a1 since the
| value calculated cannot be inexact.
@@ -715,11 +715,11 @@ z_next:
| A14. Convert the mantissa to bcd.
-| The binstr routine is used to convert the LEN digit
+| The binstr routine is used to convert the LEN digit
| mantissa to bcd in memory. The input to binstr is
| to be a fraction; i.e. (mantissa)/10^LEN and adjusted
| such that the decimal point is to the left of bit 63.
-| The bcd digits are stored in the correct position in
+| The bcd digits are stored in the correct position in
| the final string area in memory.
|
|
@@ -745,7 +745,7 @@ z_next:
| L_SCR1:original USER_FPCR/Unchanged
| L_SCR2:first word of X packed/Unchanged
-A14_st:
+A14_st:
fmovel #rz_mode,%FPCR |force rz for conversion
fdivx %fp2,%fp0 |divide abs(YINT) by 10^LEN
leal FP_SCR1(%a6),%a0
@@ -762,7 +762,7 @@ A14_st:
bgts no_sft |if so, don't shift
negl %d0 |make exp positive
m_loop:
- lsrl #1,%d2 |shift d2:d3 right, add 0s
+ lsrl #1,%d2 |shift d2:d3 right, add 0s
roxrl #1,%d3 |the number of places
dbf %d0,m_loop |given in d0
no_sft:
@@ -787,9 +787,9 @@ zer_m:
|
| Digits are stored in L_SCR1(a6) on return from BINDEC as:
|
-| 32 16 15 0
+| 32 16 15 0
| -----------------------------------------
-| | 0 | e3 | e2 | e1 | e4 | X | X | X |
+| | 0 | e3 | e2 | e1 | e4 | X | X | X |
| -----------------------------------------
|
| And are moved into their proper places in FP_SCR1. If digit e4
@@ -817,7 +817,7 @@ zer_m:
| L_SCR1:original USER_FPCR/Exponent digits on return from binstr
| L_SCR2:first word of X packed/Unchanged
-A15_st:
+A15_st:
tstb BINDEC_FLG(%a6) |check for denorm
beqs not_denorm
ftstx %fp0 |test for zero
@@ -839,7 +839,7 @@ not_denorm:
fbne not_zero |if zero, force exponent
fmoves FONE,%fp0 |force exponent to 1
bras convrt |do it
-not_zero:
+not_zero:
fmovel %d6,%fp0 |float ILOG
fabsx %fp0 |get abs of ILOG
convrt:
@@ -852,7 +852,7 @@ convrt:
subiw #0x3ffd,%d0 |subtract off bias
negw %d0 |make exp positive
x_loop:
- lsrl #1,%d2 |shift d2:d3 right
+ lsrl #1,%d2 |shift d2:d3 right
roxrl #1,%d3 |the number of places
dbf %d0,x_loop |given in d0
x_loop_fin:
@@ -863,12 +863,12 @@ x_loop_fin:
movel #4,%d0 |put 4 in d0 for binstr call
leal L_SCR1(%a6),%a0 |a0 is ptr to L_SCR1 for exp digits
bsr binstr |call binstr to convert exp
- movel L_SCR1(%a6),%d0 |load L_SCR1 lword to d0
+ movel L_SCR1(%a6),%d0 |load L_SCR1 lword to d0
movel #12,%d1 |use d1 for shift count
lsrl %d1,%d0 |shift d0 right by 12
bfins %d0,FP_SCR1(%a6){#4:#12} |put e3:e2:e1 in FP_SCR1
lsrl %d1,%d0 |shift d0 right by 12
- bfins %d0,FP_SCR1(%a6){#16:#4} |put e4 in FP_SCR1
+ bfins %d0,FP_SCR1(%a6){#16:#4} |put e4 in FP_SCR1
tstb %d0 |check if e4 is zero
beqs A16_st |if zero, skip rest
orl #opaop_mask,USER_FPSR(%a6) |set OPERR & AIOP in USER_FPSR
@@ -899,14 +899,14 @@ x_loop_fin:
A16_st:
clrl %d0 |clr d0 for collection of signs
- andib #0x0f,FP_SCR1(%a6) |clear first nibble of FP_SCR1
+ andib #0x0f,FP_SCR1(%a6) |clear first nibble of FP_SCR1
tstl L_SCR2(%a6) |check sign of original mantissa
bges mant_p |if pos, don't set SM
moveql #2,%d0 |move 2 in to d0 for SM
mant_p:
tstl %d6 |check sign of ILOG
bges wr_sgn |if pos, don't set SE
- addql #1,%d0 |set bit 0 in d0 for SE
+ addql #1,%d0 |set bit 0 in d0 for SE
wr_sgn:
bfins %d0,FP_SCR1(%a6){#0:#2} |insert SM and SE into FP_SCR1
diff -puN arch/m68k/fpsp040/binstr.S~m68k-superfluous-whitespace arch/m68k/fpsp040/binstr.S
--- 25/arch/m68k/fpsp040/binstr.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/binstr.S Thu Apr 22 13:43:13 2004
@@ -60,8 +60,8 @@
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
|BINSTR idnt 2,1 | Motorola 040 Floating Point Software Package
diff -puN arch/m68k/fpsp040/bugfix.S~m68k-superfluous-whitespace arch/m68k/fpsp040/bugfix.S
--- 25/arch/m68k/fpsp040/bugfix.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/bugfix.S Thu Apr 22 13:43:13 2004
@@ -7,7 +7,7 @@
|
| Fixes for bugs: 1238
|
-| Bug: 1238
+| Bug: 1238
|
|
| /* The following dirty_bit clear should be left in
@@ -152,8 +152,8 @@
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
|BUGFIX idnt 2,1 | Motorola 040 Floating Point Software Package
@@ -167,8 +167,8 @@
.global b1238_fix
b1238_fix:
|
-| This code is entered only on completion of the handling of an
-| nu-generated ovfl, unfl, or inex exception. If the version
+| This code is entered only on completion of the handling of an
+| nu-generated ovfl, unfl, or inex exception. If the version
| number of the fsave is not $40, this handler is not necessary.
| Simply branch to fix_done and exit normally.
|
@@ -180,11 +180,11 @@ b1238_fix:
|
moveb CU_SAVEPC(%a6),%d0
andib #0xFE,%d0
- beq fix_done |if zero, this is not bug #1238
+ beq fix_done |if zero, this is not bug #1238
|
| Test the register conflict aspect. If opclass0, check for
-| cu src equal to xu dest or equal to nu dest. If so, go to
+| cu src equal to xu dest or equal to nu dest. If so, go to
| op0. Else, or if opclass2, check for cu dest equal to
| xu dest or equal to nu dest. If so, go to tst_opcl. Else,
| exit, it is not the bug case.
@@ -196,17 +196,17 @@ b1238_fix:
bne op2sgl |not opclass 0, check op2
|
| Check for cu and nu register conflict. If one exists, this takes
-| priority over a cu and xu conflict.
+| priority over a cu and xu conflict.
|
- bfextu CMDREG1B(%a6){#3:#3},%d0 |get 1st src
+ bfextu CMDREG1B(%a6){#3:#3},%d0 |get 1st src
bfextu CMDREG3B(%a6){#6:#3},%d1 |get 3rd dest
cmpb %d0,%d1
beqs op0 |if equal, continue bugfix
|
-| Check for cu dest equal to nu dest. If so, go and fix the
+| Check for cu dest equal to nu dest. If so, go and fix the
| bug condition. Otherwise, exit.
|
- bfextu CMDREG1B(%a6){#6:#3},%d0 |get 1st dest
+ bfextu CMDREG1B(%a6){#6:#3},%d0 |get 1st dest
cmpb %d0,%d1 |cmp 1st dest with 3rd dest
beqs op0 |if equal, continue bugfix
|
@@ -215,7 +215,7 @@ b1238_fix:
bfextu CMDREG2B(%a6){#6:#3},%d1 |get 2nd dest
cmpb %d0,%d1 |cmp 1st dest with 2nd dest
beqs op0_xu |if equal, continue bugfix
- bfextu CMDREG1B(%a6){#3:#3},%d0 |get 1st src
+ bfextu CMDREG1B(%a6){#3:#3},%d0 |get 1st src
cmpb %d0,%d1 |cmp 1st src with 2nd dest
beq op0_xu
bne fix_done |if the reg checks fail, exit
@@ -245,7 +245,7 @@ setete15:
|
| We have the case in which a conflict exists between the cu src or
-| dest and the dest of the xu. We must clear the instruction in
+| dest and the dest of the xu. We must clear the instruction in
| the cu and restore the state, allowing the instruction in the
| xu to complete. Remember, the instruction in the nu
| was exceptional, and was completed by the appropriate handler.
@@ -255,7 +255,7 @@ setete15:
| exceptional, we choose to kill the process.
|
| Items saved from the stack:
-|
+|
| $3c stag - L_SCR1
| $40 cmdreg1b - L_SCR2
| $44 dtag - L_SCR3
@@ -264,8 +264,8 @@ setete15:
| fpu.
|
op0_xu:
- movel STAG(%a6),L_SCR1(%a6)
- movel CMDREG1B(%a6),L_SCR2(%a6)
+ movel STAG(%a6),L_SCR1(%a6)
+ movel CMDREG1B(%a6),L_SCR2(%a6)
movel DTAG(%a6),L_SCR3(%a6)
andil #0xe0000000,L_SCR3(%a6)
moveb #0,CU_SAVEPC(%a6)
@@ -274,13 +274,13 @@ op0_xu:
fsave -(%a7)
|
| Check if the instruction which just completed was exceptional.
-|
+|
cmpw #0x4060,(%a7)
beq op0_xb
-|
+|
| It is necessary to isolate the result of the instruction in the
| xu if it is to fp0 - fp3 and write that value to the USER_FPn
-| locations on the stack. The correct destination register is in
+| locations on the stack. The correct destination register is in
| cmdreg2b.
|
bfextu CMDREG2B(%a6){#6:#3},%d0 |get dest register no
@@ -339,7 +339,7 @@ op0_sete15:
|
| The frame returned is busy. It is not possible to reconstruct
-| the code sequence to allow completion. We will jump to
+| the code sequence to allow completion. We will jump to
| fpsp_fmt_error and allow the kernel to kill the process.
|
op0_xb:
@@ -354,20 +354,20 @@ op2sgl:
cmpiw #0x4400,%d0 |test for opclass 2 and size=sgl
bne fix_done |if not, it is not bug 1238
|
-| Check for cu dest equal to nu dest or equal to xu dest, with
+| Check for cu dest equal to nu dest or equal to xu dest, with
| a cu and nu conflict taking priority an nu conflict. If either,
| go and fix the bug condition. Otherwise, exit.
|
- bfextu CMDREG1B(%a6){#6:#3},%d0 |get 1st dest
+ bfextu CMDREG1B(%a6){#6:#3},%d0 |get 1st dest
bfextu CMDREG3B(%a6){#6:#3},%d1 |get 3rd dest
cmpb %d0,%d1 |cmp 1st dest with 3rd dest
beq op2_com |if equal, continue bugfix
- bfextu CMDREG2B(%a6){#6:#3},%d1 |get 2nd dest
+ bfextu CMDREG2B(%a6){#6:#3},%d1 |get 2nd dest
cmpb %d0,%d1 |cmp 1st dest with 2nd dest
bne fix_done |if the reg checks fail, exit
|
| We have the case in which a conflict exists between the cu src or
-| dest and the dest of the xu. We must clear the instruction in
+| dest and the dest of the xu. We must clear the instruction in
| the cu and restore the state, allowing the instruction in the
| xu to complete. Remember, the instruction in the nu
| was exceptional, and was completed by the appropriate handler.
@@ -377,7 +377,7 @@ op2sgl:
| exceptional, we choose to kill the process.
|
| Items saved from the stack:
-|
+|
| $3c stag - L_SCR1
| $40 cmdreg1b - L_SCR2
| $44 dtag - L_SCR3
@@ -387,9 +387,9 @@ op2sgl:
| fpu.
|
op2_xu:
- movel STAG(%a6),L_SCR1(%a6)
- movel CMDREG1B(%a6),L_SCR2(%a6)
- movel DTAG(%a6),L_SCR3(%a6)
+ movel STAG(%a6),L_SCR1(%a6)
+ movel CMDREG1B(%a6),L_SCR2(%a6)
+ movel DTAG(%a6),L_SCR3(%a6)
andil #0xe0000000,L_SCR3(%a6)
moveb #0,CU_SAVEPC(%a6)
movel ETEMP(%a6),FP_SCR2(%a6)
@@ -400,13 +400,13 @@ op2_xu:
fsave -(%a7)
|
| Check if the instruction which just completed was exceptional.
-|
+|
cmpw #0x4060,(%a7)
beq op2_xb
-|
+|
| It is necessary to isolate the result of the instruction in the
| xu if it is to fp0 - fp3 and write that value to the USER_FPn
-| locations on the stack. The correct destination register is in
+| locations on the stack. The correct destination register is in
| cmdreg2b.
|
bfextu CMDREG2B(%a6){#6:#3},%d0 |get dest register no
@@ -459,12 +459,12 @@ op2_com:
bnes case2
movew #0x43FF,ETEMP_EX(%a6) |to double +max
bra finish
-case2:
+case2:
cmpw #0xC07F,ETEMP_EX(%a6) |single -max
bnes case3
movew #0xC3FF,ETEMP_EX(%a6) |to double -max
bra finish
-case3:
+case3:
cmpw #0x3F80,ETEMP_EX(%a6) |single +min
bnes case4
movew #0x3C00,ETEMP_EX(%a6) |to double +min
@@ -480,7 +480,7 @@ case4:
| an fline illegal instruction to be executed.
|
| You should replace the jump to fpsp_fmt_error with a jump
-| to the entry point used to kill a process.
+| to the entry point used to kill a process.
|
op2_xb:
jmp fpsp_fmt_error
diff -puN arch/m68k/fpsp040/decbin.S~m68k-superfluous-whitespace arch/m68k/fpsp040/decbin.S
--- 25/arch/m68k/fpsp040/decbin.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/decbin.S Thu Apr 22 13:43:13 2004
@@ -60,17 +60,17 @@
| it is negative.
|
| Clean up and return. Check if the final mul or div resulted
-| in an inex2 exception. If so, set inex1 in the fpsr and
+| in an inex2 exception. If so, set inex1 in the fpsr and
| check if the inex1 exception is enabled. If so, set d7 upper
| word to $0100. This will signal unimp.sa that an enabled inex1
| exception occurred. Unimp will fix the stack.
-|
+|
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
|DECBIN idnt 2,1 | Motorola 040 Floating Point Software Package
@@ -107,12 +107,12 @@ RTABLE: .byte 0,0,0,0
.set FSTRT,0
|
.set ESTRT,4
- .set EDIGITS,2 |
+ .set EDIGITS,2 |
|
| Constants in single precision
-FZERO: .long 0x00000000
-FONE: .long 0x3F800000
-FTEN: .long 0x41200000
+FZERO: .long 0x00000000
+FONE: .long 0x3F800000
+FTEN: .long 0x41200000
.set TEN,10
@@ -224,7 +224,7 @@ nextlw:
addql #1,%d1 |inc lw pointer in mantissa
cmpl #2,%d1 |test for last lw
ble loadlw |if not, get last one
-
+
|
| Check the sign of the mant and make the value in fp0 the same sign.
|
@@ -232,7 +232,7 @@ m_sign:
btst #31,(%a0) |test sign of the mantissa
beq ap_st_z |if clear, go to append/strip zeros
fnegx %fp0 |if set, negate fp0
-
+
|
| Append/strip zeros:
|
@@ -407,7 +407,7 @@ ap_n_en:
|
| Pwrten calculates the exponent factor in the selected rounding mode
| according to the following table:
-|
+|
| Sign of Mant Sign of Exp Rounding Mode PWRTEN Rounding Mode
|
| ANY ANY RN RN
@@ -495,7 +495,7 @@ mul:
| it will be inex2, but will be reported as inex1 by get_op.
|
end_dec:
- fmovel %FPSR,%d0 |get status register
+ fmovel %FPSR,%d0 |get status register
bclrl #inex2_bit+8,%d0 |test for inex2 and clear it
fmovel %d0,%FPSR |return status reg w/o inex2
beqs no_exc |skip this if no exc
diff -puN arch/m68k/fpsp040/do_func.S~m68k-superfluous-whitespace arch/m68k/fpsp040/do_func.S
--- 25/arch/m68k/fpsp040/do_func.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/do_func.S Thu Apr 22 13:43:13 2004
@@ -4,11 +4,11 @@
| Do_func performs the unimplemented operation. The operation
| to be performed is determined from the lower 7 bits of the
| extension word (except in the case of fmovecr and fsincos).
-| The opcode and tag bits form an index into a jump table in
-| tbldo.sa. Cases of zero, infinity and NaN are handled in
+| The opcode and tag bits form an index into a jump table in
+| tbldo.sa. Cases of zero, infinity and NaN are handled in
| do_func by forcing the default result. Normalized and
| denormalized (there are no unnormalized numbers at this
-| point) are passed onto the emulation code.
+| point) are passed onto the emulation code.
|
| CMDREG1B and STAG are extracted from the fsave frame
| and combined to form the table index. The function called
@@ -22,8 +22,8 @@
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
DO_FUNC: |idnt 2,1 | Motorola 040 Floating Point Software Package
@@ -35,7 +35,7 @@ DO_FUNC: |idnt 2,1 | Motorola 040 Flo
|xref t_dz2
|xref t_operr
|xref t_inx2
- |xref t_resdnrm
+ |xref t_resdnrm
|xref dst_nan
|xref src_nan
|xref nrm_set
@@ -68,7 +68,7 @@ do_func:
| directly.
|
bfextu CMDREG1B(%a6){#0:#6},%d0 |get opclass and src fields
- cmpil #0x17,%d0 |if op class and size fields are $17,
+ cmpil #0x17,%d0 |if op class and size fields are $17,
| ;it is FMOVECR; if not, continue
bnes not_fmovecr
jmp smovcr |fmovecr; jmp directly to emulation
@@ -76,7 +76,7 @@ do_func:
not_fmovecr:
movew CMDREG1B(%a6),%d0
andl #0x7F,%d0
- cmpil #0x38,%d0 |if the extension is >= $38,
+ cmpil #0x38,%d0 |if the extension is >= $38,
bge serror |it is illegal
bfextu STAG(%a6){#0:#3},%d1
lsll #3,%d0 |make room for STAG
@@ -111,7 +111,7 @@ ld_mzinx:
bsr ld_mzero |if neg, load neg zero, return here
bra t_inx2 |now, set the inx for the next inst
|
-| Load a signed zero to fp0; do not set inex2/ainex
+| Load a signed zero to fp0; do not set inex2/ainex
|
.global szero
szero:
@@ -119,7 +119,7 @@ szero:
bne ld_mzero |if neg, load neg zero
bra ld_pzero |load positive zero
|
-| Load a signed infinity to fp0; do not set inex2/ainex
+| Load a signed infinity to fp0; do not set inex2/ainex
|
.global sinf
sinf:
@@ -127,7 +127,7 @@ sinf:
bne ld_minf |if negative branch
bra ld_pinf
|
-| Load a signed one to fp0; do not set inex2/ainex
+| Load a signed one to fp0; do not set inex2/ainex
|
.global sone
sone:
@@ -135,7 +135,7 @@ sone:
bne ld_mone
bra ld_pone
|
-| Load a signed pi/2 to fp0; do not set inex2/ainex
+| Load a signed pi/2 to fp0; do not set inex2/ainex
|
.global spi_2
spi_2:
@@ -160,13 +160,13 @@ sopr_inf:
bne t_operr
bra ld_pinf
|
-| FLOGNP1
+| FLOGNP1
|
.global sslognp1
sslognp1:
fmovemx (%a0),%fp0-%fp0
fcmpb #-1,%fp0
- fbgt slognp1
+ fbgt slognp1
fbeq t_dz2 |if = -1, divide by zero exception
fmovel #0,%FPSR |clr N flag
bra t_operr |take care of operands < -1
@@ -186,7 +186,7 @@ setoxm1i:
|
.global sslogn
sslogn:
- btstb #sign_bit,LOCAL_EX(%a0)
+ btstb #sign_bit,LOCAL_EX(%a0)
bne t_operr |take care of operands < 0
cmpiw #0x3fff,LOCAL_EX(%a0) |test for 1.0 input
bne slogn
@@ -199,7 +199,7 @@ sslogn:
.global sslognd
sslognd:
- btstb #sign_bit,LOCAL_EX(%a0)
+ btstb #sign_bit,LOCAL_EX(%a0)
beq slognd
bra t_operr |take care of operands < 0
@@ -221,7 +221,7 @@ sslog10:
.global sslog10d
sslog10d:
- btstb #sign_bit,LOCAL_EX(%a0)
+ btstb #sign_bit,LOCAL_EX(%a0)
beq slog10d
bra t_operr |take care of operands < 0
@@ -243,7 +243,7 @@ sslog2:
.global sslog2d
sslog2d:
- btstb #sign_bit,LOCAL_EX(%a0)
+ btstb #sign_bit,LOCAL_EX(%a0)
beq slog2d
bra t_operr |take care of operands < 0
@@ -310,7 +310,7 @@ smod_zsn:
btstl #7,%d0 |test if + or -
beq ld_pzero |if pos then load +0
bra ld_mzero |else neg load -0
-
+
smod_fpn:
moveb ETEMP(%a6),%d1 |get sign of src op
moveb FPTEMP(%a6),%d0 |get sign of dst op
@@ -327,7 +327,7 @@ smod_nrm:
fmovel USER_FPCR(%a6),%fpcr |use user's rmode and precision
fmovex FPTEMP(%a6),%fp0 |return dest to fp0
rts
-
+
|
| FREM
|
@@ -372,7 +372,7 @@ prem:
lea premt,%a1
movel (%a1,%d1.w*4),%a1
jmp (%a1)
-
+
srem_snan:
bra src_nan
srem_dnan:
@@ -390,7 +390,7 @@ srem_zsn:
btstl #7,%d0 |test if + or -
beq ld_pzero |if pos then load +0
bra ld_mzero |else neg load -0
-
+
srem_fpn:
moveb ETEMP(%a6),%d1 |get sign of src op
moveb FPTEMP(%a6),%d0 |get sign of dst op
@@ -424,10 +424,10 @@ pscalet:
.long scl_inf | 10,00 inf,norm = +-inf
.long scl_inf | 10,01 inf,zero = +-inf
.long scl_opr | 10,10 inf,inf = nan with operr
- .long scl_snan | 10,11 inf,nan = nan
- .long scl_dnan | 11,00 nan,norm = nan
- .long scl_dnan | 11,01 nan,zero = nan
- .long scl_dnan | 11,10 nan,inf = nan
+ .long scl_snan | 10,11 inf,nan = nan
+ .long scl_dnan | 11,00 nan,norm = nan
+ .long scl_dnan | 11,01 nan,zero = nan
+ .long scl_dnan | 11,10 nan,inf = nan
.long scl_dnan | 11,11 nan,nan = nan
.global pscale
@@ -478,7 +478,7 @@ ssincosz:
sincosp:
fmovex PZERO,%fp0
sincoscom:
- fmovemx PONE,%fp1-%fp1 |do not allow FPSR to be affected
+ fmovemx PONE,%fp1-%fp1 |do not allow FPSR to be affected
bra sto_cos |store cosine result
.global ssincosi
@@ -498,7 +498,7 @@ ssincosnan:
bsr sto_cos
bra src_nan
|
-| This code forces default values for the zero, inf, and nan cases
+| This code forces default values for the zero, inf, and nan cases
| in the transcendentals code. The CC bits must be set in the
| stacked FPSR to be correctly reported.
|
diff -puN arch/m68k/fpsp040/fpsp.h~m68k-superfluous-whitespace arch/m68k/fpsp040/fpsp.h
--- 25/arch/m68k/fpsp040/fpsp.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/fpsp.h Thu Apr 22 13:43:13 2004
@@ -5,15 +5,15 @@
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
| fpsp.h --- stack frame offsets during FPSP exception handling
|
| These equates are used to access the exception frame, the fsave
| frame and any local variables needed by the FPSP package.
-|
+|
| All FPSP handlers begin by executing:
|
| link a6,#-LOCAL_SIZE
@@ -90,13 +90,13 @@
.set USER_FP2,LV+40 | saved user FP2
.set USER_FP3,LV+52 | saved user FP3
.set USER_FPCR,LV+64 | saved user FPCR
- .set FPCR_ENABLE,USER_FPCR+2 | FPCR exception enable
- .set FPCR_MODE,USER_FPCR+3 | FPCR rounding mode control
+ .set FPCR_ENABLE,USER_FPCR+2 | FPCR exception enable
+ .set FPCR_MODE,USER_FPCR+3 | FPCR rounding mode control
.set USER_FPSR,LV+68 | saved user FPSR
- .set FPSR_CC,USER_FPSR+0 | FPSR condition code
- .set FPSR_QBYTE,USER_FPSR+1 | FPSR quotient
- .set FPSR_EXCEPT,USER_FPSR+2 | FPSR exception
- .set FPSR_AEXCEPT,USER_FPSR+3 | FPSR accrued exception
+ .set FPSR_CC,USER_FPSR+0 | FPSR condition code
+ .set FPSR_QBYTE,USER_FPSR+1 | FPSR quotient
+ .set FPSR_EXCEPT,USER_FPSR+2 | FPSR exception
+ .set FPSR_AEXCEPT,USER_FPSR+3 | FPSR accrued exception
.set USER_FPIAR,LV+72 | saved user FPIAR
.set FP_SCR1,LV+76 | room for a temporary float value
.set FP_SCR2,LV+92 | room for a temporary float value
@@ -143,8 +143,8 @@
.set CMDREG3B,LV-48 | cmd reg for E3 exceptions (2 bytes)
|
.set NMNEXC,LV-44 | NMNEXC (unsup,snan bits only)
- .set nmn_unsup_bit,1 |
- .set nmn_snan_bit,0 |
+ .set nmn_unsup_bit,1 |
+ .set nmn_snan_bit,0 |
|
.set NMCEXC,LV-43 | NMNEXC & NMCEXC
.set nmn_operr_bit,7
@@ -249,7 +249,7 @@
.set inf_mask,0x02000000
.set nan_mask,0x01000000
|
- .set bsun_mask,0x00008000 |
+ .set bsun_mask,0x00008000 |
.set snan_mask,0x00004000
.set operr_mask,0x00002000
.set ovfl_mask,0x00001000
@@ -268,7 +268,7 @@
|
.set dzinf_mask,inf_mask+dz_mask+adz_mask
.set opnan_mask,nan_mask+operr_mask+aiop_mask
- .set nzi_mask,0x01ffffff | clears N, Z, and I
+ .set nzi_mask,0x01ffffff | clears N, Z, and I
.set unfinx_mask,unfl_mask+inex2_mask+aunfl_mask+ainex_mask
.set unf2inx_mask,unfl_mask+inex2_mask+ainex_mask
.set ovfinx_mask,ovfl_mask+inex2_mask+aovfl_mask+ainex_mask
diff -puN arch/m68k/fpsp040/gen_except.S~m68k-superfluous-whitespace arch/m68k/fpsp040/gen_except.S
--- 25/arch/m68k/fpsp040/gen_except.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/gen_except.S Thu Apr 22 13:43:13 2004
@@ -2,10 +2,10 @@
| gen_except.sa 3.7 1/16/92
|
| gen_except --- FPSP routine to detect reportable exceptions
-|
+|
| This routine compares the exception enable byte of the
| user_fpcr on the stack with the exception status byte
-| of the user_fpsr.
+| of the user_fpsr.
|
| Any routine which may report an exceptions must load
| the stack frame in memory with the exceptional operand(s).
@@ -23,14 +23,14 @@
|
| Note: The IEEE standard specifies that inex2 is to be
| reported if ovfl occurs and the ovfl enable bit is not
-| set but the inex2 enable bit is.
+| set but the inex2 enable bit is.
|
|
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
GEN_EXCEPT: |idnt 2,1 | Motorola 040 Floating Point Software Package
@@ -70,12 +70,12 @@ gen_except:
|
movel ETEMP_EX(%a6),ETEMP_EX(%a1) |copy etemp from unimp
movel ETEMP_HI(%a6),ETEMP_HI(%a1) |frame to busy frame
- movel ETEMP_LO(%a6),ETEMP_LO(%a1)
+ movel ETEMP_LO(%a6),ETEMP_LO(%a1)
movel CMDREG1B(%a6),CMDREG1B(%a1) |set inst in frame to unimp
movel CMDREG1B(%a6),%d0 |fix cmd1b to make it
andl #0x03c30000,%d0 |work for cmd3b
bfextu CMDREG1B(%a6){#13:#1},%d1 |extract bit 2
- lsll #5,%d1
+ lsll #5,%d1
swap %d1
orl %d1,%d0 |put it in the right place
bfextu CMDREG1B(%a6){#10:#3},%d1 |extract bit 3,4,5
@@ -86,7 +86,7 @@ gen_except:
|
| Or in the FPSR from the emulation with the USER_FPSR on the stack.
|
- fmovel %FPSR,%d0
+ fmovel %FPSR,%d0
orl %d0,USER_FPSR(%a6)
movel USER_FPSR(%a6),FPSR_SHADOW(%a1) |set exc bits
orl #sx_mask,E_BYTE(%a1)
@@ -108,7 +108,7 @@ test_rev:
cmpib #UNIMP_41_SIZE-4,1(%a7) |test for rev unimp frame
bnel fpsp_fmt_error |if not $28 or $30
leal UNIMP_41_SIZE+LOCAL_SIZE(%a7),%a1
-
+
unimp_con:
|
| Fix up the new unimp frame with entries from the old unimp frame
@@ -117,23 +117,23 @@ unimp_con:
|
| Or in the FPSR from the emulation with the USER_FPSR on the stack.
|
- fmovel %FPSR,%d0
+ fmovel %FPSR,%d0
orl %d0,USER_FPSR(%a6)
bra do_clean
|
| Frame is idle, so check for exceptions reported through
-| USER_FPSR and set the unimp frame accordingly.
+| USER_FPSR and set the unimp frame accordingly.
| A7 must be incremented to the point before the
| idle fsave vector to the unimp vector.
|
-
+
do_check:
addl #4,%a7 |point A7 back to unimp frame
|
| Or in the FPSR from the emulation with the USER_FPSR on the stack.
|
- fmovel %FPSR,%d0
+ fmovel %FPSR,%d0
orl %d0,USER_FPSR(%a6)
|
| On a busy frame, we must clear the nmnexc bits.
@@ -165,10 +165,10 @@ frame_com:
bsun_exc:
bra do_clean
|
-| The typical work to be done to the unimp frame to report an
+| The typical work to be done to the unimp frame to report an
| exception is to set the E1/E3 byte and clr the U flag.
-| commonE1 does this for E1 exceptions, which are snan,
-| operr, and dz. commonE3 does this for E3 exceptions, which
+| commonE1 does this for E1 exceptions, which are snan,
+| operr, and dz. commonE3 does this for E3 exceptions, which
| are inex2 and inex1, and also clears the E1 exception bit
| left over from the unimp exception.
|
@@ -186,7 +186,7 @@ uniE3:
unsE3:
tstb RES_FLG(%a6)
- bnes unsE3_0
+ bnes unsE3_0
unsE3_1:
bsetb #E3,E_BYTE(%a6) |set E3 flag
unsE3_0:
@@ -194,7 +194,7 @@ unsE3_0:
movel CMDREG1B(%a6),%d0
andl #0x03c30000,%d0 |work for cmd3b
bfextu CMDREG1B(%a6){#13:#1},%d1 |extract bit 2
- lsll #5,%d1
+ lsll #5,%d1
swap %d1
orl %d1,%d0 |put it in the right place
bfextu CMDREG1B(%a6){#10:#3},%d1 |extract bit 3,4,5
@@ -218,8 +218,8 @@ no_match:
beqs no_exc |if clear, exit
bras ovfl_unfl |go to unfl_ovfl to determine if
| ;it is an unsupp or unimp exc
-
-| No exceptions are to be reported. If the instruction was
+
+| No exceptions are to be reported. If the instruction was
| unimplemented, no FPU restore is necessary. If it was
| unsupported, we must perform the restore.
no_exc:
@@ -227,7 +227,7 @@ no_exc:
beqs uni_no_exc
uns_no_exc:
tstb RES_FLG(%a6) |check if frestore is needed
- bne do_clean |if clear, no frestore needed
+ bne do_clean |if clear, no frestore needed
uni_no_exc:
moveml USER_DA(%a6),%d0-%d1/%a0-%a1
fmovemx USER_FP0(%a6),%fp0-%fp3
@@ -243,13 +243,13 @@ uni_no_exc:
|
| Unimplemented Instruction Handler:
| Ovfl:
-| Only scosh, setox, ssinh, stwotox, and scale can set overflow in
+| Only scosh, setox, ssinh, stwotox, and scale can set overflow in
| this manner.
| Unfl:
| Stwotox, setox, and scale can set underflow in this manner.
| Any of the other Library Routines such that f(x)=x in which
-| x is an extended denorm can report an underflow exception.
-| It is the responsibility of the exception-causing exception
+| x is an extended denorm can report an underflow exception.
+| It is the responsibility of the exception-causing exception
| to make sure that WBTEMP is correct.
|
| The exceptional operand is in FP_SCR1.
@@ -306,7 +306,7 @@ busy_fr:
movel CMDREG1B(%a6),%d0 |fix cmd1b to make it
andl #0x03c30000,%d0 |work for cmd3b
bfextu CMDREG1B(%a6){#13:#1},%d1 |extract bit 2
- lsll #5,%d1
+ lsll #5,%d1
swap %d1
orl %d1,%d0 |put it in the right place
bfextu CMDREG1B(%a6){#10:#3},%d1 |extract bit 3,4,5
@@ -318,10 +318,10 @@ busy_fr:
|
| Check if the frame to be restored is busy or unimp.
|** NOTE *** Bug fix for errata (0d43b #3)
-| If the frame is unimp, we must create a busy frame to
+| If the frame is unimp, we must create a busy frame to
| fix the bug with the nmnexc bits in cases in which they
| are set by a previous instruction and not cleared by
-| the save. The frame will be unimp only if the final
+| the save. The frame will be unimp only if the final
| instruction in an emulation routine caused the exception
| by doing an fmove <ea>,fp0. The exception operand, in
| internal format, is in fptemp.
@@ -353,7 +353,7 @@ loop2:
leal BUSY_SIZE+LOCAL_SIZE(%a7),%a1 |init a1 for new frame
moveb VER_TMP(%a6),(%a7) |write busy fmt word
moveb #BUSY_SIZE-4,1(%a7)
- movel FP_SCR1(%a6),WBTEMP_EX(%a1) |write
+ movel FP_SCR1(%a6),WBTEMP_EX(%a1) |write
movel FP_SCR1+4(%a6),WBTEMP_HI(%a1) |exceptional op to
movel FP_SCR1+8(%a6),WBTEMP_LO(%a1) |wbtemp
| btst.b #E1,E_BYTE(%a1)
@@ -362,7 +362,7 @@ loop2:
bfins %d0,NMCEXC(%a1){#4:#4} |and insert them in nmcexc
movel USER_FPSR(%a6),FPSR_SHADOW(%a1) |set exc bits
orl #sx_mask,E_BYTE(%a1)
-
+
do_restore:
moveml USER_DA(%a6),%d0-%d1/%a0-%a1
fmovemx USER_FP0(%a6),%fp0-%fp3
@@ -374,10 +374,10 @@ do_restore:
cont:
unlk %a6
|
-| If trace mode enabled, then go to trace handler. This handler
-| cannot have any fp instructions. If there are fp inst's and an
-| exception has been restored into the machine then the exception
-| will occur upon execution of the fp inst. This is not desirable
+| If trace mode enabled, then go to trace handler. This handler
+| cannot have any fp instructions. If there are fp inst's and an
+| exception has been restored into the machine then the exception
+| will occur upon execution of the fp inst. This is not desirable
| in the kernel (supervisor mode). See MC68040 manual Section 9.3.8.
|
finish_up:
@@ -436,12 +436,12 @@ loop40: clrl -(%sp)
movel USER_D1(%a6),%d1 | restore d1
movel #0x40280000,-(%sp)
frestore (%sp)+
- unlk %a5
+ unlk %a5
rts
frame_41:
tstb 1(%sp) | check to see if idle
- bne notidle
+ bne notidle
idle41:
clrl (%sp) | get rid of old fsave frame
movel %d1,USER_D1(%a6) | save d1
@@ -451,18 +451,18 @@ loop41: clrl -(%sp)
movel USER_D1(%a6),%d1 | restore d1
movel #0x41300000,-(%sp)
frestore (%sp)+
- unlk %a5
+ unlk %a5
rts
notidle:
- bclrb #etemp15_bit,-40(%a5)
+ bclrb #etemp15_bit,-40(%a5)
frestore (%sp)+
- unlk %a5
+ unlk %a5
rts
nofix:
frestore (%sp)+
- unlk %a5
+ unlk %a5
rts
|end
diff -puN arch/m68k/fpsp040/get_op.S~m68k-superfluous-whitespace arch/m68k/fpsp040/get_op.S
--- 25/arch/m68k/fpsp040/get_op.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/get_op.S Thu Apr 22 13:43:13 2004
@@ -16,7 +16,7 @@
|
| - For unnormalized numbers (opclass 0, 2, or 3) the
| number(s) is normalized and the operand type tag is updated.
-|
+|
| - For a packed number (opclass 2) the number is unpacked and the
| operand type tag is updated.
|
@@ -41,7 +41,7 @@
| the '040. The '040 then re-executes the fadd.x fpm,fpn with
| a normalized number in the source and the instruction is
| successful.
-|
+|
| Next consider if in the process of normalizing the un-
| normalized number it becomes a denormalized number. The
| routine which converts the unnorm to a norm (called mk_norm)
@@ -54,8 +54,8 @@
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
GET_OP: |idnt 2,1 | Motorola 040 Floating Point Software Package
@@ -194,7 +194,7 @@ uns_notpacked:
uni_getop:
bfextu CMDREG1B(%a6){#0:#6},%d0 |get opclass and src fields
- cmpil #0x17,%d0 |if op class and size fields are $17,
+ cmpil #0x17,%d0 |if op class and size fields are $17,
| ;it is FMOVECR; if not, continue
|
| If the instruction is fmovecr, exit get_op. It is handled
@@ -226,21 +226,21 @@ dst_ex_dnrm:
movew FPTEMP_EX(%a6),%d0 |get destination exponent
andiw #0x7fff,%d0 |mask sign, check if exp = 0000
beqs src_op_ck |if denorm then check source op.
-| ;denorms are taken care of in res_func
+| ;denorms are taken care of in res_func
| ;(unsupp) or do_func (unimp)
| ;else unnorm fall through
leal FPTEMP(%a6),%a0 |point a0 to dop - used in mk_norm
bsr mk_norm |go normalize - mk_norm returns:
-| ;L_SCR1{7:5} = operand tag
+| ;L_SCR1{7:5} = operand tag
| ; (000 = norm, 100 = denorm)
-| ;L_SCR1{4} = fpte15 or ete15
+| ;L_SCR1{4} = fpte15 or ete15
| ; 0 = exp > $3fff
| ; 1 = exp <= $3fff
-| ;and puts the normalized num back
+| ;and puts the normalized num back
| ;on the fsave stack
|
- moveb L_SCR1(%a6),DTAG(%a6) |write the new tag & fpte15
-| ;to the fsave stack and fall
+ moveb L_SCR1(%a6),DTAG(%a6) |write the new tag & fpte15
+| ;to the fsave stack and fall
| ;through to check source operand
|
src_op_ck:
@@ -255,19 +255,19 @@ src_op_ck:
src_ex_dnrm:
movew ETEMP_EX(%a6),%d0 |get source exponent
andiw #0x7fff,%d0 |mask sign, check if exp = 0000
- beq end_getop |if denorm then exit, denorms are
+ beq end_getop |if denorm then exit, denorms are
| ;handled in do_func
leal ETEMP(%a6),%a0 |point a0 to sop - used in mk_norm
bsr mk_norm |go normalize - mk_norm returns:
-| ;L_SCR1{7:5} = operand tag
+| ;L_SCR1{7:5} = operand tag
| ; (000 = norm, 100 = denorm)
-| ;L_SCR1{4} = fpte15 or ete15
+| ;L_SCR1{4} = fpte15 or ete15
| ; 0 = exp > $3fff
| ; 1 = exp <= $3fff
-| ;and puts the normalized num back
+| ;and puts the normalized num back
| ;on the fsave stack
|
- moveb L_SCR1(%a6),STAG(%a6) |write the new tag & ete15
+ moveb L_SCR1(%a6),STAG(%a6) |write the new tag & ete15
rts |end_getop
|
@@ -285,7 +285,7 @@ is_double:
movew #0x3c01,%d1 |write the bias for a dbl denorm
common:
btstb #sign_bit,ETEMP_EX(%a6) |grab sign bit of mantissa
- beqs pos
+ beqs pos
bset #15,%d1 |set sign bit because it is negative
pos:
movew %d1,ETEMP_EX(%a6)
@@ -297,7 +297,7 @@ pos:
movew %d1,CMDREG1B(%a6) |write back to the command word in stack
| ;this is needed to fix unsupp data stack
leal ETEMP(%a6),%a0 |point a0 to sop
-
+
bsr mk_norm |convert sgl/dbl denorm to norm
moveb L_SCR1(%a6),STAG(%a6) |put tag into source tag reg - d0
rts |end_getop
@@ -306,7 +306,7 @@ pos:
| instruction is dyadic or monadic is still unknown
|
pack_source:
- movel FPTEMP_LO(%a6),ETEMP(%a6) |write ms part of packed
+ movel FPTEMP_LO(%a6),ETEMP(%a6) |write ms part of packed
| ;number to etemp slot
bsr chk_dy_mo |set dyadic/monadic flag
bsr unpack
@@ -325,7 +325,7 @@ pack_dya:
btstb #7,DTAG(%a6) |check dest tag for unnorm or denorm
bne dst_ex_dnrm |else, handle the unnorm or ext denorm
|
-| Dest is not denormalized. Check for norm, and set fpte15
+| Dest is not denormalized. Check for norm, and set fpte15
| accordingly.
|
moveb DTAG(%a6),%d0
@@ -357,13 +357,13 @@ end_getop:
| unsupported data type exception. Set if dyadic.
|
chk_dy_mo:
- movew CMDREG1B(%a6),%d0
+ movew CMDREG1B(%a6),%d0
btstl #5,%d0 |testing extension command word
beqs set_mon |if bit 5 = 0 then monadic
btstl #4,%d0 |know that bit 5 = 1
beqs set_dya |if bit 4 = 0 then dyadic
andiw #0x007f,%d0 |get rid of all but extension bits {6:0}
- cmpiw #0x0038,%d0 |if extension = $38 then fcmp (dyadic)
+ cmpiw #0x0038,%d0 |if extension = $38 then fcmp (dyadic)
bnes set_mon
set_dya:
st DY_MO_FLG(%a6) |set the inst flag type to dyadic
@@ -406,7 +406,7 @@ set_mon:
| L_SCR1{7:5} = operand tag (000 = norm, 100 = denorm)
| L_SCR1{4} = fpte15 or ete15 (0 = exp > $3fff, 1 = exp <=$3fff)
| the normalized operand is placed back on the fsave stack
-mk_norm:
+mk_norm:
clrl L_SCR1(%a6)
bclrb #sign_bit,LOCAL_EX(%a0)
sne LOCAL_SGN(%a0) |transform into internal extended format
@@ -426,11 +426,11 @@ reload:
cmpw #0x3fff,LOCAL_EX(%a0) |if exp > $3fff
bgts end_mk | fpte15/ete15 already set to 0
bsetb #4,L_SCR1(%a6) |else set fpte15/ete15 to 1
-| ;calling routine actually sets the
-| ;value on the stack (along with the
-| ;tag), since this routine doesn't
+| ;calling routine actually sets the
+| ;value on the stack (along with the
+| ;tag), since this routine doesn't
| ;know if it should set ete15 or fpte15
-| ;ie, it doesn't know if this is the
+| ;ie, it doesn't know if this is the
| ;src op or dest op.
end_mk:
bfclr LOCAL_SGN(%a0){#0:#8}
@@ -455,7 +455,7 @@ no_unfl:
|
uns_opx:
bsr nrm_zero |normalize the number
- btstb #7,LOCAL_HI(%a0) |check if integer bit (j-bit) is set
+ btstb #7,LOCAL_HI(%a0) |check if integer bit (j-bit) is set
beqs uns_den |if clear then now have a denorm
uns_nrm:
orb #norm_tag,L_SCR1(%a6) |set tag to norm
@@ -468,7 +468,7 @@ uns_den:
|
uni_inst:
bsr nrm_zero
- btstb #7,LOCAL_HI(%a0) |check if integer bit (j-bit) is set
+ btstb #7,LOCAL_HI(%a0) |check if integer bit (j-bit) is set
beqs uni_den |if clear then now have a denorm
uni_nrm:
orb #norm_tag,L_SCR1(%a6) |set tag to norm
@@ -480,9 +480,9 @@ uni_den:
|
| Decimal to binary conversion
|
-| Special cases of inf and NaNs are completed outside of decbin.
+| Special cases of inf and NaNs are completed outside of decbin.
| If the input is an snan, the snan bit is not set.
-|
+|
| input:
| ETEMP(a6) - points to packed decimal string in memory
| output:
@@ -610,16 +610,16 @@ mnot_spec:
finish:
movew CMDREG1B(%a6),%d0 |get the command word
- andw #0xfbff,%d0 |change the source specifier field to
+ andw #0xfbff,%d0 |change the source specifier field to
| ;extended (was packed).
movew %d0,CMDREG1B(%a6) |write command word back to fsave stack
-| ;we need to do this so the 040 will
-| ;re-execute the inst. without taking
+| ;we need to do this so the 040 will
+| ;re-execute the inst. without taking
| ;another packed trap.
fix_stag:
-|Converted result is now in etemp on fsave stack, now set the source
-|tag (stag)
+|Converted result is now in etemp on fsave stack, now set the source
+|tag (stag)
| if (ete =$7fff) then INF or NAN
| if (etemp = $x.0----0) then
| stag = INF
@@ -632,12 +632,12 @@ fix_stag:
| stag = NORM
|
| Note also that the etemp_15 bit (just right of the stag) must
-| be set accordingly.
+| be set accordingly.
|
movew ETEMP_EX(%a6),%d1
andiw #0x7fff,%d1 |strip sign
- cmpw #0x7fff,%d1
- bnes z_or_nrm
+ cmpw #0x7fff,%d1
+ bnes z_or_nrm
movel ETEMP_HI(%a6),%d1
bnes is_nan
movel ETEMP_LO(%a6),%d1
@@ -651,7 +651,7 @@ is_nan:
movel #0x60,%d0
rts
z_or_nrm:
- tstw %d1
+ tstw %d1
bnes is_nrm
is_zro:
| For a zero, set etemp_15
@@ -670,7 +670,7 @@ end_is_nrm:
movel #0,%d0
end_fix:
rts
-
+
end_get:
rts
|end
diff -puN arch/m68k/fpsp040/kernel_ex.S~m68k-superfluous-whitespace arch/m68k/fpsp040/kernel_ex.S
--- 25/arch/m68k/fpsp040/kernel_ex.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/kernel_ex.S Thu Apr 22 13:43:13 2004
@@ -1,19 +1,19 @@
|
-| kernel_ex.sa 3.3 12/19/90
+| kernel_ex.sa 3.3 12/19/90
|
-| This file contains routines to force exception status in the
+| This file contains routines to force exception status in the
| fpu for exceptional cases detected or reported within the
| transcendental functions. Typically, the t_xx routine will
| set the appropriate bits in the USER_FPSR word on the stack.
| The bits are tested in gen_except.sa to determine if an exceptional
-| situation needs to be created on return from the FPSP.
+| situation needs to be created on return from the FPSP.
|
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
KERNEL_EX: |idnt 2,1 | Motorola 040 Floating Point Software Package
@@ -31,7 +31,7 @@ huge: .long 0x7ffe0000,0xffffffff,0x
|xref unf_sub
|xref nrm_set
- .global t_dz
+ .global t_dz
.global t_dz2
.global t_operr
.global t_unfl
@@ -49,7 +49,7 @@ huge: .long 0x7ffe0000,0xffffffff,0x
|
| if dz trap disabled
| store properly signed inf (use sign of etemp) into fp0
-| set FPSR exception status dz bit, condition code
+| set FPSR exception status dz bit, condition code
| inf bit, and accrued dz bit
| return
| frestore the frame into the machine (done by unimp_hd)
@@ -61,7 +61,7 @@ huge: .long 0x7ffe0000,0xffffffff,0x
| frestore the frame into the machine (done by unimp_hd)
|
| t_dz2 is used by monadic functions such as flogn (from do_func).
-| t_dz is used by monadic functions such as satanh (from the
+| t_dz is used by monadic functions such as satanh (from the
| transcendental function).
|
t_dz2:
@@ -104,10 +104,10 @@ dz_ena_end:
| OPERR exception
|
| if (operr trap disabled)
-| set FPSR exception status operr bit, condition code
+| set FPSR exception status operr bit, condition code
| nan bit; Store default NAN into fp0
| frestore the frame into the machine (done by unimp_hd)
-|
+|
| else (operr trap enabled)
| set FPSR exception status operr bit, accrued operr bit
| set flag to disable sto_res from corrupting fp register
@@ -159,13 +159,13 @@ unfl_ena:
unfl_dis:
bfextu FPCR_MODE(%a6){#0:#2},%d0 |get round precision
-
+
bclrb #sign_bit,LOCAL_EX(%a0)
sne LOCAL_SGN(%a0) |convert to internal ext format
bsr unf_sub |returns IEEE result at a0
| ;and sets FPSR_CC accordingly
-
+
bfclr LOCAL_SGN(%a0){#0:#8} |convert back to IEEE ext format
beqs unfl_fin
@@ -175,7 +175,7 @@ unfl_dis:
unfl_fin:
fmovemx (%a0),%fp0-%fp0 |store result in fp0
rts
-
+
|
| t_ovfl2 --- OVFL exception (without inex2 returned)
@@ -280,7 +280,7 @@ no_uacc1:
| DST_NAN
|
| Determine if the destination nan is signalling or non-signalling,
-| and set the FPSR bits accordingly. See the MC68040 User's Manual
+| and set the FPSR bits accordingly. See the MC68040 User's Manual
| section 3.2.2.5 NOT-A-NUMBERS.
|
dst_nan:
@@ -288,7 +288,7 @@ dst_nan:
beqs dst_pos |if clr, it was positive
bsetb #neg_bit,FPSR_CC(%a6) |set N bit
dst_pos:
- btstb #signan_bit,FPTEMP_HI(%a6) |check if signalling
+ btstb #signan_bit,FPTEMP_HI(%a6) |check if signalling
beqs dst_snan |branch if signalling
fmovel %d1,%fpcr |restore user's rmode/prec
@@ -300,14 +300,14 @@ dst_pos:
andib #0xe0,%d0
cmpib #0x60,%d0
bnes no_snan
- btstb #signan_bit,ETEMP_HI(%a6) |check if signalling
+ btstb #signan_bit,ETEMP_HI(%a6) |check if signalling
bnes no_snan
orl #snaniop_mask,USER_FPSR(%a6) |set NAN, SNAN, AIOP
no_snan:
- rts
+ rts
dst_snan:
- btstb #snan_bit,FPCR_ENABLE(%a6) |check if trap enabled
+ btstb #snan_bit,FPCR_ENABLE(%a6) |check if trap enabled
beqs dst_dis |branch if disabled
orb #nan_tag,DTAG(%a6) |set up dtag for nan
@@ -316,9 +316,9 @@ dst_snan:
rts
dst_dis:
- bsetb #signan_bit,FPTEMP_HI(%a6) |set SNAN bit in sop
+ bsetb #signan_bit,FPTEMP_HI(%a6) |set SNAN bit in sop
fmovel %d1,%fpcr |restore user's rmode/prec
- fmovex FPTEMP(%a6),%fp0 |load non-sign. nan
+ fmovex FPTEMP(%a6),%fp0 |load non-sign. nan
orl #snaniop_mask,USER_FPSR(%a6) |set NAN, SNAN, AIOP
rts
@@ -326,7 +326,7 @@ dst_dis:
| SRC_NAN
|
| Determine if the source nan is signalling or non-signalling,
-| and set the FPSR bits accordingly. See the MC68040 User's Manual
+| and set the FPSR bits accordingly. See the MC68040 User's Manual
| section 3.2.2.5 NOT-A-NUMBERS.
|
src_nan:
@@ -334,16 +334,16 @@ src_nan:
beqs src_pos |if clr, it was positive
bsetb #neg_bit,FPSR_CC(%a6) |set N bit
src_pos:
- btstb #signan_bit,ETEMP_HI(%a6) |check if signalling
+ btstb #signan_bit,ETEMP_HI(%a6) |check if signalling
beqs src_snan |branch if signalling
fmovel %d1,%fpcr |restore user's rmode/prec
fmovex ETEMP(%a6),%fp0 |return the non-signalling nan
- rts
+ rts
src_snan:
- btstb #snan_bit,FPCR_ENABLE(%a6) |check if trap enabled
+ btstb #snan_bit,FPCR_ENABLE(%a6) |check if trap enabled
beqs src_dis |branch if disabled
- bsetb #signan_bit,ETEMP_HI(%a6) |set SNAN bit in sop
+ bsetb #signan_bit,ETEMP_HI(%a6) |set SNAN bit in sop
orb #norm_tag,DTAG(%a6) |set up dtag for norm
orb #nan_tag,STAG(%a6) |set up stag for nan
st STORE_FLG(%a6) |do not store a result
@@ -351,9 +351,9 @@ src_snan:
rts
src_dis:
- bsetb #signan_bit,ETEMP_HI(%a6) |set SNAN bit in sop
+ bsetb #signan_bit,ETEMP_HI(%a6) |set SNAN bit in sop
fmovel %d1,%fpcr |restore user's rmode/prec
- fmovex ETEMP(%a6),%fp0 |load non-sign. nan
+ fmovex ETEMP(%a6),%fp0 |load non-sign. nan
orl #snaniop_mask,USER_FPSR(%a6) |set NAN, SNAN, AIOP
rts
@@ -367,7 +367,7 @@ t_extdnrm:
bras xdnrm_con
|
| Entry point for scale with extended denorm. The function does
-| not set inex2, aunfl, or ainex.
+| not set inex2, aunfl, or ainex.
|
t_resdnrm:
orl #unfl_mask,USER_FPSR(%a6)
@@ -402,7 +402,7 @@ xdnrm_dn:
bfclr LOCAL_SGN(%a0){#0:#8} |change back to IEEE ext format
beqs xdep
bsetb #sign_bit,LOCAL_EX(%a0)
-xdep:
+xdep:
bfclr STAG(%a6){#5:#3} |clear wbtm66,wbtm1,wbtm0
bsetb #wbtemp15_bit,WB_BYTE(%a6) |set wbtemp15
bclrb #sticky_bit,STICKY(%a6) |clear sticky bit
@@ -439,7 +439,7 @@ xdnrm_store:
|
.global t_avoid_unsupp
t_avoid_unsupp:
- link %a2,#-LOCAL_SIZE |so that a2 fpsp.h negative
+ link %a2,#-LOCAL_SIZE |so that a2 fpsp.h negative
| ;offsets may be used
fsave -(%a7)
tstb 1(%a7) |check if idle, exit if so
diff -puN arch/m68k/fpsp040/README~m68k-superfluous-whitespace arch/m68k/fpsp040/README
--- 25/arch/m68k/fpsp040/README~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/README Thu Apr 22 13:43:13 2004
@@ -12,7 +12,7 @@ MOTOROLA DISCLAIMS ALL WARRANTIES WHETHE
INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A
PARTICULAR PURPOSE and any warranty against infringement with
regard to the SOFTWARE (INCLUDING ANY MODIFIED VERSIONS THEREOF)
-and any accompanying written materials.
+and any accompanying written materials.
To the maximum extent permitted by applicable law,
IN NO EVENT SHALL MOTOROLA BE LIABLE FOR ANY DAMAGES WHATSOEVER
@@ -20,7 +20,7 @@ IN NO EVENT SHALL MOTOROLA BE LIABLE FOR
PROFITS, BUSINESS INTERRUPTION, LOSS OF BUSINESS INFORMATION, OR
OTHER PECUNIARY LOSS) ARISING OF THE USE OR INABILITY TO USE THE
SOFTWARE. Motorola assumes no responsibility for the maintenance
-and support of the SOFTWARE.
+and support of the SOFTWARE.
You are hereby granted a copyright license to use, modify, and
distribute the SOFTWARE so long as this entire notice is retained
diff -puN arch/m68k/fpsp040/res_func.S~m68k-superfluous-whitespace arch/m68k/fpsp040/res_func.S
--- 25/arch/m68k/fpsp040/res_func.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/res_func.S Thu Apr 22 13:43:13 2004
@@ -8,7 +8,7 @@
| (Exception vector 55).
|
| For packed move out (fmove.p fpm,<ea>) the operation is
-| completed here; data is packed and moved to user memory.
+| completed here; data is packed and moved to user memory.
| The stack is restored to the 040 only in the case of a
| reportable exception in the conversion.
|
@@ -16,8 +16,8 @@
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
RES_FUNC: |idnt 2,1 | Motorola 040 Floating Point Software Package
@@ -48,7 +48,7 @@ dp_bnds: .short 0x3c01,0x43fe
|xref t_unfl
.global res_func
- .global p_move
+ .global p_move
res_func:
clrb DNRM_FLG(%a6)
@@ -100,7 +100,7 @@ monadic:
movew CMDREG1B(%a6),%d0 |get command register
andil #0x7f,%d0 |strip to only command word
|
-| At this point, fabs, fneg, fsmove, fdmove, ftst, fsqrt, fssqrt, and
+| At this point, fabs, fneg, fsmove, fdmove, ftst, fsqrt, fssqrt, and
| fdsqrt are possible.
| For cases fabs, fneg, fsmove, and fdmove goto spos (do not normalize)
| For cases fsqrt, fssqrt, and fdsqrt goto nrm_src (do normalize)
@@ -143,7 +143,7 @@ cu_ntpo:
rts
cu_ntn:
orl #nan_mask,USER_FPSR(%a6)
- movel ETEMP_EX(%a6),FPTEMP_EX(%a6) |set up fptemp sign for
+ movel ETEMP_EX(%a6),FPTEMP_EX(%a6) |set up fptemp sign for
| ;snan handler
rts
@@ -206,7 +206,7 @@ cu_nmnr:
cu_nmrd:
movel #2,%d0 |set up the size for denorm
movew LOCAL_EX(%a0),%d1 |compare exponent to double threshold
- andw #0x7fff,%d1
+ andw #0x7fff,%d1
cmpw #0x3c01,%d1
bls cu_nunfl
bfextu FPCR_MODE(%a6){#2:#2},%d1 |get rmode
@@ -359,7 +359,7 @@ cu_wreon:
| ;write the new tag & ete15 to the fstack
mon_dnrm:
|
-| At this point, check for the cases in which normalizing the
+| At this point, check for the cases in which normalizing the
| denorm produces incorrect results.
|
tstb DY_MO_FLG(%a6) |all cases of dyadic instructions would
@@ -374,7 +374,7 @@ mon_dnrm:
movew CMDREG1B(%a6),%d0 |get command register
andil #0x7f,%d0 |strip to only command word
|
-| At this point, fabs, fneg, fsmove, fdmove, ftst, fsqrt, fssqrt, and
+| At this point, fabs, fneg, fsmove, fdmove, ftst, fsqrt, fssqrt, and
| fdsqrt are possible.
| For cases fabs, fneg, fsmove, and fdmove goto spos (do not normalize)
| For cases fsqrt, fssqrt, and fdsqrt goto nrm_src (do normalize)
@@ -382,12 +382,12 @@ mon_dnrm:
btstl #0,%d0
bnes nrm_src |weed out fsqrt instructions
st CU_ONLY(%a6) |set cu-only inst flag
- bra cu_dnrm |fmove, fabs, fneg, ftst
+ bra cu_dnrm |fmove, fabs, fneg, ftst
| ;cases go to cu_dnrm
nrm_src:
bclrb #sign_bit,LOCAL_EX(%a0)
sne LOCAL_SGN(%a0)
- bsr nrm_set |normalize number (exponent will go
+ bsr nrm_set |normalize number (exponent will go
| ; negative)
bclrb #sign_bit,LOCAL_EX(%a0) |get rid of false sign
@@ -413,7 +413,7 @@ fix_stk:
|
| cu_dnrm handles all cu-only instructions (fmove, fabs, fneg, and
-| ftst) completely in software without an frestore to the 040.
+| ftst) completely in software without an frestore to the 040.
|
cu_dnrm:
st CU_ONLY(%a6)
@@ -446,7 +446,7 @@ cu_dtpo:
rts
cu_dtn:
orl #nan_mask,USER_FPSR(%a6)
- movel ETEMP_EX(%a6),FPTEMP_EX(%a6) |set up fptemp sign for
+ movel ETEMP_EX(%a6),FPTEMP_EX(%a6) |set up fptemp sign for
| ;snan handler
rts
cu_dtcz:
@@ -525,7 +525,7 @@ cu_dmsn:
bra cu_sndr |load single neg zero w/lsb
|
| The precision is extended, so the result in etemp is correct.
-| Simply set unfl (not inex2 or aunfl) and write the result to
+| Simply set unfl (not inex2 or aunfl) and write the result to
| the correct fp register.
cu_wrexd:
orl #unfl_mask,USER_FPSR(%a6)
@@ -597,7 +597,7 @@ cu_sndr:
orl #neg_mask,USER_FPSR(%a6)
orl #unfinx_mask,USER_FPSR(%a6)
bra wr_etemp
-
+
|
| This code checks for 16-bit overflow conditions on dyadic
| operations which are not restorable into the floating-point
@@ -613,7 +613,7 @@ cu_sndr:
| $ff for both ops denormalized
|
| The wrap-around condition occurs for add, sub, div, and cmp
-| when
+| when
|
| abs(dest_exp - src_exp) >= $8000
|
@@ -627,7 +627,7 @@ cu_sndr:
| for this condition. The restore flag (RES_FLG) is left clear.
| No frestore is done unless an exception is to be reported.
|
-| For fadd:
+| For fadd:
| if(sign_of(dest) != sign_of(src))
| replace exponent of src with $3fff (keep sign)
| use fpu to perform dest+new_src (user's rmode and X)
@@ -689,10 +689,10 @@ ck_wrap:
cmpiw #cmpcode,%d0
beq wrap_cmp
|
-| Inst is fdiv.
+| Inst is fdiv.
|
wrap_div:
- cmpb #0xff,DNRM_FLG(%a6) |if both ops denorm,
+ cmpb #0xff,DNRM_FLG(%a6) |if both ops denorm,
beq fix_stk |restore to fpu
|
| One of the ops is denormalized. Test for wrap condition
@@ -722,7 +722,7 @@ ckinf_ns:
bra ck_in_com
ckinf_nd:
moveb DTAG(%a6),%d0 |check destination tag for inf or nan
-ck_in_com:
+ck_in_com:
andib #0x60,%d0 |isolate tag bits
cmpb #0x40,%d0 |is it inf?
beq nan_or_inf |not wrap case
@@ -755,7 +755,7 @@ div_srcd:
beqs force_ovf
st WBTEMP_SGN(%a6)
|
-| This code handles the case of the instruction resulting in
+| This code handles the case of the instruction resulting in
| an overflow condition.
|
force_ovf:
@@ -777,7 +777,7 @@ frcovf_fpcr:
bfextu FPCR_MODE(%a6){#0:#2},%d0 |inst not forced - use fpcr prec
frcovf_rnd:
-| The 881/882 does not set inex2 for the following case, so the
+| The 881/882 does not set inex2 for the following case, so the
| line is commented out to be compatible with 881/882
| tst.b %d0
| beq.b frcovf_x
@@ -785,7 +785,7 @@ frcovf_rnd:
|frcovf_x:
bsrl ovf_res |get correct result based on
-| ;round precision/mode. This
+| ;round precision/mode. This
| ;sets FPSR_CC correctly
| ;returns in external format
bfclr WBTEMP_SGN(%a6){#0:#8}
@@ -796,7 +796,7 @@ frcovf_rnd:
| Inst is fadd.
|
wrap_add:
- cmpb #0xff,DNRM_FLG(%a6) |if both ops denorm,
+ cmpb #0xff,DNRM_FLG(%a6) |if both ops denorm,
beq fix_stk |restore to fpu
|
| One of the ops is denormalized. Test for wrap condition
@@ -964,14 +964,14 @@ add_ckovf:
| and aovfl, and clr the mantissa (incorrectly set by the
| round routine.)
|
- orl #inf_mask+ovfl_inx_mask,USER_FPSR(%a6)
+ orl #inf_mask+ovfl_inx_mask,USER_FPSR(%a6)
clrl 4(%a0)
bra frcfpnr
|
| Inst is fsub.
|
wrap_sub:
- cmpb #0xff,DNRM_FLG(%a6) |if both ops denorm,
+ cmpb #0xff,DNRM_FLG(%a6) |if both ops denorm,
beq fix_stk |restore to fpu
|
| One of the ops is denormalized. Test for wrap condition
@@ -1145,14 +1145,14 @@ sub_ckovf:
| and aovfl, and clr the mantissa (incorrectly set by the
| round routine.)
|
- orl #inf_mask+ovfl_inx_mask,USER_FPSR(%a6)
+ orl #inf_mask+ovfl_inx_mask,USER_FPSR(%a6)
clrl 4(%a0)
bra frcfpnr
|
| Inst is fcmp.
|
wrap_cmp:
- cmpb #0xff,DNRM_FLG(%a6) |if both ops denorm,
+ cmpb #0xff,DNRM_FLG(%a6) |if both ops denorm,
beq fix_stk |restore to fpu
|
| One of the ops is denormalized. Test for wrap condition
@@ -1190,7 +1190,7 @@ cmp_setn:
| Inst is fmul.
|
wrap_mul:
- cmpb #0xff,DNRM_FLG(%a6) |if both ops denorm,
+ cmpb #0xff,DNRM_FLG(%a6) |if both ops denorm,
beq force_unf |force an underflow (really!)
|
| One of the ops is denormalized. Test for wrap condition
@@ -1213,9 +1213,9 @@ mul_srcd:
bfexts ETEMP_EX(%a6){#1:#15},%d1 |get src exp (always neg)
addl %d1,%d0 |subtract src from dest
bgt fix_stk
-
+
|
-| This code handles the case of the instruction resulting in
+| This code handles the case of the instruction resulting in
| an underflow condition.
|
force_unf:
@@ -1245,7 +1245,7 @@ frcunf_fpcr:
bfextu FPCR_MODE(%a6){#0:#2},%d0 |inst not forced - use fpcr prec
frcunf_rnd:
bsrl unf_sub |get correct result based on
-| ;round precision/mode. This
+| ;round precision/mode. This
| ;sets FPSR_CC correctly
bfclr WBTEMP_SGN(%a6){#0:#8} |convert back to IEEE ext format
beqs frcfpn
@@ -1277,14 +1277,14 @@ frcfpn_rnd:
bclrb #sign_bit,WBTEMP_EX(%a6)
sne WBTEMP_SGN(%a6)
bsrl ovf_res |get correct result based on
-| ;round precision/mode. This
+| ;round precision/mode. This
| ;sets FPSR_CC correctly
bfclr WBTEMP_SGN(%a6){#0:#8} |convert back to IEEE ext format
beqs frcfpn_clr
bsetb #sign_bit,WBTEMP_EX(%a6)
frcfpn_clr:
orl #ovfinx_mask,USER_FPSR(%a6)
-|
+|
| Perform the write.
|
frcfpn:
@@ -1301,9 +1301,9 @@ frc0123:
cmpib #0,%d0
beqs frc0_dst
cmpib #1,%d0
- beqs frc1_dst
+ beqs frc1_dst
cmpib #2,%d0
- beqs frc2_dst
+ beqs frc2_dst
frc3_dst:
movel WBTEMP_EX(%a6),USER_FP3(%a6)
movel WBTEMP_HI(%a6),USER_FP3+4(%a6)
@@ -1337,7 +1337,7 @@ wr_etemp:
beqs fmoveinc |enabled, force restore
btstb #snan_bit,FPCR_ENABLE(%a6) |and don't overwrite
beqs fmoveinc |the dest
- movel ETEMP_EX(%a6),FPTEMP_EX(%a6) |set up fptemp sign for
+ movel ETEMP_EX(%a6),FPTEMP_EX(%a6) |set up fptemp sign for
| ;snan handler
tstb ETEMP(%a6) |check for negative
blts snan_neg
@@ -1361,7 +1361,7 @@ fminc_cnan:
cmpib #0x60,%d0 |check if stag is NaN
bnes fminc_czero
orl #nan_mask,USER_FPSR(%a6) |if nan, nothing yet has set NaN
- movel ETEMP_EX(%a6),FPTEMP_EX(%a6) |set up fptemp sign for
+ movel ETEMP_EX(%a6),FPTEMP_EX(%a6) |set up fptemp sign for
| ;snan handler
tstw LOCAL_EX(%a0) |check sign
bges fminc_con
@@ -1389,9 +1389,9 @@ fp0123:
cmpib #0,%d0
beqs fp0_dst
cmpib #1,%d0
- beqs fp1_dst
+ beqs fp1_dst
cmpib #2,%d0
- beqs fp2_dst
+ beqs fp2_dst
fp3_dst:
movel ETEMP_EX(%a6),USER_FP3(%a6)
movel ETEMP_HI(%a6),USER_FP3+4(%a6)
@@ -1421,20 +1421,20 @@ opclass3:
beq pack_out |else it is norm or denorm
bra mv_out
-
+
|
| MOVE OUT
|
mv_tbl:
.long li
- .long sgp
- .long xp
- .long mvout_end |should never be taken
- .long wi
- .long dp
- .long bi
- .long mvout_end |should never be taken
+ .long sgp
+ .long xp
+ .long mvout_end |should never be taken
+ .long wi
+ .long dp
+ .long bi
+ .long mvout_end |should never be taken
mv_out:
bfextu CMDREG1B(%a6){#3:#3},%d1 |put source specifier in d1
leal mv_tbl,%a0
@@ -1442,7 +1442,7 @@ mv_out:
jmp (%a0)
|
-| This exit is for move-out to memory. The aunfl bit is
+| This exit is for move-out to memory. The aunfl bit is
| set if the result is inex and unfl is signalled.
|
mvout_end:
@@ -1466,7 +1466,7 @@ no_aufl:
mvout_con:
rts
|
-| This exit is for move-out to int register. The aunfl bit is
+| This exit is for move-out to int register. The aunfl bit is
| not set in any case for this move.
|
mvouti_end:
@@ -1496,7 +1496,7 @@ li:
fmovemx ETEMP(%a6),%fp0-%fp0
fcmpd #0x41dfffffffc00000,%fp0
| 41dfffffffc00000 in dbl prec = 401d0000fffffffe00000000 in ext prec
- fbge lo_plrg
+ fbge lo_plrg
fcmpd #0xc1e0000000000000,%fp0
| c1e0000000000000 in dbl prec = c01e00008000000000000000 in ext prec
fble lo_nlrg
@@ -1541,7 +1541,7 @@ wi:
fmovemx ETEMP(%a6),%fp0-%fp0
fcmps #0x46fffe00,%fp0
| 46fffe00 in sgl prec = 400d0000fffe000000000000 in ext prec
- fbge wo_plrg
+ fbge wo_plrg
fcmps #0xc7000000,%fp0
| c7000000 in sgl prec = c00e00008000000000000000 in ext prec
fble wo_nlrg
@@ -1586,7 +1586,7 @@ bi:
fmovemx ETEMP(%a6),%fp0-%fp0
fcmps #0x42fe0000,%fp0
| 42fe0000 in sgl prec = 40050000fe00000000000000 in ext prec
- fbge by_plrg
+ fbge by_plrg
fcmps #0xc3000000,%fp0
| c3000000 in sgl prec = c00600008000000000000000 in ext prec
fble by_nlrg
@@ -1629,7 +1629,7 @@ by_nlrg:
int_dnrm:
movel #0,L_SCR1(%a6) | initialize result to 0
bfextu FPCR_MODE(%a6){#2:#2},%d1 | d1 is the rounding mode
- cmpb #2,%d1
+ cmpb #2,%d1
bmis int_inx | if RN or RZ, done
bnes int_rp | if RP, continue below
tstw ETEMP(%a6) | RM: store -1 in L_SCR1 if src is negative
@@ -1642,7 +1642,7 @@ int_rp:
bmis int_inx | otherwise, result is 0
lea L_SCR1(%a6),%a1 | a1 is address of L_SCR1
addal %d0,%a1 | offset by destination width -1
- subal #1,%a1
+ subal #1,%a1
bsetb #0,(%a1) | set low bit at a1 address
int_inx:
oril #inx2a_mask,USER_FPSR(%a6)
@@ -1656,10 +1656,10 @@ int_operr:
oril #opaop_mask,USER_FPSR(%a6)
| ;fall through to perform int_wrt
-int_wrt:
+int_wrt:
movel EXC_EA(%a6),%a1 |load destination address
tstl %a1 |check to see if it is a dest register
- beqs wrt_dn |write data register
+ beqs wrt_dn |write data register
lea L_SCR1(%a6),%a0 |point to supervisor source address
bsrl mem_write
bra mvouti_end
@@ -1680,7 +1680,7 @@ sz_long:
sz_con:
movel %d0,%d1 |reg_dest expects size:reg in d1
bsrl reg_dest |load proper data register
- bra mvouti_end
+ bra mvouti_end
xp:
lea ETEMP(%a6),%a0
bclrb #sign_bit,LOCAL_EX(%a0)
@@ -1718,7 +1718,7 @@ dp:
blt dp_under
cmpw 2(%a1),%d0
bgt dp_over
-
+
movel #2,%d0 |set destination format to double
| ;fall through to do_fp
|
@@ -1726,10 +1726,10 @@ do_fp:
bfextu FPCR_MODE(%a6){#2:#2},%d1 |rnd mode in d1
swap %d0 |rnd prec in upper word
addl %d0,%d1 |d1 has PREC/MODE info
-
- clrl %d0 |clear g,r,s
- bsrl round |round
+ clrl %d0 |clear g,r,s
+
+ bsrl round |round
movel %a0,%a1
movel EXC_EA(%a6),%a0
@@ -1764,12 +1764,12 @@ xdnrm:
bsrl dest_ext |store to memory
bsetb #unfl_bit,FPSR_EXCEPT(%a6)
bra mvout_end
-
+
sp_under:
bsetb #etemp15_bit,STAG(%a6)
cmpw 4(%a1),%d0
- blts sp_catas |catastrophic underflow case
+ blts sp_catas |catastrophic underflow case
movel #1,%d0 |load in round precision
movel #sgl_thresh,%d1 |load in single denorm threshold
@@ -1784,9 +1784,9 @@ dp_under:
cmpw 4(%a1),%d0
blts dp_catas |catastrophic underflow case
-
+
movel #dbl_thresh,%d1 |load in double precision threshold
- movel #2,%d0
+ movel #2,%d0
bsrl dpspdnrm |expects d1 to have proper
| ;denorm threshold
| ;expects d0 to have round precision
@@ -1813,11 +1813,11 @@ sp_catas:
movel %a0,%a1 |a1 has the operand input
movel EXC_EA(%a6),%a0 |a0 has the destination pointer
-
+
bsrl dest_sgl |store the result
oril #unfinx_mask,USER_FPSR(%a6)
bra mvout_end
-
+
dp_catas:
| Temp fix for z bit set in unf_sub
movel USER_FPSR(%a6),-(%a7)
@@ -1828,12 +1828,12 @@ dp_catas:
movel (%a7)+,USER_FPSR(%a6)
movel #1,%d0
- subw %d0,LOCAL_EX(%a0) |account for difference between
+ subw %d0,LOCAL_EX(%a0) |account for difference between
| ;denorm/norm bias
movel %a0,%a1 |a1 has the operand input
movel EXC_EA(%a6),%a0 |a0 has the destination pointer
-
+
bsrl dest_dbl |store the result
oril #unfinx_mask,USER_FPSR(%a6)
bra mvout_end
@@ -1880,7 +1880,7 @@ dp_over:
bra mvout_end
|
-| DPSPDNRM
+| DPSPDNRM
|
| This subroutine takes an extended normalized number and denormalizes
| it to the given round precision. This subroutine also decrements
@@ -1894,7 +1894,7 @@ dp_over:
|
| Output: (In the format for dest_sgl or dest_dbl)
| a0 points to the destination
-| a1 points to the operand
+| a1 points to the operand
|
| Exceptions: Reports inexact 2 exception by setting USER_FPSR bits
|
@@ -1905,7 +1905,7 @@ dpspdnrm:
bfextu FPCR_MODE(%a6){#2:#2},%d1 |get rounding mode
swap %d1
- movew 2(%a7),%d1 |set rounding precision
+ movew 2(%a7),%d1 |set rounding precision
swap %d1 |at this point d1 has PREC/MODE info
bsrl round |round result, sets the inex bit in
| ;USER_FPSR if needed
@@ -1952,20 +1952,20 @@ p_regd:
.long p_dyd7
pack_out:
- leal p_movet,%a0 |load jmp table address
+ leal p_movet,%a0 |load jmp table address
movew STAG(%a6),%d0 |get source tag
bfextu %d0{#16:#3},%d0 |isolate source bits
movel (%a0,%d0.w*4),%a0 |load a0 with routine label for tag
jmp (%a0) |go to the routine
p_write:
- movel #0x0c,%d0 |get byte count
+ movel #0x0c,%d0 |get byte count
movel EXC_EA(%a6),%a1 |get the destination address
- bsr mem_write |write the user's destination
+ bsr mem_write |write the user's destination
moveb #0,CU_SAVEPC(%a6) |set the cu save pc to all 0's
|
-| Also note that the dtag must be set to norm here - this is because
+| Also note that the dtag must be set to norm here - this is because
| the 040 uses the dtag to execute the correct microcode.
|
bfclr DTAG(%a6){#0:#3} |set dtag to norm
diff -puN arch/m68k/fpsp040/round.S~m68k-superfluous-whitespace arch/m68k/fpsp040/round.S
--- 25/arch/m68k/fpsp040/round.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/round.S Thu Apr 22 13:43:13 2004
@@ -8,8 +8,8 @@
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
|ROUND idnt 2,1 | Motorola 040 Floating Point Software Package
@@ -21,7 +21,7 @@
|
| round --- round result according to precision/mode
|
-| a0 points to the input operand in the internal extended format
+| a0 points to the input operand in the internal extended format
| d1(high word) contains rounding precision:
| ext = $0000xxxx
| sgl = $0001xxxx
@@ -44,15 +44,15 @@
.global round
round:
-| If g=r=s=0 then result is exact and round is done, else set
-| the inex flag in status reg and continue.
+| If g=r=s=0 then result is exact and round is done, else set
+| the inex flag in status reg and continue.
|
- bsrs ext_grs |this subroutine looks at the
-| :rounding precision and sets
+ bsrs ext_grs |this subroutine looks at the
+| :rounding precision and sets
| ;the appropriate g-r-s bits.
tstl %d0 |if grs are zero, go force
bne rnd_cont |lower bits to zero for size
-
+
swap %d1 |set up d1.w for round prec.
bra truncate
@@ -79,7 +79,7 @@ mode_tab:
| If sign of fp number = 0 (positive), then add 1 to l.
|
rnd_plus:
- swap %d1 |set up d1 for round prec.
+ swap %d1 |set up d1 for round prec.
tstb LOCAL_SGN(%a0) |check for sign
bmi truncate |if positive then truncate
movel #0xffffffff,%d0 |force g,r,s to be all f's
@@ -92,8 +92,8 @@ rnd_plus:
| If sign of fp number = 1 (negative), then add 1 to l.
|
rnd_mnus:
- swap %d1 |set up d1 for round prec.
- tstb LOCAL_SGN(%a0) |check for sign
+ swap %d1 |set up d1 for round prec.
+ tstb LOCAL_SGN(%a0) |check for sign
bpl truncate |if negative then truncate
movel #0xffffffff,%d0 |force g,r,s to be all f's
lea add_to_l,%a1
@@ -104,7 +104,7 @@ rnd_mnus:
|
| Always truncate.
rnd_zero:
- swap %d1 |set up d1 for round prec.
+ swap %d1 |set up d1 for round prec.
bra truncate
|
|
@@ -114,7 +114,7 @@ rnd_zero:
| Note that this will round to even in case of a tie.
|
rnd_near:
- swap %d1 |set up d1 for round prec.
+ swap %d1 |set up d1 for round prec.
asll #1,%d0 |shift g-bit to c-bit
bcc truncate |if (g=1) then
lea add_to_l,%a1
@@ -125,11 +125,11 @@ rnd_near:
| ext_grs --- extract guard, round and sticky bits
|
| Input: d1 = PREC:ROUND
-| Output: d0{31:29}= guard, round, sticky
+| Output: d0{31:29}= guard, round, sticky
|
| The ext_grs extract the guard/round/sticky bits according to the
| selected rounding precision. It is called by the round subroutine
-| only. All registers except d0 are kept intact. d0 becomes an
+| only. All registers except d0 are kept intact. d0 becomes an
| updated guard,round,sticky in d0{31:29}
|
| Notes: the ext_grs uses the round PREC, and therefore has to swap d1
@@ -140,7 +140,7 @@ ext_grs:
cmpiw #0,%d1
bnes sgl_or_dbl
bras end_ext_grs
-
+
sgl_or_dbl:
moveml %d2/%d3,-(%a7) |make some temp registers
cmpiw #1,%d1
@@ -150,19 +150,19 @@ grs_sgl:
movel #30,%d2 |of the sgl prec. limits
lsll %d2,%d3 |shift g-r bits to MSB of d3
movel LOCAL_HI(%a0),%d2 |get word 2 for s-bit test
- andil #0x0000003f,%d2 |s bit is the or of all other
+ andil #0x0000003f,%d2 |s bit is the or of all other
bnes st_stky |bits to the right of g-r
tstl LOCAL_LO(%a0) |test lower mantissa
bnes st_stky |if any are set, set sticky
tstl %d0 |test original g,r,s
bnes st_stky |if any are set, set sticky
bras end_sd |if words 3 and 4 are clr, exit
-grs_dbl:
+grs_dbl:
bfextu LOCAL_LO(%a0){#21:#2},%d3 |dbl-prec. g-r are 2 bits right
movel #30,%d2 |of the dbl prec. limits
lsll %d2,%d3 |shift g-r bits to the MSB of d3
movel LOCAL_LO(%a0),%d2 |get lower mantissa for s-bit test
- andil #0x000001ff,%d2 |s bit is the or-ing of all
+ andil #0x000001ff,%d2 |s bit is the or-ing of all
bnes st_stky |other bits to the right of g-r
tstl %d0 |test word original g,r,s
bnes st_stky |if any are set, set sticky
@@ -269,20 +269,20 @@ end_rnd:
|
| NORMALIZE
|
-| These routines (nrm_zero & nrm_set) normalize the unnorm. This
-| is done by shifting the mantissa left while decrementing the
+| These routines (nrm_zero & nrm_set) normalize the unnorm. This
+| is done by shifting the mantissa left while decrementing the
| exponent.
|
-| NRM_SET shifts and decrements until there is a 1 set in the integer
+| NRM_SET shifts and decrements until there is a 1 set in the integer
| bit of the mantissa (msb in d1).
|
-| NRM_ZERO shifts and decrements until there is a 1 set in the integer
-| bit of the mantissa (msb in d1) unless this would mean the exponent
-| would go less than 0. In that case the number becomes a denorm - the
-| exponent (d0) is set to 0 and the mantissa (d1 & d2) is not
+| NRM_ZERO shifts and decrements until there is a 1 set in the integer
+| bit of the mantissa (msb in d1) unless this would mean the exponent
+| would go less than 0. In that case the number becomes a denorm - the
+| exponent (d0) is set to 0 and the mantissa (d1 & d2) is not
| normalized.
|
-| Note that both routines have been optimized (for the worst case) and
+| Note that both routines have been optimized (for the worst case) and
| therefore do not have the easy to follow decrement/shift loop.
|
| NRM_ZERO
@@ -304,34 +304,34 @@ end_rnd:
.global nrm_zero
nrm_zero:
movew LOCAL_EX(%a0),%d0
- cmpw #64,%d0 |see if exp > 64
+ cmpw #64,%d0 |see if exp > 64
bmis d0_less
- bsr nrm_set |exp > 64 so exp won't exceed 0
+ bsr nrm_set |exp > 64 so exp won't exceed 0
rts
d0_less:
moveml %d2/%d3/%d5/%d6,-(%a7)
movel LOCAL_HI(%a0),%d1
movel LOCAL_LO(%a0),%d2
- bfffo %d1{#0:#32},%d3 |get the distance to the first 1
+ bfffo %d1{#0:#32},%d3 |get the distance to the first 1
| ;in ms mant
beqs ms_clr |branch if no bits were set
cmpw %d3,%d0 |of X>Y
- bmis greater |then exp will go past 0 (neg) if
+ bmis greater |then exp will go past 0 (neg) if
| ;it is just shifted
bsr nrm_set |else exp won't go past 0
moveml (%a7)+,%d2/%d3/%d5/%d6
- rts
+ rts
greater:
movel %d2,%d6 |save ls mant in d6
lsll %d0,%d2 |shift ls mant by count
lsll %d0,%d1 |shift ms mant by count
movel #32,%d5
- subl %d0,%d5 |make op a denorm by shifting bits
- lsrl %d5,%d6 |by the number in the exp, then
+ subl %d0,%d5 |make op a denorm by shifting bits
+ lsrl %d5,%d6 |by the number in the exp, then
| ;set exp = 0.
orl %d6,%d1 |shift the ls mant bits into the ms mant
- movel #0,%d0 |same as if decremented exp to 0
+ movel #0,%d0 |same as if decremented exp to 0
| ;while shifting
movew %d0,LOCAL_EX(%a0)
movel %d1,LOCAL_HI(%a0)
@@ -380,7 +380,7 @@ nrm_set:
rts
|
-| We get here if ms mant was = 0, and we assume ls mant has bits
+| We get here if ms mant was = 0, and we assume ls mant has bits
| set (otherwise this would have been tagged a zero not a denorm).
|
lower:
@@ -400,26 +400,26 @@ lower:
|
| Used by underflow.
|
-| Input:
+| Input:
| a0 points to the operand to be denormalized
| (in the internal extended format)
-|
-| d0: rounding precision
+|
+| d0: rounding precision
| Output:
| a0 points to the denormalized result
| (in the internal extended format)
|
-| d0 is guard,round,sticky
+| d0 is guard,round,sticky
|
-| d0 comes into this routine with the rounding precision. It
-| is then loaded with the denormalized exponent threshold for the
+| d0 comes into this routine with the rounding precision. It
+| is then loaded with the denormalized exponent threshold for the
| rounding precision.
|
.global denorm
denorm:
btstb #6,LOCAL_EX(%a0) |check for exponents between $7fff-$4000
- beqs no_sgn_ext
+ beqs no_sgn_ext
bsetb #7,LOCAL_EX(%a0) |sign extend if it is so
no_sgn_ext:
@@ -442,7 +442,7 @@ load_dbl:
movel %d1,%d0 |copy d1 into d0
subw LOCAL_EX(%a0),%d0 |diff = threshold - exp
cmpw #67,%d0 |if diff > 67 (mant + grs bits)
- bpls chk_stky |then branch (all bits would be
+ bpls chk_stky |then branch (all bits would be
| ; shifted off in denorm routine)
clrl %d0 |else clear the sticky flag
bsr dnrm_lp |denormalize the number
@@ -455,7 +455,7 @@ load_sgl:
movel %d1,%d0 |copy d1 into d0
subw LOCAL_EX(%a0),%d0 |diff = threshold - exp
cmpw #67,%d0 |if diff > 67 (mant + grs bits)
- bpls chk_stky |then branch (all bits would be
+ bpls chk_stky |then branch (all bits would be
| ; shifted off in denorm routine)
clrl %d0 |else clear the sticky flag
bsr dnrm_lp |denormalize the number
@@ -474,7 +474,7 @@ set_stky:
movel #0x20000000,%d0 |set sticky bit in return value
clr_mant:
movew %d1,LOCAL_EX(%a0) |load exp with threshold
- movel #0,LOCAL_HI(%a0) |set d1 = 0 (ms mantissa)
+ movel #0,LOCAL_HI(%a0) |set d1 = 0 (ms mantissa)
movel #0,LOCAL_LO(%a0) |set d2 = 0 (ms mantissa)
rts
dnrm_inex:
@@ -487,7 +487,7 @@ no_inex:
|
| Input:
| a0 points to the operand to be denormalized
-| d0{31:29} initial guard,round,sticky
+| d0{31:29} initial guard,round,sticky
| d1{15:0} denormalization threshold
| Output:
| a0 points to the denormalized operand
@@ -496,7 +496,7 @@ no_inex:
|
| The LOCAL_LO and LOCAL_GRS parts of the value are copied to FP_SCR2
| so that bfext can be used to extract the new low part of the mantissa.
-| Dnrm_lp can be called with a0 pointing to ETEMP or WBTEMP and there
+| Dnrm_lp can be called with a0 pointing to ETEMP or WBTEMP and there
| is no LOCAL_GRS scratch word following it on the fsave frame.
|
.global dnrm_lp
@@ -515,8 +515,8 @@ not_E3:
movel %d1,%d0 |copy the denorm threshold
subw LOCAL_EX(%a0),%d1 |d1 = threshold - uns exponent
bles no_lp |d1 <= 0
- cmpw #32,%d1
- blts case_1 |0 = d1 < 32
+ cmpw #32,%d1
+ blts case_1 |0 = d1 < 32
cmpw #64,%d1
blts case_2 |32 <= d1 < 64
bra case_3 |d1 >= 64
@@ -542,7 +542,7 @@ case_1:
movel %d2,LOCAL_HI(%a0) |store new LOCAL_HI
movel %d1,LOCAL_LO(%a0) |store new LOCAL_LO
clrb %d1
- bftst %d0{#2:#30}
+ bftst %d0{#2:#30}
beqs c1nstky
bsetl #rnd_stky_bit,%d0
st %d1
@@ -585,7 +585,7 @@ end_c2:
movel FP_SCR2+LOCAL_GRS(%a6),%d2 |restore original g,r,s
andil #0xe0000000,%d2 |clear all but G,R,S
tstl %d2 |test if original G,R,S are clear
- beqs clear_grs
+ beqs clear_grs
orl #0x20000000,%d0 |set sticky bit in d0
clear_grs:
andil #0xe0000000,%d0 |get rid of all but G,R,S
@@ -621,7 +621,7 @@ sixty_four:
bfextu %d0{#2:#30},%d1
andil #0xc0000000,%d0
bras c3com
-
+
sixty_five:
movel LOCAL_HI(%a0),%d0
bfextu %d0{#1:#31},%d1
diff -puN arch/m68k/fpsp040/sacos.S~m68k-superfluous-whitespace arch/m68k/fpsp040/sacos.S
--- 25/arch/m68k/fpsp040/sacos.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/sacos.S Thu Apr 22 13:43:13 2004
@@ -12,7 +12,7 @@
|
| Accuracy and Monotonicity: The returned result is within 3 ulps in
| 64 significant bit, i.e. within 0.5001 ulp to 53 bits if the
-| result is subsequently rounded to double precision. The
+| result is subsequently rounded to double precision. The
| result is provably monotonic in double precision.
|
| Speed: The program sCOS takes approximately 310 cycles.
@@ -38,8 +38,8 @@
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
|SACOS idnt 2,1 | Motorola 040 Floating Point Software Package
@@ -74,17 +74,17 @@ sacos:
|--ACOS(X) = 2 * ATAN( SQRT( (1-X)/(1+X) ) )
fmoves #0x3F800000,%fp1
- faddx %fp0,%fp1 | ...1+X
- fnegx %fp0 | ... -X
+ faddx %fp0,%fp1 | ...1+X
+ fnegx %fp0 | ... -X
fadds #0x3F800000,%fp0 | ...1-X
- fdivx %fp1,%fp0 | ...(1-X)/(1+X)
+ fdivx %fp1,%fp0 | ...(1-X)/(1+X)
fsqrtx %fp0 | ...SQRT((1-X)/(1+X))
fmovemx %fp0-%fp0,(%a0) | ...overwrite input
movel %d1,-(%sp) |save original users fpcr
clrl %d1
bsr satan | ...ATAN(SQRT([1-X]/[1+X]))
fmovel (%sp)+,%fpcr |restore users exceptions
- faddx %fp0,%fp0 | ...2 * ATAN( STUFF )
+ faddx %fp0,%fp0 | ...2 * ATAN( STUFF )
bra t_frcinx
ACOSBIG:
@@ -110,6 +110,6 @@ ACOSBIG:
ACOSP1:
fmovel %d1,%FPCR
fmoves #0x00000000,%fp0
- rts |Facos ; of +1 is exact
+ rts |Facos ; of +1 is exact
|end
diff -puN arch/m68k/fpsp040/sasin.S~m68k-superfluous-whitespace arch/m68k/fpsp040/sasin.S
--- 25/arch/m68k/fpsp040/sasin.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/sasin.S Thu Apr 22 13:43:13 2004
@@ -12,7 +12,7 @@
|
| Accuracy and Monotonicity: The returned result is within 3 ulps in
| 64 significant bit, i.e. within 0.5001 ulp to 53 bits if the
-| result is subsequently rounded to double precision. The
+| result is subsequently rounded to double precision. The
| result is provably monotonic in double precision.
|
| Speed: The program sASIN takes approximately 310 cycles.
@@ -38,8 +38,8 @@
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
|SASIN idnt 2,1 | Motorola 040 Floating Point Software Package
@@ -80,7 +80,7 @@ sasin:
fmulx %fp2,%fp1 | ...(1+X)(1-X)
fmovemx (%a7)+,%fp2-%fp2
fsqrtx %fp1 | ...SQRT([1-X][1+X])
- fdivx %fp1,%fp0 | ...X/SQRT([1-X][1+X])
+ fdivx %fp1,%fp0 | ...X/SQRT([1-X][1+X])
fmovemx %fp0-%fp0,(%a0)
bsr satan
bra t_frcinx
@@ -97,7 +97,7 @@ asinbig:
andil #0x80000000,%d0 | ...SIGN BIT OF X
oril #0x3F800000,%d0 | ...+-1 IN SGL FORMAT
movel %d0,-(%sp) | ...push SIGN(X) IN SGL-FMT
- fmovel %d1,%FPCR
+ fmovel %d1,%FPCR
fmuls (%sp)+,%fp0
bra t_frcinx
diff -puN arch/m68k/fpsp040/satanh.S~m68k-superfluous-whitespace arch/m68k/fpsp040/satanh.S
--- 25/arch/m68k/fpsp040/satanh.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/satanh.S Thu Apr 22 13:43:13 2004
@@ -13,7 +13,7 @@
|
| Accuracy and Monotonicity: The returned result is within 3 ulps in
| 64 significant bit, i.e. within 0.5001 ulp to 53 bits if the
-| result is subsequently rounded to double precision. The
+| result is subsequently rounded to double precision. The
| result is provably monotonic in double precision.
|
| Speed: The program satanh takes approximately 270 cycles.
@@ -33,7 +33,7 @@
| 3. If |X| > 1, go to 5.
|
| 4. (|X| = 1) Generate infinity with an appropriate sign and
-| divide-by-zero by
+| divide-by-zero by
| sgn := sign(X)
| atan(X) := sgn / (+0).
| Exit.
@@ -45,8 +45,8 @@
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
|satanh idnt 2,1 | Motorola 040 Floating Point Software Package
diff -puN arch/m68k/fpsp040/satan.S~m68k-superfluous-whitespace arch/m68k/fpsp040/satan.S
--- 25/arch/m68k/fpsp040/satan.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/satan.S Thu Apr 22 13:43:13 2004
@@ -43,8 +43,8 @@
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
|satan idnt 2,1 | Motorola 040 Floating Point Software Package
@@ -52,7 +52,7 @@
|section 8
#include "fpsp.h"
-
+
BOUNDS1: .long 0x3FFB8000,0x4002FFFF
ONE: .long 0x3F800000
@@ -322,7 +322,7 @@ ATANMAIN:
|--THE REASON FOR THIS REARRANGEMENT IS TO MAKE THE INDEPENDENT
|--PARTS A1*U*V AND (A2 + ... STUFF) MORE LOAD-BALANCED
-
+
fmovex %fp0,%fp1
fmulx %fp1,%fp1
fmoved ATANA3,%fp2
@@ -332,7 +332,7 @@ ATANMAIN:
faddd ATANA2,%fp2 | ...A2+V*(A3+V)
fmuld ATANA1,%fp1 | ...A1*U*V
fmulx %fp2,%fp1 | ...A1*U*V*(A2+V*(A3+V))
-
+
faddx %fp1,%fp0 | ...ATAN(U), FP1 RELEASED
fmovel %d1,%FPCR |restore users exceptions
faddx ATANF(%a6),%fp0 | ...ATAN(X)
@@ -356,7 +356,7 @@ ATANSM:
|--COMPUTE POLYNOMIAL
fmulx %fp0,%fp0 | ...FP0 IS Y = X*X
-
+
movew #0x0000,XDCARE(%a6)
fmovex %fp0,%fp1
@@ -381,7 +381,7 @@ ATANSM:
fmulx X(%a6),%fp0 | ...X*Y
faddx %fp2,%fp1 | ...[B1+Z*(B3+Z*B5)]+[Y*(B2+Z*(B4+Z*B6))]
-
+
fmulx %fp1,%fp0 | ...X*Y*([B1+Z*(B3+Z*B5)]+[Y*(B2+Z*(B4+Z*B6))])
@@ -413,7 +413,7 @@ ATANBIG:
fmoves #0xBF800000,%fp1 | ...LOAD -1
fdivx %fp0,%fp1 | ...FP1 IS -1/X
-
+
|--DIVIDE IS STILL CRANKING
fmovex %fp1,%fp0 | ...FP0 IS X'
@@ -439,14 +439,14 @@ ATANBIG:
fmulx X(%a6),%fp0 | ...X'*Y
faddx %fp2,%fp1 | ...[Y*(C2+Z*C4)]+[C1+Z*(C3+Z*C5)]
-
+
fmulx %fp1,%fp0 | ...X'*Y*([B1+Z*(B3+Z*B5)]
| ... +[Y*(B2+Z*(B4+Z*B6))])
faddx X(%a6),%fp0
fmovel %d1,%FPCR |restore users exceptions
-
+
btstb #7,(%a0)
beqs pos_big
@@ -474,5 +474,5 @@ pos_huge:
fmovel %d1,%fpcr
fsubx PTINY,%fp0
bra t_frcinx
-
+
|end
diff -puN arch/m68k/fpsp040/scale.S~m68k-superfluous-whitespace arch/m68k/fpsp040/scale.S
--- 25/arch/m68k/fpsp040/scale.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/scale.S Thu Apr 22 13:43:13 2004
@@ -9,7 +9,7 @@
| The entry point sscale is called from do_func to emulate
| the fscale unimplemented instruction.
|
-| Input: Double-extended destination operand in FPTEMP,
+| Input: Double-extended destination operand in FPTEMP,
| double-extended source operand in ETEMP.
|
| Output: The function returns scale(X,Y) to fp0.
@@ -17,12 +17,12 @@
| Modifies: fp0.
|
| Algorithm:
-|
+|
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
|SCALE idnt 2,1 | Motorola 040 Floating Point Software Package
@@ -147,7 +147,7 @@ nden_exit:
src_neg:
addl %d0,%d1 |add src to dest
beqs denorm |if zero, result is denorm
- blts fix_dnrm |if negative, result is
+ blts fix_dnrm |if negative, result is
| ;needing denormalization
tstb L_SCR1(%a6)
beqs sneg_pos
@@ -161,7 +161,7 @@ sneg_pos:
|
| The result exponent is below denorm value. Test for catastrophic
-| underflow and force zero if true. If not, try to shift the
+| underflow and force zero if true. If not, try to shift the
| mantissa right until a zero exponent exists.
|
fix_dnrm:
@@ -229,7 +229,7 @@ no_dir:
rts
|
-| The rounding mode changed the zero to a smallest denorm. Call
+| The rounding mode changed the zero to a smallest denorm. Call
| t_resdnrm with exceptional operand in ETEMP.
|
sm_dnrm:
@@ -250,7 +250,7 @@ not_zero:
fix_exit:
bras sm_dnrm
-
+
|
| The result has underflowed to zero. Return zero and set
| unfl, aunfl, and ainex.
@@ -284,7 +284,7 @@ neg_zero:
clrl FP_SCR1(%a6) |clear the exceptional operand
clrl FP_SCR1+4(%a6) |for gen_except.
clrl FP_SCR1+8(%a6)
- fmoves #0x80000000,%fp0
+ fmoves #0x80000000,%fp0
rts
pos_zero:
clrl FP_SCR1(%a6) |clear the exceptional operand
@@ -299,7 +299,7 @@ pos_zero:
| then adding the remainder of the source to the exponent.
|
dst_dnrm:
- moveml %d2/%d3,-(%a7)
+ moveml %d2/%d3,-(%a7)
movew FPTEMP_EX(%a6),%d1
movel FPTEMP_HI(%a6),%d2
movel FPTEMP_LO(%a6),%d3
@@ -313,7 +313,7 @@ dst_loop:
roxll #1,%d2
bras dst_loop
|
-| Destination became normalized. Simply add the remaining
+| Destination became normalized. Simply add the remaining
| portion of the src to the exponent.
|
dst_norm:
diff -puN arch/m68k/fpsp040/scosh.S~m68k-superfluous-whitespace arch/m68k/fpsp040/scosh.S
--- 25/arch/m68k/fpsp040/scosh.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/scosh.S Thu Apr 22 13:43:13 2004
@@ -49,8 +49,8 @@
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
|SCOSH idnt 2,1 | Motorola 040 Floating Point Software Package
@@ -99,7 +99,7 @@ scosh:
movel (%sp)+,%d1
fmoves #0x3E800000,%fp1 | ...(1/4)
- fdivx %fp0,%fp1 | ...1/(2 EXP(|X|))
+ fdivx %fp0,%fp1 | ...1/(2 EXP(|X|))
fmovel %d1,%FPCR
faddx %fp1,%fp0
diff -puN arch/m68k/fpsp040/setox.S~m68k-superfluous-whitespace arch/m68k/fpsp040/setox.S
--- 25/arch/m68k/fpsp040/setox.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/setox.S Thu Apr 22 13:43:13 2004
@@ -331,8 +331,8 @@
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
|setox idnt 2,1 | Motorola 040 Floating Point Software Package
@@ -505,7 +505,7 @@ EXPCONT1:
fmovex %fp0,%fp2
fmuls #0xBC317218,%fp0 | ...N * L1, L1 = lead(-log2/64)
fmulx L2,%fp2 | ...N * L2, L1+L2 = -log2/64
- faddx %fp1,%fp0 | ...X + N*L1
+ faddx %fp1,%fp0 | ...X + N*L1
faddx %fp2,%fp0 | ...fp0 is R, reduced arg.
| MOVE.W #$3FA5,EXPA3 ...load EXPA3 in cache
@@ -516,46 +516,46 @@ EXPCONT1:
|--[R+R*S*(A2+S*A4)] + [S*(A1+S*(A3+S*A5))]
fmovex %fp0,%fp1
- fmulx %fp1,%fp1 | ...fp1 IS S = R*R
+ fmulx %fp1,%fp1 | ...fp1 IS S = R*R
fmoves #0x3AB60B70,%fp2 | ...fp2 IS A5
| MOVE.W #0,2(%a1) ...load 2^(J/64) in cache
- fmulx %fp1,%fp2 | ...fp2 IS S*A5
+ fmulx %fp1,%fp2 | ...fp2 IS S*A5
fmovex %fp1,%fp3
fmuls #0x3C088895,%fp3 | ...fp3 IS S*A4
faddd EXPA3,%fp2 | ...fp2 IS A3+S*A5
faddd EXPA2,%fp3 | ...fp3 IS A2+S*A4
- fmulx %fp1,%fp2 | ...fp2 IS S*(A3+S*A5)
+ fmulx %fp1,%fp2 | ...fp2 IS S*(A3+S*A5)
movew %d0,SCALE(%a6) | ...SCALE is 2^(M) in extended
clrw SCALE+2(%a6)
movel #0x80000000,SCALE+4(%a6)
clrl SCALE+8(%a6)
- fmulx %fp1,%fp3 | ...fp3 IS S*(A2+S*A4)
+ fmulx %fp1,%fp3 | ...fp3 IS S*(A2+S*A4)
fadds #0x3F000000,%fp2 | ...fp2 IS A1+S*(A3+S*A5)
- fmulx %fp0,%fp3 | ...fp3 IS R*S*(A2+S*A4)
+ fmulx %fp0,%fp3 | ...fp3 IS R*S*(A2+S*A4)
- fmulx %fp1,%fp2 | ...fp2 IS S*(A1+S*(A3+S*A5))
- faddx %fp3,%fp0 | ...fp0 IS R+R*S*(A2+S*A4),
+ fmulx %fp1,%fp2 | ...fp2 IS S*(A1+S*(A3+S*A5))
+ faddx %fp3,%fp0 | ...fp0 IS R+R*S*(A2+S*A4),
| ...fp3 released
fmovex (%a1)+,%fp1 | ...fp1 is lead. pt. of 2^(J/64)
- faddx %fp2,%fp0 | ...fp0 is EXP(R) - 1
+ faddx %fp2,%fp0 | ...fp0 is EXP(R) - 1
| ...fp2 released
|--Step 5
|--final reconstruction process
|--EXP(X) = 2^M * ( 2^(J/64) + 2^(J/64)*(EXP(R)-1) )
- fmulx %fp1,%fp0 | ...2^(J/64)*(Exp(R)-1)
+ fmulx %fp1,%fp0 | ...2^(J/64)*(Exp(R)-1)
fmovemx (%a7)+,%fp2-%fp2/%fp3 | ...fp2 restored
fadds (%a1),%fp0 | ...accurate 2^(J/64)
- faddx %fp1,%fp0 | ...2^(J/64) + 2^(J/64)*...
+ faddx %fp1,%fp0 | ...2^(J/64) + 2^(J/64)*...
movel ADJFLAG(%a6),%d0
|--Step 6
@@ -564,7 +564,7 @@ EXPCONT1:
ADJUST:
fmulx ADJSCALE(%a6),%fp0
NORMAL:
- fmovel %d1,%FPCR | ...restore user FPCR
+ fmovel %d1,%FPCR | ...restore user FPCR
fmulx SCALE(%a6),%fp0 | ...multiply 2^(M)
bra t_frcinx
diff -puN arch/m68k/fpsp040/sgetem.S~m68k-superfluous-whitespace arch/m68k/fpsp040/sgetem.S
--- 25/arch/m68k/fpsp040/sgetem.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/sgetem.S Thu Apr 22 13:43:13 2004
@@ -1,14 +1,14 @@
|
| sgetem.sa 3.1 12/10/90
|
-| The entry point sGETEXP returns the exponent portion
+| The entry point sGETEXP returns the exponent portion
| of the input argument. The exponent bias is removed
-| and the exponent value is returned as an extended
+| and the exponent value is returned as an extended
| precision number in fp0. sGETEXPD handles denormalized
| numbers.
|
-| The entry point sGETMAN extracts the mantissa of the
-| input argument. The mantissa is converted to an
+| The entry point sGETMAN extracts the mantissa of the
+| input argument. The mantissa is converted to an
| extended precision number and returned in fp0. The
| range of the result is [1.0 - 2.0).
|
@@ -24,8 +24,8 @@
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
|SGETEM idnt 2,1 | Motorola 040 Floating Point Software Package
@@ -81,7 +81,7 @@ sgetman:
fmovel %d0,%fpcr |this fpcr setting is used by the 882
movew LOCAL_EX(%a0),%d0 |get the exp (really just want sign bit)
orw #0x7fff,%d0 |clear old exp
- bclrl #14,%d0 |make it the new exp +-3fff
+ bclrl #14,%d0 |make it the new exp +-3fff
movew %d0,LOCAL_EX(%a0) |move the sign & exp back to fsave stack
fmovex (%a0),%fp0 |put new value back in fp0
rts
diff -puN arch/m68k/fpsp040/sint.S~m68k-superfluous-whitespace arch/m68k/fpsp040/sint.S
--- 25/arch/m68k/fpsp040/sint.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/sint.S Thu Apr 22 13:43:13 2004
@@ -1,8 +1,8 @@
|
| sint.sa 3.1 12/10/90
|
-| The entry point sINT computes the rounded integer
-| equivalent of the input argument, sINTRZ computes
+| The entry point sINT computes the rounded integer
+| equivalent of the input argument, sINTRZ computes
| the integer rounded to zero of the input argument.
|
| Entry points sint and sintrz are called from do_func
@@ -24,10 +24,10 @@
|
| Algorithm: (sint and sintrz)
|
-| 1. If exp(X) >= 63, return X.
+| 1. If exp(X) >= 63, return X.
| If exp(X) < 0, return +/- 0 or +/- 1, according to
| the rounding mode.
-|
+|
| 2. (X is in range) set rsc = 63 - exp(X). Unnormalize the
| result to the exponent $403e.
|
@@ -51,8 +51,8 @@
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
|SINT idnt 2,1 | Motorola 040 Floating Point Software Package
@@ -78,9 +78,9 @@
sint:
bfextu FPCR_MODE(%a6){#2:#2},%d1 |use user's mode for rounding
| ;implicitly has extend precision
-| ;in upper word.
+| ;in upper word.
movel %d1,L_SCR1(%a6) |save mode bits
- bras sintexc
+ bras sintexc
|
| FINT with extended denorm inputs.
@@ -115,13 +115,13 @@ sintmz:
sintrz:
movel #1,L_SCR1(%a6) |use rz mode for rounding
| ;implicitly has extend precision
-| ;in upper word.
- bras sintexc
+| ;in upper word.
+ bras sintexc
|
| SINTDO
|
| Input: a0 points to an IEEE extended format operand
-| Output: fp0 has the result
+| Output: fp0 has the result
|
| Exceptions:
|
@@ -133,7 +133,7 @@ sintrz:
sintdo:
bfextu FPCR_MODE(%a6){#2:#2},%d1 |use user's mode for rounding
| ;implicitly has ext precision
-| ;in upper word.
+| ;in upper word.
movel %d1,L_SCR1(%a6) |save mode bits
|
| Real work of sint is in sintexc
@@ -141,7 +141,7 @@ sintdo:
sintexc:
bclrb #sign_bit,LOCAL_EX(%a0) |convert to internal extended
| ;format
- sne LOCAL_SGN(%a0)
+ sne LOCAL_SGN(%a0)
cmpw #0x403e,LOCAL_EX(%a0) |check if (unbiased) exp > 63
bgts out_rnge |branch if exp < 63
cmpw #0x3ffd,LOCAL_EX(%a0) |check if (unbiased) exp < 0
@@ -187,7 +187,7 @@ un_rnrz:
un_rnrz_neg:
bsr ld_mzero
bra t_inx2
-
+
|
| Input is greater than 2^63. All bits are significant. Return
| the input.
@@ -206,7 +206,7 @@ intps:
rts
in_rnge:
-| ;shift off fraction bits
+| ;shift off fraction bits
clrl %d0 |clear d0 - initial g,r,s for
| ;dnrm_lp
movel #0x403e,%d1 |set threshold for dnrm_lp
diff -puN arch/m68k/fpsp040/skeleton.S~m68k-superfluous-whitespace arch/m68k/fpsp040/skeleton.S
--- 25/arch/m68k/fpsp040/skeleton.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/skeleton.S Thu Apr 22 13:43:13 2004
@@ -18,20 +18,20 @@
| to handle the exception.
|
| If the exception was completely handled by the package, then
-| the return will be via a 'jmp fpsp_done'. Unless there is
+| the return will be via a 'jmp fpsp_done'. Unless there is
| OS specific work to be done (such as handling a context switch or
| interrupt) the user program can be resumed via 'rte'.
|
| In the following skeleton code, some typical 'real_xxxx' handling
| code is shown. This code may need to be moved to an appropriate
| place in the target system, or rewritten.
-|
+|
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
|
@@ -50,7 +50,7 @@
|
|section 8
-
+
#include "fpsp.h"
|xref b1238_fix
@@ -72,7 +72,7 @@ real_dz:
SAVE_ALL_INT
GET_CURRENT(%d0)
- movel %sp,%sp@- | stack frame pointer argument
+ movel %sp,%sp@- | stack frame pointer argument
bsrl trap_c
addql #4,%sp
bral ret_from_exception
@@ -82,7 +82,7 @@ real_dz:
|
| All inexact exceptions are real, but the 'real' handler
| will probably want to clear the pending exception.
-| The provided code will clear the E3 exception (if pending),
+| The provided code will clear the E3 exception (if pending),
| otherwise clear the E1 exception. The frestore is not really
| necessary for E1 exceptions.
|
@@ -96,7 +96,7 @@ real_dz:
| to the appropriate handler for the exception in the fpsr. Note
| that this fix is only for d43b parts, and is skipped if the
| version number is not $40.
-|
+|
|
.global real_inex
.global inex
@@ -116,7 +116,7 @@ inex:
bra snan
inex_ckofl:
btstb #ovfl_bit,2(%sp) |test for ovfl
- beq inex_ckufl
+ beq inex_ckufl
addl #4,%sp
frestore (%sp)+
unlk %a6
@@ -163,11 +163,11 @@ inex_done:
SAVE_ALL_INT
GET_CURRENT(%d0)
- movel %sp,%sp@- | stack frame pointer argument
+ movel %sp,%sp@- | stack frame pointer argument
bsrl trap_c
addql #4,%sp
bral ret_from_exception
-
+
|
| Overflow exception
|
@@ -189,11 +189,11 @@ ovfl_done:
SAVE_ALL_INT
GET_CURRENT(%d0)
- movel %sp,%sp@- | stack frame pointer argument
+ movel %sp,%sp@- | stack frame pointer argument
bsrl trap_c
addql #4,%sp
bral ret_from_exception
-
+
|
| Underflow exception
|
@@ -215,11 +215,11 @@ unfl_done:
SAVE_ALL_INT
GET_CURRENT(%d0)
- movel %sp,%sp@- | stack frame pointer argument
+ movel %sp,%sp@- | stack frame pointer argument
bsrl trap_c
addql #4,%sp
bral ret_from_exception
-
+
|
| Signalling NAN exception
|
@@ -237,11 +237,11 @@ real_snan:
SAVE_ALL_INT
GET_CURRENT(%d0)
- movel %sp,%sp@- | stack frame pointer argument
+ movel %sp,%sp@- | stack frame pointer argument
bsrl trap_c
addql #4,%sp
bral ret_from_exception
-
+
|
| Operand Error exception
|
@@ -259,12 +259,12 @@ real_operr:
SAVE_ALL_INT
GET_CURRENT(%d0)
- movel %sp,%sp@- | stack frame pointer argument
+ movel %sp,%sp@- | stack frame pointer argument
bsrl trap_c
addql #4,%sp
bral ret_from_exception
-
+
|
| BSUN exception
|
@@ -287,7 +287,7 @@ real_bsun:
SAVE_ALL_INT
GET_CURRENT(%d0)
- movel %sp,%sp@- | stack frame pointer argument
+ movel %sp,%sp@- | stack frame pointer argument
bsrl trap_c
addql #4,%sp
bral ret_from_exception
@@ -295,7 +295,7 @@ real_bsun:
|
| F-line exception
|
-| A 'real' F-line exception is one that the FPSP isn't supposed to
+| A 'real' F-line exception is one that the FPSP isn't supposed to
| handle. E.g. an instruction with a co-processor ID that is not 1.
|
|
@@ -308,7 +308,7 @@ real_fline:
SAVE_ALL_INT
GET_CURRENT(%d0)
- movel %sp,%sp@- | stack frame pointer argument
+ movel %sp,%sp@- | stack frame pointer argument
bsrl trap_c
addql #4,%sp
bral ret_from_exception
@@ -330,7 +330,7 @@ real_unsupp:
SAVE_ALL_INT
GET_CURRENT(%d0)
- movel %sp,%sp@- | stack frame pointer argument
+ movel %sp,%sp@- | stack frame pointer argument
bsrl trap_c
addql #4,%sp
bral ret_from_exception
@@ -355,14 +355,14 @@ real_trace:
| {4028, 4130} - unimp frame
| {4000, 4100} - idle frame
|
-| This entry point simply holds an f-line illegal value.
+| This entry point simply holds an f-line illegal value.
| Replace this with a call to your kernel panic code or
| code to handle future revisions of the fpu.
|
.global fpsp_fmt_error
fpsp_fmt_error:
- .long 0xf27f0000 |f-line illegal
+ .long 0xf27f0000 |f-line illegal
|
| fpsp_done --- FPSP exit point
@@ -442,7 +442,7 @@ user_write:
| a1 - supervisor destination address
| d0 - number of bytes to read (maximum count is 12)
|
-| Like mem_write, mem_read always reads with a supervisor
+| Like mem_write, mem_read always reads with a supervisor
| destination address on the supervisor stack. Also like mem_write,
| the EXC_SR is checked and a simple memory copy is done if reading
| from supervisor space is indicated.
diff -puN arch/m68k/fpsp040/slog2.S~m68k-superfluous-whitespace arch/m68k/fpsp040/slog2.S
--- 25/arch/m68k/fpsp040/slog2.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/slog2.S Thu Apr 22 13:43:13 2004
@@ -1,28 +1,28 @@
|
| slog2.sa 3.1 12/10/90
|
-| The entry point slog10 computes the base-10
+| The entry point slog10 computes the base-10
| logarithm of an input argument X.
-| slog10d does the same except the input value is a
-| denormalized number.
+| slog10d does the same except the input value is a
+| denormalized number.
| sLog2 and sLog2d are the base-2 analogues.
|
-| INPUT: Double-extended value in memory location pointed to
+| INPUT: Double-extended value in memory location pointed to
| by address register a0.
|
-| OUTPUT: log_10(X) or log_2(X) returned in floating-point
+| OUTPUT: log_10(X) or log_2(X) returned in floating-point
| register fp0.
|
-| ACCURACY and MONOTONICITY: The returned result is within 1.7
-| ulps in 64 significant bit, i.e. within 0.5003 ulp
-| to 53 bits if the result is subsequently rounded
-| to double precision. The result is provably monotonic
+| ACCURACY and MONOTONICITY: The returned result is within 1.7
+| ulps in 64 significant bit, i.e. within 0.5003 ulp
+| to 53 bits if the result is subsequently rounded
+| to double precision. The result is provably monotonic
| in double precision.
|
-| SPEED: Two timings are measured, both in the copy-back mode.
-| The first one is measured when the function is invoked
-| the first time (so the instructions and data are not
-| in cache), and the second one is measured when the
+| SPEED: Two timings are measured, both in the copy-back mode.
+| The first one is measured when the function is invoked
+| the first time (so the instructions and data are not
+| in cache), and the second one is measured when the
| function is reinvoked at the same input argument.
|
| ALGORITHM and IMPLEMENTATION NOTES:
@@ -42,7 +42,7 @@
| 2.2 Return ans := Y * INV_L10.
|
|
-| slog10:
+| slog10:
|
| Step 0. If X < 0, create a NaN and raise the invalid operation
| flag. Otherwise, save FPCR in D1; set FpCR to default.
@@ -96,15 +96,15 @@
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
|SLOG2 idnt 2,1 | Motorola 040 Floating Point Software Package
|section 8
- |xref t_frcinx
+ |xref t_frcinx
|xref t_operr
|xref slogn
|xref slognd
diff -puN arch/m68k/fpsp040/slogn.S~m68k-superfluous-whitespace arch/m68k/fpsp040/slogn.S
--- 25/arch/m68k/fpsp040/slogn.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/slogn.S Thu Apr 22 13:43:13 2004
@@ -13,11 +13,11 @@
|
| Accuracy and Monotonicity: The returned result is within 2 ulps in
| 64 significant bit, i.e. within 0.5001 ulp to 53 bits if the
-| result is subsequently rounded to double precision. The
+| result is subsequently rounded to double precision. The
| result is provably monotonic in double precision.
|
-| Speed: The program slogn takes approximately 190 cycles for input
-| argument X such that |X-1| >= 1/16, which is the usual
+| Speed: The program slogn takes approximately 190 cycles for input
+| argument X such that |X-1| >= 1/16, which is the usual
| situation. For those arguments, slognp1 takes approximately
| 210 cycles. For the less common arguments, the program will
| run no worse than 10% slower.
@@ -45,26 +45,26 @@
| Step 2: Let 1+X = 2**k * Y, where 1 <= Y < 2. Define F as done in Step 2
| of the algorithm for LOGN and compute log(1+X) as
| k*log(2) + log(F) + poly where poly approximates log(1+u),
-| u = (Y-F)/F.
+| u = (Y-F)/F.
|
| Implementation Notes:
| Note 1. There are 64 different possible values for F, thus 64 log(F)'s
-| need to be tabulated. Moreover, the values of 1/F are also
+| need to be tabulated. Moreover, the values of 1/F are also
| tabulated so that the division in (Y-F)/F can be performed by a
| multiplication.
|
| Note 2. In Step 2 of lognp1, in order to preserved accuracy, the value
-| Y-F has to be calculated carefully when 1/2 <= X < 3/2.
+| Y-F has to be calculated carefully when 1/2 <= X < 3/2.
|
| Note 3. To fully exploit the pipeline, polynomials are usually separated
| into two parts evaluated independently before being added up.
-|
+|
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
|slogn idnt 2,1 | Motorola 040 Floating Point Software Package
@@ -262,7 +262,7 @@ slognd:
|----the value TWOTO100 is no longer needed.
|----Note that this code assumes the denormalized input is NON-ZERO.
- moveml %d2-%d7,-(%a7) | ...save some registers
+ moveml %d2-%d7,-(%a7) | ...save some registers
movel #0x00000000,%d3 | ...D3 is exponent of smallest norm. #
movel 4(%a0),%d4
movel 8(%a0),%d5 | ...(D4,D5) is (Hi_X,Lo_X)
@@ -347,14 +347,14 @@ LOGMAIN:
|--NOTE THAT U = (Y-F)/F IS VERY SMALL AND THUS APPROXIMATING
|--LOG(1+U) CAN BE VERY EFFICIENT.
|--ALSO NOTE THAT THE VALUE 1/F IS STORED IN A TABLE SO THAT NO
-|--DIVISION IS NEEDED TO CALCULATE (Y-F)/F.
+|--DIVISION IS NEEDED TO CALCULATE (Y-F)/F.
|--GET K, Y, F, AND ADDRESS OF 1/F.
asrl #8,%d0
asrl #8,%d0 | ...SHIFTED 16 BITS, BIASED EXPO. OF X
- subil #0x3FFF,%d0 | ...THIS IS K
+ subil #0x3FFF,%d0 | ...THIS IS K
addl ADJK(%a6),%d0 | ...ADJUST K, ORIGINAL INPUT MAY BE DENORM.
- lea LOGTBL,%a0 | ...BASE ADDRESS OF 1/F AND LOG(F)
+ lea LOGTBL,%a0 | ...BASE ADDRESS OF 1/F AND LOG(F)
fmovel %d0,%fp1 | ...CONVERT K TO FLOATING-POINT FORMAT
|--WHILE THE CONVERSION IS GOING ON, WE GET F AND ADDRESS OF 1/F
@@ -363,7 +363,7 @@ LOGMAIN:
andil #0xFE000000,FFRAC(%a6) | ...FIRST 7 BITS OF Y
oril #0x01000000,FFRAC(%a6) | ...GET F: ATTACH A 1 AT THE EIGHTH BIT
movel FFRAC(%a6),%d0 | ...READY TO GET ADDRESS OF 1/F
- andil #0x7E000000,%d0
+ andil #0x7E000000,%d0
asrl #8,%d0
asrl #8,%d0
asrl #4,%d0 | ...SHIFTED 20, D0 IS THE DISPLACEMENT
@@ -390,7 +390,7 @@ LP1CONT1:
|--[U + V*(A1+V*(A3+V*A5))] + [U*V*(A2+V*(A4+V*A6))]
fmovex %fp2,%fp3
- fmovex %fp2,%fp1
+ fmovex %fp2,%fp1
fmuld LOGA6,%fp1 | ...V*A6
fmuld LOGA5,%fp2 | ...V*A5
@@ -440,7 +440,7 @@ LP1CONT2:
fmovex %fp1,%fp0
fmulx %fp0,%fp0 | ...FP0 IS V
fmovex %fp1,SAVEU(%a6) | ...STORE U IN MEMORY, FREE FP1
- fmovex %fp0,%fp1
+ fmovex %fp0,%fp1
fmulx %fp1,%fp1 | ...FP1 IS W
fmoved LOGB5,%fp3
@@ -465,7 +465,7 @@ LP1CONT2:
fmulx %fp1,%fp0 | ...U*V*( [B1+W*(B3+W*B5)] + [V*(B2+W*B4)] )
fmovel %d1,%fpcr
- faddx SAVEU(%a6),%fp0
+ faddx SAVEU(%a6),%fp0
bra t_frcinx
rts
@@ -549,7 +549,7 @@ KISNEG1:
asrl #8,%d0
asrl #4,%d0 | ...D0 CONTAINS DISPLACEMENT FOR 1/F
faddx %fp1,%fp1 | ...GET 2Z
- fmovemx %fp2-%fp2/%fp3,-(%sp) | ...SAVE FP2
+ fmovemx %fp2-%fp2/%fp3,-(%sp) | ...SAVE FP2
faddx %fp1,%fp0 | ...FP0 IS Y-F = (2-F)+2Z
lea LOGTBL,%a0 | ...A0 IS ADDRESS OF 1/F
addal %d0,%a0
@@ -569,7 +569,7 @@ KISZERO:
faddx %fp1,%fp0 | ...FP0 IS Y-F
fmovemx %fp2-%fp2/%fp3,-(%sp) | ...FP2 SAVED
lea LOGTBL,%a0
- addal %d0,%a0 | ...A0 IS ADDRESS OF 1/F
+ addal %d0,%a0 | ...A0 IS ADDRESS OF 1/F
fmoves zero,%fp1 | ...FP1 IS K = 0
bra LP1CONT1
diff -puN arch/m68k/fpsp040/smovecr.S~m68k-superfluous-whitespace arch/m68k/fpsp040/smovecr.S
--- 25/arch/m68k/fpsp040/smovecr.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/smovecr.S Thu Apr 22 13:43:13 2004
@@ -15,8 +15,8 @@
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
|SMOVECR idnt 2,1 | Motorola 040 Floating Point Software Package
@@ -39,7 +39,7 @@
FZERO: .long 00000000
|
-| FMOVECR
+| FMOVECR
|
.global smovcr
smovcr:
@@ -55,9 +55,9 @@ smovcr:
cmpib #0x0e,%d0 |check range $0b - $0e
bles SM_TBL |valid constants in this range
cmpib #0x2f,%d0 |check range $10 - $2f
- bles Z_VAL |if in this range, return zero
+ bles Z_VAL |if in this range, return zero
cmpib #0x3f,%d0 |check range $30 - $3f
- ble BG_TBL |valid constants in this range
+ ble BG_TBL |valid constants in this range
Z_VAL:
fmoves FZERO,%fp0
rts
@@ -149,7 +149,7 @@ not_ext:
lea FP_SCR1(%a6),%a0
btstb #sign_bit,LOCAL_EX(%a0)
sne LOCAL_SGN(%a0) |convert to internal ext. format
-
+
bsr round |go round the mantissa
bfclr LOCAL_SGN(%a0){#0:#8} |convert back to IEEE ext format
diff -puN arch/m68k/fpsp040/srem_mod.S~m68k-superfluous-whitespace arch/m68k/fpsp040/srem_mod.S
--- 25/arch/m68k/fpsp040/srem_mod.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/srem_mod.S Thu Apr 22 13:43:13 2004
@@ -21,7 +21,7 @@
| ---------
|
| Step 1. Save and strip signs of X and Y: signX := sign(X),
-| signY := sign(Y), X := |X|, Y := |Y|,
+| signY := sign(Y), X := |X|, Y := |Y|,
| signQ := signX EOR signY. Record whether MOD or REM
| is requested.
|
@@ -41,7 +41,7 @@
|
| Step 4. At this point, R = X - QY = MOD(X,Y). Set
| Last_Subtract := false (used in Step 7 below). If
-| MOD is requested, go to Step 6.
+| MOD is requested, go to Step 6.
|
| Step 5. R = MOD(X,Y), but REM(X,Y) is requested.
| 5.1 If R < Y/2, then R = MOD(X,Y) = REM(X,Y). Go to
@@ -61,13 +61,13 @@
| X = 2^(j)*(Q+1)Y. set Q := 2^(j)*(Q+1),
| R := 0. Return signQ, last 7 bits of Q, and R.
|
-|
-
+|
+
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
SREM_MOD: |idnt 2,1 | Motorola 040 Floating Point Software Package
@@ -362,10 +362,10 @@ Fix_Sign:
|..Get Q
|
Get_Q:
- clrl %d6
+ clrl %d6
movew SignQ(%a6),%d6 | ...D6 is sign(Q)
movel #8,%d7
- lsrl %d7,%d6
+ lsrl %d7,%d6
andil #0x0000007F,%d3 | ...7 bits of Q
orl %d6,%d3 | ...sign and bits of Q
swap %d3
@@ -391,7 +391,7 @@ Finish:
Rem_is_0:
|..R = 2^(-j)X - Q Y = Y, thus R = 0 and quotient = 2^j (Q+1)
addql #1,%d3
- cmpil #8,%d0 | ...D0 is j
+ cmpil #8,%d0 | ...D0 is j
bges Q_Big
lsll %d0,%d3
diff -puN arch/m68k/fpsp040/ssinh.S~m68k-superfluous-whitespace arch/m68k/fpsp040/ssinh.S
--- 25/arch/m68k/fpsp040/ssinh.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/ssinh.S Thu Apr 22 13:43:13 2004
@@ -5,7 +5,7 @@
| an input argument; sSinhd does the same except for denormalized
| input.
|
-| Input: Double-extended number X in location pointed to
+| Input: Double-extended number X in location pointed to
| by address register a0.
|
| Output: The value sinh(X) returned in floating-point register Fp0.
@@ -49,8 +49,8 @@
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
|SSINH idnt 2,1 | Motorola 040 Floating Point Software Package
@@ -91,7 +91,7 @@ ssinh:
moveml %a1/%d1,-(%sp)
fmovemx %fp0-%fp0,(%a0)
clrl %d1
- bsr setoxm1 | ...FP0 IS Z = EXPM1(Y)
+ bsr setoxm1 | ...FP0 IS Z = EXPM1(Y)
fmovel #0,%fpcr
moveml (%sp)+,%a1/%d1
diff -puN arch/m68k/fpsp040/ssin.S~m68k-superfluous-whitespace arch/m68k/fpsp040/ssin.S
--- 25/arch/m68k/fpsp040/ssin.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/ssin.S Thu Apr 22 13:43:13 2004
@@ -83,8 +83,8 @@
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
|SSIN idnt 2,1 | Motorola 040 Floating Point Software Package
@@ -204,7 +204,7 @@ SINMAIN:
|--HIDE THE NEXT THREE INSTRUCTIONS
lea PITBL+0x200,%a1 | ...TABLE OF N*PI/2, N = -32,...,32
-
+
|--FP1 IS NOW READY
fmovel %fp1,N(%a6) | ...CONVERT TO INTEGER
@@ -273,7 +273,7 @@ SINPOLY:
faddx %fp2,%fp1 | ...[A1+T(A3+T(A5+TA7))]+[S(A2+T(A4+TA6))]
|--FP3 RELEASED, RESTORE NOW AND TAKE SOME ADVANTAGE OF HIDING
|--FP2 RELEASED, RESTORE NOW AND TAKE FULL ADVANTAGE OF HIDING
-
+
fmulx %fp1,%fp0 | ...SIN(R')-R'
|--FP1 RELEASED.
@@ -335,7 +335,7 @@ COSPOLY:
fmulx %fp2,%fp0 | ...S(B2+T(B4+T(B6+TB8)))
|--FP3 RELEASED, RESTORE NOW AND TAKE SOME ADVANTAGE OF HIDING
|--FP2 RELEASED.
-
+
faddx %fp1,%fp0
|--FP1 RELEASED
@@ -352,7 +352,7 @@ SINBORS:
|--IF |X| < 2**(-40), RETURN X OR 1.
cmpil #0x3FFF8000,%d0
bgts REDUCEX
-
+
SINSM:
movel ADJN(%a6),%d0
@@ -466,7 +466,7 @@ WORK:
movew %d2,FP_SCR2(%a6)
clrw FP_SCR2+2(%a6)
movel #0xC90FDAA2,FP_SCR2+4(%a6)
- clrl FP_SCR2+8(%a6) | ...FP_SCR2 is 2**(L) * Piby2_1
+ clrl FP_SCR2+8(%a6) | ...FP_SCR2 is 2**(L) * Piby2_1
|--FP2 IS READY
fsubs TWOTO63(%a6),%fp2 | ...FP2 is N
@@ -514,7 +514,7 @@ RESTORE:
movel (%a7)+,%d2
fmovemx (%a7)+,%fp2-%fp5
-
+
movel ADJN(%a6),%d0
cmpil #4,%d0
@@ -559,7 +559,7 @@ SCMAIN:
|--HIDE THE NEXT THREE INSTRUCTIONS
lea PITBL+0x200,%a1 | ...TABLE OF N*PI/2, N = -32,...,32
-
+
|--FP1 IS NOW READY
fmovel %fp1,N(%a6) | ...CONVERT TO INTEGER
@@ -577,7 +577,7 @@ SCCONT:
|--HIDE THE NEXT TWO
movel N(%a6),%d0
rorl #1,%d0
-
+
cmpil #0,%d0 | ...D0 < 0 IFF N IS ODD
bge NEVEN
@@ -641,7 +641,7 @@ NODD:
fmulx %fp0,%fp1 | ...S(A1+...)
fmulx %fp2,%fp0 | ...S(B2+...)
-
+
fmulx RPRIME(%a6),%fp1 | ...R'S(A1+...)
fadds COSB1,%fp0 | ...B1+S(B2...)
@@ -709,7 +709,7 @@ NEVEN:
fmulx %fp0,%fp1 | ...S(B2+...)
fmulx %fp2,%fp0 | ...s(a1+...)
-
+
fadds COSB1,%fp1 | ...B1+S(B2...)
fmulx RPRIME(%a6),%fp0 | ...R'S(A1+...)
@@ -728,7 +728,7 @@ NEVEN:
SCBORS:
cmpil #0x3FFF8000,%d0
bgt REDUCEX
-
+
SCSM:
movew #0x0000,XDCARE(%a6)
diff -puN arch/m68k/fpsp040/stanh.S~m68k-superfluous-whitespace arch/m68k/fpsp040/stanh.S
--- 25/arch/m68k/fpsp040/stanh.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/stanh.S Thu Apr 22 13:43:13 2004
@@ -49,14 +49,14 @@
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
|STANH idnt 2,1 | Motorola 040 Floating Point Software Package
|section 8
-
+
#include "fpsp.h"
.set X,FP_SCR5
@@ -106,7 +106,7 @@ stanh:
movel %d1,-(%a7)
clrl %d1
fmovemx %fp0-%fp0,(%a0)
- bsr setoxm1 | ...FP0 IS Z = EXPM1(Y)
+ bsr setoxm1 | ...FP0 IS Z = EXPM1(Y)
movel (%a7)+,%d1
fmovex %fp0,%fp1
@@ -149,7 +149,7 @@ TANHBORS:
eorl #0xC0000000,%d0 | ...-SIGN(X)*2
fmoves %d0,%fp1 | ...-SIGN(X)*2 IN SGL FMT
- fdivx %fp0,%fp1 | ...-SIGN(X)2 / [EXP(Y)+1 ]
+ fdivx %fp0,%fp1 | ...-SIGN(X)2 / [EXP(Y)+1 ]
movel SGN(%a6),%d0
orl #0x3F800000,%d0 | ...SGN
diff -puN arch/m68k/fpsp040/stan.S~m68k-superfluous-whitespace arch/m68k/fpsp040/stan.S
--- 25/arch/m68k/fpsp040/stan.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/stan.S Thu Apr 22 13:43:13 2004
@@ -50,8 +50,8 @@
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
|STAN idnt 2,1 | Motorola 040 Floating Point Software Package
@@ -213,34 +213,34 @@ TANCONT:
blt NODD
fmovex %fp0,%fp1
- fmulx %fp1,%fp1 | ...S = R*R
+ fmulx %fp1,%fp1 | ...S = R*R
fmoved TANQ4,%fp3
fmoved TANP3,%fp2
- fmulx %fp1,%fp3 | ...SQ4
- fmulx %fp1,%fp2 | ...SP3
+ fmulx %fp1,%fp3 | ...SQ4
+ fmulx %fp1,%fp2 | ...SP3
faddd TANQ3,%fp3 | ...Q3+SQ4
faddx TANP2,%fp2 | ...P2+SP3
- fmulx %fp1,%fp3 | ...S(Q3+SQ4)
- fmulx %fp1,%fp2 | ...S(P2+SP3)
+ fmulx %fp1,%fp3 | ...S(Q3+SQ4)
+ fmulx %fp1,%fp2 | ...S(P2+SP3)
faddx TANQ2,%fp3 | ...Q2+S(Q3+SQ4)
faddx TANP1,%fp2 | ...P1+S(P2+SP3)
- fmulx %fp1,%fp3 | ...S(Q2+S(Q3+SQ4))
- fmulx %fp1,%fp2 | ...S(P1+S(P2+SP3))
+ fmulx %fp1,%fp3 | ...S(Q2+S(Q3+SQ4))
+ fmulx %fp1,%fp2 | ...S(P1+S(P2+SP3))
faddx TANQ1,%fp3 | ...Q1+S(Q2+S(Q3+SQ4))
- fmulx %fp0,%fp2 | ...RS(P1+S(P2+SP3))
+ fmulx %fp0,%fp2 | ...RS(P1+S(P2+SP3))
- fmulx %fp3,%fp1 | ...S(Q1+S(Q2+S(Q3+SQ4)))
-
+ fmulx %fp3,%fp1 | ...S(Q1+S(Q2+S(Q3+SQ4)))
+
+
+ faddx %fp2,%fp0 | ...R+RS(P1+S(P2+SP3))
- faddx %fp2,%fp0 | ...R+RS(P1+S(P2+SP3))
-
fadds #0x3F800000,%fp1 | ...1+S(Q1+...)
@@ -251,40 +251,40 @@ TANCONT:
NODD:
fmovex %fp0,%fp1
- fmulx %fp0,%fp0 | ...S = R*R
+ fmulx %fp0,%fp0 | ...S = R*R
fmoved TANQ4,%fp3
fmoved TANP3,%fp2
- fmulx %fp0,%fp3 | ...SQ4
- fmulx %fp0,%fp2 | ...SP3
+ fmulx %fp0,%fp3 | ...SQ4
+ fmulx %fp0,%fp2 | ...SP3
faddd TANQ3,%fp3 | ...Q3+SQ4
faddx TANP2,%fp2 | ...P2+SP3
- fmulx %fp0,%fp3 | ...S(Q3+SQ4)
- fmulx %fp0,%fp2 | ...S(P2+SP3)
+ fmulx %fp0,%fp3 | ...S(Q3+SQ4)
+ fmulx %fp0,%fp2 | ...S(P2+SP3)
faddx TANQ2,%fp3 | ...Q2+S(Q3+SQ4)
faddx TANP1,%fp2 | ...P1+S(P2+SP3)
- fmulx %fp0,%fp3 | ...S(Q2+S(Q3+SQ4))
- fmulx %fp0,%fp2 | ...S(P1+S(P2+SP3))
+ fmulx %fp0,%fp3 | ...S(Q2+S(Q3+SQ4))
+ fmulx %fp0,%fp2 | ...S(P1+S(P2+SP3))
faddx TANQ1,%fp3 | ...Q1+S(Q2+S(Q3+SQ4))
- fmulx %fp1,%fp2 | ...RS(P1+S(P2+SP3))
+ fmulx %fp1,%fp2 | ...RS(P1+S(P2+SP3))
+
+ fmulx %fp3,%fp0 | ...S(Q1+S(Q2+S(Q3+SQ4)))
- fmulx %fp3,%fp0 | ...S(Q1+S(Q2+S(Q3+SQ4)))
-
- faddx %fp2,%fp1 | ...R+RS(P1+S(P2+SP3))
+ faddx %fp2,%fp1 | ...R+RS(P1+S(P2+SP3))
fadds #0x3F800000,%fp0 | ...1+S(Q1+...)
-
+
fmovex %fp1,-(%sp)
eoril #0x80000000,(%sp)
- fmovel %d1,%fpcr |restore users exceptions
+ fmovel %d1,%fpcr |restore users exceptions
fdivx (%sp)+,%fp0 |last inst - possible exception set
bra t_frcinx
@@ -397,7 +397,7 @@ WORK:
movew %d2,FP_SCR2(%a6)
clrw FP_SCR2+2(%a6)
movel #0xC90FDAA2,FP_SCR2+4(%a6)
- clrl FP_SCR2+8(%a6) | ...FP_SCR2 is 2**(L) * Piby2_1
+ clrl FP_SCR2+8(%a6) | ...FP_SCR2 is 2**(L) * Piby2_1
|--FP2 IS READY
fsubs TWOTO63(%a6),%fp2 | ...FP2 is N
@@ -445,7 +445,7 @@ RESTORE:
movel (%a7)+,%d2
fmovemx (%a7)+,%fp2-%fp5
-
+
movel N(%a6),%d0
rorl #1,%d0
diff -puN arch/m68k/fpsp040/sto_res.S~m68k-superfluous-whitespace arch/m68k/fpsp040/sto_res.S
--- 25/arch/m68k/fpsp040/sto_res.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/sto_res.S Thu Apr 22 13:43:13 2004
@@ -5,9 +5,9 @@
| Library functions return result in fp0. If fp0 is not the
| users destination register then fp0 is moved to the
| correct floating-point destination register. fp0 and fp1
-| are then restored to the original contents.
+| are then restored to the original contents.
|
-| Input: result in fp0,fp1
+| Input: result in fp0,fp1
|
| d2 & a0 should be kept unmodified
|
@@ -19,8 +19,8 @@
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
STO_RES: |idnt 2,1 | Motorola 040 Floating Point Software Package
diff -puN arch/m68k/fpsp040/stwotox.S~m68k-superfluous-whitespace arch/m68k/fpsp040/stwotox.S
--- 25/arch/m68k/fpsp040/stwotox.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/stwotox.S Thu Apr 22 13:43:13 2004
@@ -76,8 +76,8 @@
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
|STWOTOX idnt 2,1 | Motorola 040 Floating Point Software Package
@@ -222,17 +222,17 @@ TWOOK1:
cmpil #0x400D80C0,%d0 | ...|X| > 16480?
bles TWOMAIN
bra EXPBORS
-
+
TWOMAIN:
|--USUAL CASE, 2^(-70) <= |X| <= 16480
fmovex %fp0,%fp1
fmuls #0x42800000,%fp1 | ...64 * X
-
+
fmovel %fp1,N(%a6) | ...N = ROUND-TO-INT(64 X)
movel %d2,-(%sp)
- lea EXPTBL,%a1 | ...LOAD ADDRESS OF TABLE OF 2^(J/64)
+ lea EXPTBL,%a1 | ...LOAD ADDRESS OF TABLE OF 2^(J/64)
fmovel N(%a6),%fp1 | ...N --> FLOATING FMT
movel N(%a6),%d0
movel %d0,%d2
@@ -244,7 +244,7 @@ TWOMAIN:
asrl #1,%d0 | ...D0 IS M
subl %d0,%d2 | ...d2 IS M', N = 64(M+M') + J
addil #0x3FFF,%d2
- movew %d2,ADJFACT(%a6) | ...ADJFACT IS 2^(M')
+ movew %d2,ADJFACT(%a6) | ...ADJFACT IS 2^(M')
movel (%sp)+,%d2
|--SUMMARY: a1 IS ADDRESS FOR THE LEADING PORTION OF 2^(J/64),
|--D0 IS M WHERE N = 64(M+M') + J. NOTE THAT |M| <= 16140 BY DESIGN.
@@ -258,13 +258,13 @@ TWOMAIN:
movew (%a1)+,FACT2(%a6)
clrw FACT2+2(%a6)
- fsubx %fp1,%fp0 | ...X - (1/64)*INT(64 X)
+ fsubx %fp1,%fp0 | ...X - (1/64)*INT(64 X)
movew (%a1)+,FACT2HI(%a6)
clrw FACT2HI+2(%a6)
clrl FACT2LOW(%a6)
addw %d0,FACT1(%a6)
-
+
fmulx LOG2,%fp0 | ...FP0 IS R
addw %d0,FACT2(%a6)
@@ -332,10 +332,10 @@ TENMAIN:
fmovex %fp0,%fp1
fmuld L2TEN64,%fp1 | ...X*64*LOG10/LOG2
-
+
fmovel %fp1,N(%a6) | ...N=INT(X*64*LOG10/LOG2)
movel %d2,-(%sp)
- lea EXPTBL,%a1 | ...LOAD ADDRESS OF TABLE OF 2^(J/64)
+ lea EXPTBL,%a1 | ...LOAD ADDRESS OF TABLE OF 2^(J/64)
fmovel N(%a6),%fp1 | ...N --> FLOATING FMT
movel N(%a6),%d0
movel %d0,%d2
@@ -347,7 +347,7 @@ TENMAIN:
asrl #1,%d0 | ...D0 IS M
subl %d0,%d2 | ...d2 IS M', N = 64(M+M') + J
addil #0x3FFF,%d2
- movew %d2,ADJFACT(%a6) | ...ADJFACT IS 2^(M')
+ movew %d2,ADJFACT(%a6) | ...ADJFACT IS 2^(M')
movel (%sp)+,%d2
|--SUMMARY: a1 IS ADDRESS FOR THE LEADING PORTION OF 2^(J/64),
@@ -375,7 +375,7 @@ TENMAIN:
clrl FACT2LOW(%a6)
fmulx LOG10,%fp0 | ...FP0 IS R
-
+
addw %d0,FACT1(%a6)
addw %d0,FACT2(%a6)
@@ -405,9 +405,9 @@ expr:
fmulx %fp1,%fp2 | ...FP2 IS S*(A1+S*(A3+S*A5))
faddx %fp3,%fp0 | ...FP0 IS R+R*S*(A2+S*A4)
-
+
faddx %fp2,%fp0 | ...FP0 IS EXP(R) - 1
-
+
|--FINAL RECONSTRUCTION PROCESS
|--EXP(X) = 2^M*2^(J/64) + 2^M*2^(J/64)*(EXP(R)-1) - (1 OR 0)
diff -puN arch/m68k/fpsp040/tbldo.S~m68k-superfluous-whitespace arch/m68k/fpsp040/tbldo.S
--- 25/arch/m68k/fpsp040/tbldo.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/tbldo.S Thu Apr 22 13:43:13 2004
@@ -6,19 +6,19 @@
| of indirection in do_func for monadic
| functions. Dyadic functions require two
| levels, and the tables are still contained
-| in do_func. The table is arranged for
+| in do_func. The table is arranged for
| index with a 10-bit index, with the first
| 7 bits the opcode, and the remaining 3
| the stag. For dyadic functions, all
| valid addresses are to the generic entry
-| point.
+| point.
|
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
|TBLDO idnt 2,1 | Motorola 040 Floating Point Software Package
@@ -57,7 +57,7 @@ tblpre:
.long smovcr |$00-7 fmovecr all
.long sint |$01-0 fint norm
- .long szero |$01-1 fint zero
+ .long szero |$01-1 fint zero
.long sinf |$01-2 fint inf
.long src_nan |$01-3 fint nan
.long sintd |$01-4 fint denorm inx
diff -puN arch/m68k/fpsp040/util.S~m68k-superfluous-whitespace arch/m68k/fpsp040/util.S
--- 25/arch/m68k/fpsp040/util.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/util.S Thu Apr 22 13:43:13 2004
@@ -4,20 +4,20 @@
| This file contains routines used by other programs.
|
| ovf_res: used by overflow to force the correct
-| result. ovf_r_k, ovf_r_x2, ovf_r_x3 are
+| result. ovf_r_k, ovf_r_x2, ovf_r_x3 are
| derivatives of this routine.
| get_fline: get user's opcode word
| g_dfmtou: returns the destination format.
| g_opcls: returns the opclass of the float instruction.
-| g_rndpr: returns the rounding precision.
+| g_rndpr: returns the rounding precision.
| reg_dest: write byte, word, or long data to Dn
|
|
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
|UTIL idnt 2,1 | Motorola 040 Floating Point Software Package
@@ -39,13 +39,13 @@
| are unnecessary as ovf_res always returns the sign separately from
| the exponent.
| ;+inf
-EXT_PINF: .long 0x7fff0000,0x00000000,0x00000000,0x00000000
+EXT_PINF: .long 0x7fff0000,0x00000000,0x00000000,0x00000000
| ;largest +ext
-EXT_PLRG: .long 0x7ffe0000,0xffffffff,0xffffffff,0x00000000
+EXT_PLRG: .long 0x7ffe0000,0xffffffff,0xffffffff,0x00000000
| ;largest magnitude +sgl in ext
-SGL_PLRG: .long 0x407e0000,0xffffff00,0x00000000,0x00000000
+SGL_PLRG: .long 0x407e0000,0xffffff00,0x00000000,0x00000000
| ;largest magnitude +dbl in ext
-DBL_PLRG: .long 0x43fe0000,0xffffffff,0xfffff800,0x00000000
+DBL_PLRG: .long 0x43fe0000,0xffffffff,0xfffff800,0x00000000
| ;largest -ext
tblovfl:
@@ -70,7 +70,7 @@ tblovfl:
|
| ovf_r_k --- overflow result calculation
|
-| This entry point is used by kernel_ex.
+| This entry point is used by kernel_ex.
|
| This forces the destination precision to be extended
|
@@ -79,7 +79,7 @@ tblovfl:
|
.global ovf_r_k
ovf_r_k:
- lea ETEMP(%a6),%a0 |a0 points to source operand
+ lea ETEMP(%a6),%a0 |a0 points to source operand
bclrb #sign_bit,ETEMP_EX(%a6)
sne ETEMP_SGN(%a6) |convert to internal IEEE format
@@ -112,10 +112,10 @@ ovf_e3_exc:
beql ovff_dbl |force precision is double
movew CMDREG3B(%a6),%d0 |get the command word again
andil #0x7f,%d0 |clear all except operation
- cmpil #0x33,%d0
+ cmpil #0x33,%d0
beql ovf_fsgl |fsglmul or fsgldiv
cmpil #0x30,%d0
- beql ovf_fsgl
+ beql ovf_fsgl
bra ovf_fpcr |instruction is none of the above
| ;use FPCR
ovf_e1_exc:
@@ -129,10 +129,10 @@ ovf_e1_exc:
andil #0x0000007f,%d0 |clear all except the op code
cmpil #0x00000027,%d0
beql ovf_fsgl |fsglmul
- cmpil #0x00000024,%d0
+ cmpil #0x00000024,%d0
beql ovf_fsgl |fsgldiv
bra ovf_fpcr |none of the above, use FPCR
-|
+|
|
| Inst is either fsgldiv or fsglmul. Force extended precision.
|
@@ -152,7 +152,7 @@ ovff_dbl:
ovf_fpcr:
bfextu FPCR_MODE(%a6){#0:#2},%d0 |set round precision
bra ovf_res
-
+
|
|
| ovf_r_x3 --- overflow result calculation
@@ -174,9 +174,9 @@ ovf_r_x3:
| ovf_res --- overflow result calculation
|
| Input:
-| a0 points to operand in internal extended format
+| a0 points to operand in internal extended format
| Output:
-| a0 points to result in internal extended format
+| a0 points to result in internal extended format
|
.global ovf_res
ovf_res:
@@ -192,7 +192,7 @@ ovf_res:
EXT_RN:
leal EXT_PINF,%a1 |answer is +/- infinity
bsetb #inf_bit,FPSR_CC(%a6)
- bra set_sign |now go set the sign
+ bra set_sign |now go set the sign
EXT_RZ:
leal EXT_PLRG,%a1 |answer is +/- large number
bra set_sign |now go set the sign
@@ -312,10 +312,10 @@ get_fline:
movel (%a7)+,%d0
rts
|
-| g_rndpr --- put rounding precision in d0{1:0}
-|
+| g_rndpr --- put rounding precision in d0{1:0}
+|
| valid return codes are:
-| 00 - extended
+| 00 - extended
| 01 - single
| 10 - double
|
@@ -350,7 +350,7 @@ g_rndpr:
| For move out instructions (opclass 011) the destination format
| is the same as the rounding precision. Pass results from g_dfmtou.
|
- bsr g_dfmtou
+ bsr g_dfmtou
rts
op_0x0:
btstb #E3,E_BYTE(%a6)
@@ -364,7 +364,7 @@ unf_e3_exc:
beql unff_dbl
movew CMDREG3B(%a6),%d0 |get the command word again
andil #0x7f,%d0 |clear all except operation
- cmpil #0x33,%d0
+ cmpil #0x33,%d0
beql unf_fsgl |fsglmul or fsgldiv
cmpil #0x30,%d0
beql unf_fsgl |fsgldiv or fsglmul
@@ -408,7 +408,7 @@ unff_dbl:
| Force extended
|
unf_fsgl:
- movel #0,%d0
+ movel #0,%d0
rts
|
| Get rounding precision set in FPCR{7:6}.
@@ -436,7 +436,7 @@ opc_1b:
| If E1, the format is from cmdreg1b{12:10}
| If E3, the format is extended.
|
-| Dest. Fmt.
+| Dest. Fmt.
| extended 010 -> 00
| single 001 -> 01
| double 101 -> 10
@@ -468,26 +468,26 @@ not_dbl:
| are unnecessary as unf_sub always returns the sign separately from
| the exponent.
| ;+zero
-EXT_PZRO: .long 0x00000000,0x00000000,0x00000000,0x00000000
+EXT_PZRO: .long 0x00000000,0x00000000,0x00000000,0x00000000
| ;+zero
-SGL_PZRO: .long 0x3f810000,0x00000000,0x00000000,0x00000000
+SGL_PZRO: .long 0x3f810000,0x00000000,0x00000000,0x00000000
| ;+zero
-DBL_PZRO: .long 0x3c010000,0x00000000,0x00000000,0x00000000
+DBL_PZRO: .long 0x3c010000,0x00000000,0x00000000,0x00000000
| ;smallest +ext denorm
-EXT_PSML: .long 0x00000000,0x00000000,0x00000001,0x00000000
+EXT_PSML: .long 0x00000000,0x00000000,0x00000001,0x00000000
| ;smallest +sgl denorm
-SGL_PSML: .long 0x3f810000,0x00000100,0x00000000,0x00000000
+SGL_PSML: .long 0x3f810000,0x00000100,0x00000000,0x00000000
| ;smallest +dbl denorm
-DBL_PSML: .long 0x3c010000,0x00000000,0x00000800,0x00000000
+DBL_PSML: .long 0x3c010000,0x00000000,0x00000800,0x00000000
|
| UNF_SUB --- underflow result calculation
|
| Input:
-| d0 contains round precision
+| d0 contains round precision
| a0 points to input operand in the internal extended format
|
| Output:
-| a0 points to correct internal extended precision result.
+| a0 points to correct internal extended precision result.
|
tblunf:
@@ -522,7 +522,7 @@ unf_sub:
uEXT_RN:
leal EXT_PZRO,%a1 |answer is +/- zero
bsetb #z_bit,FPSR_CC(%a6)
- bra uset_sign |now go set the sign
+ bra uset_sign |now go set the sign
uEXT_RZ:
leal EXT_PZRO,%a1 |answer is +/- zero
bsetb #z_bit,FPSR_CC(%a6)
@@ -629,7 +629,7 @@ end_unfr:
|
|
| Input:
-| L_SCR1: Data
+| L_SCR1: Data
| d1: data size and dest register number formatted as:
|
| 32 5 4 3 2 1 0
diff -puN arch/m68k/fpsp040/x_bsun.S~m68k-superfluous-whitespace arch/m68k/fpsp040/x_bsun.S
--- 25/arch/m68k/fpsp040/x_bsun.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/x_bsun.S Thu Apr 22 13:43:13 2004
@@ -13,8 +13,8 @@
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
X_BSUN: |idnt 2,1 | Motorola 040 Floating Point Software Package
diff -puN arch/m68k/fpsp040/x_fline.S~m68k-superfluous-whitespace arch/m68k/fpsp040/x_fline.S
--- 25/arch/m68k/fpsp040/x_fline.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/x_fline.S Thu Apr 22 13:43:13 2004
@@ -13,8 +13,8 @@
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
X_FLINE: |idnt 2,1 | Motorola 040 Floating Point Software Package
@@ -52,7 +52,7 @@ fpsp_fline:
leal L_SCR1(%a6),%a1 |use L_SCR1 as scratch
movel #4,%d0
addl #4,%a6 |to offset the sub.l #4,a7 above so that
-| ;a6 can point correctly to the stack frame
+| ;a6 can point correctly to the stack frame
| ;before branching to mem_read
bsrl mem_read
subl #4,%a6
@@ -62,7 +62,7 @@ fpsp_fline:
bne not_mvcr |exit if not
bfextu %d0{#16:#6},%d1
cmpib #0x17,%d1 |check if it is an FMOVECR encoding
- bne not_mvcr
+ bne not_mvcr
| ;if an FMOVECR instruction, fix stack
| ;and go to FPSP_UNIMP
fix_stack:
diff -puN arch/m68k/fpsp040/x_operr.S~m68k-superfluous-whitespace arch/m68k/fpsp040/x_operr.S
--- 25/arch/m68k/fpsp040/x_operr.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/x_operr.S Thu Apr 22 13:43:13 2004
@@ -13,8 +13,8 @@
| the dest format is integer (b, w, l) and the operr is caused by
| integer overflow, or the source op is inf, then the result stored is
| garbage.
-| There are three cases in which operr is incorrectly signaled on the
-| 040. This occurs for move_out of format b, w, or l for the largest
+| There are three cases in which operr is incorrectly signaled on the
+| 040. This occurs for move_out of format b, w, or l for the largest
| negative integer (-2^7 for b, -2^15 for w, -2^31 for l).
|
| On opclass = 011 fmove.(b,w,l) that causes a conversion
@@ -36,15 +36,15 @@
| Note 2: For trap enabled 040 does the following:
| If the inst is move_out, then same as Note 1.
| If the inst is not move_out, the dest is not modified.
-| The exceptional operand is not defined for integer overflow
+| The exceptional operand is not defined for integer overflow
| during a move_out.
|
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
X_OPERR: |idnt 2,1 | Motorola 040 Floating Point Software Package
@@ -77,7 +77,7 @@ fpsp_operr:
beqs operr_end
|
-| If the destination size is B,W,or L, the operr must be
+| If the destination size is B,W,or L, the operr must be
| handled here.
|
movel CMDREG1B(%a6),%d0
@@ -90,9 +90,9 @@ fpsp_operr:
beq operr_byte
|
-| The size is not B,W,or L, so the operr is handled by the
+| The size is not B,W,or L, so the operr is handled by the
| kernel handler. Set the operr bits and clean up, leaving
-| only the integer exception frame on the stack, and the
+| only the integer exception frame on the stack, and the
| fpu in the original exceptional state.
|
operr_end:
@@ -111,7 +111,7 @@ operr_long:
moveb STAG(%a6),%d0 |test stag for nan
andib #0xe0,%d0 |clr all but tag
cmpib #0x60,%d0 |check for nan
- beq operr_nan
+ beq operr_nan
cmpil #0x80000000,FPTEMP_LO(%a6) |test if ls lword is special
bnes chklerr |if not equal, check for incorrect operr
bsr check_upper |check if exp and ms mant are special
@@ -158,7 +158,7 @@ operr_word:
moveb STAG(%a6),%d0 |test stag for nan
andib #0xe0,%d0 |clr all but tag
cmpib #0x60,%d0 |check for nan
- beq operr_nan
+ beq operr_nan
cmpil #0xffff8000,FPTEMP_LO(%a6) |test if ls lword is special
bnes chkwerr |if not equal, check for incorrect operr
bsr check_upper |check if exp and ms mant are special
@@ -185,7 +185,7 @@ operr_byte:
moveb STAG(%a6),%d0 |test stag for nan
andib #0xe0,%d0 |clr all but tag
cmpib #0x60,%d0 |check for nan
- beqs operr_nan
+ beqs operr_nan
cmpil #0xffffff80,FPTEMP_LO(%a6) |test if ls lword is special
bnes chkberr |if not equal, check for incorrect operr
bsr check_upper |check if exp and ms mant are special
@@ -229,7 +229,7 @@ store_max:
bclrb #inex2_bit,FPSR_EXCEPT(%a6)
bclrb #ainex_bit,FPSR_AEXCEPT(%a6)
fmovel #0,%FPSR
-
+
tstw FPTEMP_EX(%a6) |check sign
blts load_neg
movel #0x7fffffff,%d0
@@ -280,7 +280,7 @@ dest_mem:
bsrl mem_write
rts
|
-| Check the exponent for $c000 and the upper 32 bits of the
+| Check the exponent for $c000 and the upper 32 bits of the
| mantissa for $ffffffff. If both are true, return d0 clr
| and store the lower n bits of the least lword of FPTEMP
| to d0 for write out. If not, it is a real operr, and set d0.
diff -puN arch/m68k/fpsp040/x_ovfl.S~m68k-superfluous-whitespace arch/m68k/fpsp040/x_ovfl.S
--- 25/arch/m68k/fpsp040/x_ovfl.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/x_ovfl.S Thu Apr 22 13:43:13 2004
@@ -8,7 +8,7 @@
| or when storing to memory, the contents of a floating-point
| data register are too large to be represented in the
| destination format.
-|
+|
| Trap disabled results
|
| If the instruction is move_out, then garbage is stored in the
@@ -35,8 +35,8 @@
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
X_OVFL: |idnt 2,1 | Motorola 040 Floating Point Software Package
@@ -73,7 +73,7 @@ fpsp_ovfl:
| if overflow traps not enabled check for inexact exception
|
btstb #ovfl_bit,FPCR_ENABLE(%a6)
- beqs ck_inex
+ beqs ck_inex
|
btstb #E3,E_BYTE(%a6)
beqs no_e3_1
@@ -120,7 +120,7 @@ no_e3_2:
frestore (%a7)+
unlk %a6
bral real_inex
-
+
ovfl_exit:
bclrb #E3,E_BYTE(%a6) |test and clear E3 bit
beqs e1_set
@@ -152,7 +152,7 @@ e1_set:
|
ovf_adj:
|
-| Have a0 point to the correct operand.
+| Have a0 point to the correct operand.
|
btstb #E3,E_BYTE(%a6) |test E3 bit
beqs ovf_e1
@@ -175,10 +175,10 @@ ovf_com:
| CCs are defined to be 'not affected' for the opclass3 instruction.
|
moveb FPSR_CC(%a6),L_SCR1(%a6)
- bsrl ovf_r_x3 |returns a0 pointing to result
+ bsrl ovf_r_x3 |returns a0 pointing to result
moveb L_SCR1(%a6),FPSR_CC(%a6)
bral store |stores to memory or register
-
+
not_opc011:
bsrl ovf_r_x2 |returns a0 pointing to result
bral store |stores to memory or register
diff -puN arch/m68k/fpsp040/x_snan.S~m68k-superfluous-whitespace arch/m68k/fpsp040/x_snan.S
--- 25/arch/m68k/fpsp040/x_snan.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/x_snan.S Thu Apr 22 13:43:13 2004
@@ -14,7 +14,7 @@
| of the mantissa are sent to the integer unit).
|
| For trap enabled the 040 does the following:
-| If the inst is move_out, then the results are the same as for trap
+| If the inst is move_out, then the results are the same as for trap
| disabled with the exception posted. If the instruction is not move_
| out, the dest. is not modified, and the exception is posted.
|
@@ -22,8 +22,8 @@
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
X_SNAN: |idnt 2,1 | Motorola 040 Floating Point Software Package
@@ -139,7 +139,7 @@ loop2:
bral fpsp_done
|
-| Move_out
+| Move_out
|
move_out:
movel EXC_EA(%a6),%a0 |get <ea> from exc frame
@@ -147,18 +147,18 @@ move_out:
bfextu CMDREG1B(%a6){#3:#3},%d0 |move rx field to d0{2:0}
cmpil #0,%d0 |check for long
beqs sto_long |branch if move_out long
-
+
cmpil #4,%d0 |check for word
beqs sto_word |branch if move_out word
-
+
cmpil #6,%d0 |check for byte
beqs sto_byte |branch if move_out byte
-
+
|
| Not byte, word or long
|
rts
-|
+|
| Get the 32 most significant bits of etemp mantissa
|
sto_long:
@@ -167,13 +167,13 @@ sto_long:
|
| Set signalling nan bit
|
- bsetl #30,%d1
+ bsetl #30,%d1
|
| Store to the users destination address
|
tstl %a0 |check if <ea> is 0
beqs wrt_dn |destination is a data register
-
+
movel %d1,-(%a7) |move the snan onto the stack
movel %a0,%a1 |load dest addr into a1
movel %a7,%a0 |load src addr of snan into a0
@@ -189,7 +189,7 @@ sto_word:
|
| Set signalling nan bit
|
- bsetl #30,%d1
+ bsetl #30,%d1
|
| Store to the users destination address
|
@@ -211,7 +211,7 @@ sto_byte:
|
| Set signalling nan bit
|
- bsetl #30,%d1
+ bsetl #30,%d1
|
| Store to the users destination address
|
@@ -253,7 +253,7 @@ wrt_byte:
| Check if it is a src nan or dst nan
|
not_out:
- movel DTAG(%a6),%d0
+ movel DTAG(%a6),%d0
bfextu %d0{#0:#3},%d0 |isolate dtag in lsbs
cmpib #3,%d0 |check for nan in destination
diff -puN arch/m68k/fpsp040/x_store.S~m68k-superfluous-whitespace arch/m68k/fpsp040/x_store.S
--- 25/arch/m68k/fpsp040/x_store.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/x_store.S Thu Apr 22 13:43:13 2004
@@ -11,8 +11,8 @@
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
X_STORE: |idnt 2,1 | Motorola 040 Floating Point Software Package
@@ -54,7 +54,7 @@ is_pos:
| in the USER_FPn variable on the stack because all exception
| handlers restore fp0-fp3 from there.
|
- cmpb #0x80,%d0
+ cmpb #0x80,%d0
bnes not_fp0
fmovemx %fp0-%fp0,USER_FP0(%a6)
rts
@@ -115,18 +115,18 @@ opc011:
| get rid of ext integer bit
| dbl_mant = ext_mant{62:12}
|
-| --------------- --------------- ---------------
+| --------------- --------------- ---------------
| extended -> |s| exp | |1| ms mant | | ls mant |
-| --------------- --------------- ---------------
-| 95 64 63 62 32 31 11 0
+| --------------- --------------- ---------------
+| 95 64 63 62 32 31 11 0
| | |
| | |
| | |
-| v v
-| --------------- ---------------
-| double -> |s|exp| mant | | mant |
-| --------------- ---------------
-| 63 51 32 31 0
+| v v
+| --------------- ---------------
+| double -> |s|exp| mant | | mant |
+| --------------- ---------------
+| 63 51 32 31 0
|
dest_dbl:
clrl %d0 |clear d0
@@ -137,7 +137,7 @@ dest_dbl:
addw #0x3ff,%d0 |add double precision bias
swap %d0 |d0 now in upper word
lsll #4,%d0 |d0 now in proper place for dbl prec exp
- tstb LOCAL_SGN(%a1)
+ tstb LOCAL_SGN(%a1)
beqs get_mant |if positive, go process mantissa
bsetl #31,%d0 |if negative, put in sign information
| ; before continuing
@@ -186,18 +186,18 @@ dbl_wrt:
| get rid of ext integer bit
| sgl_mant = ext_mant{62:12}
|
-| --------------- --------------- ---------------
+| --------------- --------------- ---------------
| extended -> |s| exp | |1| ms mant | | ls mant |
-| --------------- --------------- ---------------
-| 95 64 63 62 40 32 31 12 0
+| --------------- --------------- ---------------
+| 95 64 63 62 40 32 31 12 0
| | |
| | |
| | |
-| v v
-| ---------------
-| single -> |s|exp| mant |
-| ---------------
-| 31 22 0
+| v v
+| ---------------
+| single -> |s|exp| mant |
+| ---------------
+| 31 22 0
|
dest_sgl:
clrl %d0
@@ -208,7 +208,7 @@ dest_sgl:
addw #0x7f,%d0 |add single precision bias
swap %d0 |put exp in upper word of d0
lsll #7,%d0 |shift it into single exp bits
- tstb LOCAL_SGN(%a1)
+ tstb LOCAL_SGN(%a1)
beqs get_sman |if positive, continue
bsetl #31,%d0 |if negative, put in sign first
bras get_sman |get mantissa
@@ -240,7 +240,7 @@ sgl_Dn:
orl #0x10,%d1 |reg_dest wants size added to reg#
bral reg_dest |size is X, rts in reg_dest will
| ;return to caller of dest_sgl
-
+
dest_ext:
tstb LOCAL_SGN(%a1) |put back sign into exponent word
beqs dstx_cont
diff -puN arch/m68k/fpsp040/x_unfl.S~m68k-superfluous-whitespace arch/m68k/fpsp040/x_unfl.S
--- 25/arch/m68k/fpsp040/x_unfl.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/x_unfl.S Thu Apr 22 13:43:13 2004
@@ -4,25 +4,25 @@
| fpsp_unfl --- FPSP handler for underflow exception
|
| Trap disabled results
-| For 881/2 compatibility, sw must denormalize the intermediate
-| result, then store the result. Denormalization is accomplished
-| by taking the intermediate result (which is always normalized) and
-| shifting the mantissa right while incrementing the exponent until
-| it is equal to the denormalized exponent for the destination
-| format. After denormalization, the result is rounded to the
+| For 881/2 compatibility, sw must denormalize the intermediate
+| result, then store the result. Denormalization is accomplished
+| by taking the intermediate result (which is always normalized) and
+| shifting the mantissa right while incrementing the exponent until
+| it is equal to the denormalized exponent for the destination
+| format. After denormalization, the result is rounded to the
| destination format.
-|
+|
| Trap enabled results
-| All trap disabled code applies. In addition the exceptional
-| operand needs to made available to the user with a bias of $6000
+| All trap disabled code applies. In addition the exceptional
+| operand needs to made available to the user with a bias of $6000
| added to the exponent.
|
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
X_UNFL: |idnt 2,1 | Motorola 040 Floating Point Software Package
@@ -91,7 +91,7 @@ ck_inex:
|
| Inexact enabled and reported, and we must take an inexact exception
-|
+|
take_inex:
btstb #E3,E_BYTE(%a6)
beqs no_e3_2
@@ -145,7 +145,7 @@ unf_res:
| ;1=sgl, 2=dbl
| ;we need the RND_PREC in the
| ;upper word for round
- movew #0,-(%a7)
+ movew #0,-(%a7)
movew %d0,-(%a7) |copy RND_PREC to stack
|
|
@@ -199,7 +199,7 @@ unf_cont:
| must not corrupt a0 and d0.
|
|
-| Perform Round
+| Perform Round
| Input: a0 points to input operand
| d0{31:29} has guard, round, sticky
| d1{01:00} has rounding mode
@@ -222,7 +222,7 @@ opc011:
bsrl g_dfmtou
tstb %d0
beqs ext_opc011 |If extended, do not subtract
-| ;If destination format is sgl/dbl,
+| ;If destination format is sgl/dbl,
tstb LOCAL_HI(%a0) |If rounded result is normal,don't
| ;subtract
bmis ext_opc011
@@ -252,12 +252,12 @@ not_opc011:
bnes ck_sgn
bsetb #z_bit,FPSR_CC(%a6) |set condition codes if zero
ck_sgn:
- btstb #sign_bit,LOCAL_EX(%a0) |check the sign bit
+ btstb #sign_bit,LOCAL_EX(%a0) |check the sign bit
beqs unf_done
bsetb #neg_bit,FPSR_CC(%a6)
|
-| Finish.
+| Finish.
|
unf_done:
btstb #inex2_bit,FPSR_EXCEPT(%a6)
diff -puN arch/m68k/fpsp040/x_unimp.S~m68k-superfluous-whitespace arch/m68k/fpsp040/x_unimp.S
--- 25/arch/m68k/fpsp040/x_unimp.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/x_unimp.S Thu Apr 22 13:43:13 2004
@@ -1,14 +1,14 @@
|
| x_unimp.sa 3.3 7/1/91
|
-| fpsp_unimp --- FPSP handler for unimplemented instruction
+| fpsp_unimp --- FPSP handler for unimplemented instruction
| exception.
|
| Invoked when the user program encounters a floating-point
| op-code that hardware does not support. Trap vector# 11
| (See table 8-1 MC68030 User's Manual).
|
-|
+|
| Note: An fsave for an unimplemented inst. will create a short
| fsave stack.
|
@@ -22,8 +22,8 @@
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
X_UNIMP: |idnt 2,1 | Motorola 040 Floating Point Software Package
diff -puN arch/m68k/fpsp040/x_unsupp.S~m68k-superfluous-whitespace arch/m68k/fpsp040/x_unsupp.S
--- 25/arch/m68k/fpsp040/x_unsupp.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/fpsp040/x_unsupp.S Thu Apr 22 13:43:13 2004
@@ -3,18 +3,18 @@
|
| fpsp_unsupp --- FPSP handler for unsupported data type exception
|
-| Trap vector #55 (See table 8-1 Mc68030 User's manual).
+| Trap vector #55 (See table 8-1 Mc68030 User's manual).
| Invoked when the user program encounters a data format (packed) that
| hardware does not support or a data type (denormalized numbers or un-
| normalized numbers).
-| Normalizes denorms and unnorms, unpacks packed numbers then stores
-| them back into the machine to let the 040 finish the operation.
+| Normalizes denorms and unnorms, unpacks packed numbers then stores
+| them back into the machine to let the 040 finish the operation.
|
| Unsupp calls two routines:
-| 1. get_op - gets the operand(s)
-| 2. res_func - restore the function back into the 040 or
-| if fmove.p fpm,<ea> then pack source (fpm)
-| and store in users memory <ea>.
+| 1. get_op - gets the operand(s)
+| 2. res_func - restore the function back into the 040 or
+| if fmove.p fpm,<ea> then pack source (fpm)
+| and store in users memory <ea>.
|
| Input: Long fsave stack frame
|
@@ -23,8 +23,8 @@
| Copyright (C) Motorola, Inc. 1990
| All Rights Reserved
|
-| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
-| The copyright notice above does not evidence any
+| THIS IS UNPUBLISHED PROPRIETARY SOURCE CODE OF MOTOROLA
+| The copyright notice above does not evidence any
| actual or intended publication of such source code.
X_UNSUPP: |idnt 2,1 | Motorola 040 Floating Point Software Package
diff -puN arch/m68k/hp300/hp300map.map~m68k-superfluous-whitespace arch/m68k/hp300/hp300map.map
--- 25/arch/m68k/hp300/hp300map.map~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/hp300/hp300map.map Thu Apr 22 13:43:13 2004
@@ -3,29 +3,29 @@ keymaps 0-2,4-5,8,12
# Change the above line into
# keymaps 0-2,4-6,8,12
# in case you want the entries
-# altgr control keycode 83 = Boot
-# altgr control keycode 111 = Boot
+# altgr control keycode 83 = Boot
+# altgr control keycode 111 = Boot
# below.
#
# In fact AltGr is used very little, and one more keymap can
# be saved by mapping AltGr to Alt (and adapting a few entries):
# keycode 100 = Alt
#
-keycode 1 =
+keycode 1 =
keycode 2 = Alt
keycode 3 = Alt
keycode 4 = Shift
keycode 5 = Shift
keycode 6 = Control
-keycode 7 =
-keycode 8 =
-keycode 9 =
-keycode 10 =
-keycode 11 =
-keycode 12 =
-keycode 13 =
+keycode 7 =
+keycode 8 =
+keycode 9 =
+keycode 10 =
+keycode 11 =
+keycode 12 =
+keycode 13 =
keycode 14 =
-keycode 15 =
+keycode 15 =
keycode 16 =
keycode 17 =
keycode 18 =
@@ -34,12 +34,12 @@ keycode 20 =
keycode 21 =
keycode 22 =
keycode 23 =
-keycode 24 = b
-keycode 25 = v
+keycode 24 = b
+keycode 25 = v
keycode 26 = c
keycode 27 = x
keycode 28 = z
-keycode 29 =
+keycode 29 =
keycode 30 =
keycode 31 = Escape Delete
keycode 32 =
@@ -55,7 +55,7 @@ keycode 41 = g
keycode 42 = f
keycode 43 = d
keycode 44 = s
-keycode 45 = a
+keycode 45 = a
keycode 46 =
keycode 47 = Caps_Lock
keycode 48 = u
@@ -65,8 +65,8 @@ keycode 51 = r
keycode 52 = e
keycode 53 = w
keycode 54 = q
-keycode 55 = Tab Tab
- alt keycode 55 = Meta_Tab
+keycode 55 = Tab Tab
+ alt keycode 55 = Meta_Tab
keycode 56 = seven ampersand
keycode 57 = six asciicircum
keycode 58 = five percent
@@ -74,19 +74,19 @@ keycode 59 = four dollar
keycode 60 = three numbersign
keycode 61 = two at at
keycode 62 = one exclam exclam
-keycode 63 = grave asciitilde
- control keycode 63 = nul
- alt keycode 63 = Meta_grave
-keycode 64 =
-keycode 65 =
-keycode 66 =
-keycode 67 =
-keycode 68 =
-keycode 69 =
-keycode 70 =
-keycode 71 =
+keycode 63 = grave asciitilde
+ control keycode 63 = nul
+ alt keycode 63 = Meta_grave
+keycode 64 =
+keycode 65 =
+keycode 66 =
+keycode 67 =
+keycode 68 =
+keycode 69 =
+keycode 70 =
+keycode 71 =
keycode 72 =
-keycode 73 = F4
+keycode 73 = F4
control keycode 73 = Console_4
keycode 74 = F3
control keycode 74 = Console_3
@@ -107,8 +107,8 @@ keycode 83 = F7
keycode 84 = F8
control keycode 84 = Console_8
keycode 85 =
-keycode 86 =
-keycode 87 =
+keycode 86 =
+keycode 87 =
keycode 88 = eight asterisk asterisk
keycode 89 = nine parenleft bracketleft
keycode 90 = zero parenright bracketright
@@ -122,30 +122,30 @@ keycode 97 = o
keycode 98 = p
keycode 99 = bracketleft braceleft
keycode 100 = bracketright braceright
-keycode 101 = backslash bar
+keycode 101 = backslash bar
control keycode 101 = Control_backslash
- alt keycode 101 = Meta_backslash
-keycode 102 =
-keycode 103 =
+ alt keycode 101 = Meta_backslash
+keycode 102 =
+keycode 103 =
keycode 104 = j
keycode 105 = k
keycode 106 = l
keycode 107 = semicolon colon
- alt keycode 107 = Meta_semicolon
-keycode 108 = apostrophe quotedbl
- control keycode 108 = Control_g
- alt keycode 108 = Meta_apostrophe
+ alt keycode 107 = Meta_semicolon
+keycode 108 = apostrophe quotedbl
+ control keycode 108 = Control_g
+ alt keycode 108 = Meta_apostrophe
keycode 109 = Return
-keycode 110 =
-keycode 111 =
+keycode 110 =
+keycode 111 =
keycode 112 = m
keycode 113 = comma less
keycode 114 = period greater
keycode 115 = slash question
-keycode 116 =
-keycode 117 =
-keycode 118 =
-keycode 119 =
+keycode 116 =
+keycode 117 =
+keycode 118 =
+keycode 119 =
keycode 120 = n
keycode 121 = space space
keycode 122 =
diff -puN arch/m68k/hp300/ints.c~m68k-superfluous-whitespace arch/m68k/hp300/ints.c
--- 25/arch/m68k/hp300/ints.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/hp300/ints.c Thu Apr 22 13:43:13 2004
@@ -29,7 +29,7 @@
* Service routines are added via hp300_request_irq() and removed
* via hp300_free_irq(). The device driver should set IRQ_FLG_FAST
* if it needs to be serviced early (eg FIFOless UARTs); this will
- * cause it to be added at the front of the queue rather than
+ * cause it to be added at the front of the queue rather than
* the back.
* Currently IRQ_FLG_SLOW and flags=0 are treated identically; if
* we needed three levels of priority we could distinguish them
@@ -52,7 +52,7 @@ static irqreturn_t hp300_int_handler(int
t->handler(irq, t->dev_id, fp);
/* We could put in some accounting routines, checks for stray interrupts,
* etc, in here. Note that currently we can't tell whether or not
- * a handler handles the interrupt, though.
+ * a handler handles the interrupt, though.
*/
return IRQ_HANDLED;
}
@@ -80,7 +80,7 @@ int hp300_request_irq(unsigned int irq,
unsigned long flags, const char *devname, void *dev_id)
{
irq_node_t *t, *n = new_irq_node();
-
+
if (!n) /* oops, no free nodes */
return -ENOMEM;
@@ -117,7 +117,7 @@ void hp300_free_irq(unsigned int irq, vo
unsigned long flags;
spin_lock_irqsave(&irqlist_lock, flags);
-
+
t = hp300_irq_list[irq];
if (!t) /* no handlers at all for that IRQ */
{
@@ -125,7 +125,7 @@ void hp300_free_irq(unsigned int irq, vo
spin_unlock_irqrestore(&irqlist_lock, flags);
return;
}
-
+
if (t->dev_id == dev_id)
{ /* removing first handler on chain */
t->flags = IRQ_FLG_STD; /* we probably don't really need these */
@@ -136,9 +136,9 @@ void hp300_free_irq(unsigned int irq, vo
spin_unlock_irqrestore(&irqlist_lock, flags);
return;
}
-
+
/* OK, must be removing from middle of the chain */
-
+
for (t = hp300_irq_list[irq]; t->next && t->next->dev_id != dev_id; t = t->next)
/* do nothing */;
if (!t->next)
@@ -153,7 +153,7 @@ void hp300_free_irq(unsigned int irq, vo
t->next->devname = NULL;
t->next->handler = NULL;
t->next = t->next->next;
-
+
spin_unlock_irqrestore(&irqlist_lock, flags);
}
diff -puN arch/m68k/ifpsp060/CHANGES~m68k-superfluous-whitespace arch/m68k/ifpsp060/CHANGES
--- 25/arch/m68k/ifpsp060/CHANGES~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/ifpsp060/CHANGES Thu Apr 22 13:43:13 2004
@@ -5,10 +5,10 @@ M68060 Software Package
Production Release P1.00 -- October 10, 1994
M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved.
-
+
THE SOFTWARE is provided on an "AS IS" basis and without warranty.
To the maximum extent permitted by applicable law,
-MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
+MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
and any warranty against infringement with regard to the SOFTWARE
(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
@@ -31,7 +31,7 @@ CHANGES SINCE LAST RELEASE:
---------------------------
1) "movep" emulation where data was being read from memory
-was reading the intermediate bytes. Emulation now only
+was reading the intermediate bytes. Emulation now only
reads the required bytes.
2) "flogn", "flog2", and "flog10" of "1" was setting the
@@ -57,7 +57,7 @@ of the operation. This has been correcte
For example, if a user executed "fsin.x ADDR,fp0" where
ADDR should cause a "segmentation violation", the memory read
requested by the package should return a failing value
- to the package. Since the package currently ignores this
+ to the package. Since the package currently ignores this
return value, the user program will continue to the
next instruction, and the result created in fp0 will be
undefined.
@@ -76,16 +76,16 @@ of the operation. This has been correcte
as described in the MC68060 User's Manual.
For instruction read access errors, the info stacked is:
- SR = SR at time of exception
- PC = PC of instruction being emulated
+ SR = SR at time of exception
+ PC = PC of instruction being emulated
VOFF = $4008 (stack frame format type)
ADDRESS = PC of instruction being emulated
FSLW = FAULT STATUS LONGWORD
The valid FSLW bits are:
- bit 27 = 1 (misaligned bit)
- bit 24 = 1 (read)
- bit 23 = 0 (write)
+ bit 27 = 1 (misaligned bit)
+ bit 24 = 1 (read)
+ bit 23 = 0 (write)
bit 22:21 = 10 (SIZE = word)
bit 20:19 = 00 (TT)
bit 18:16 = x10 (TM; x = 1 for supervisor mode)
@@ -98,15 +98,15 @@ of the operation. This has been correcte
other bits.
For data read/write access errors, the info stacked is:
- SR = SR at time of exception
- PC = PC of instruction being emulated
+ SR = SR at time of exception
+ PC = PC of instruction being emulated
VOFF = $4008 (stack frame format type)
ADDRESS = Address of source or destination operand
FSLW = FAULT STATUS LONGWORD
The valid FSLW bits are:
- bit 27 = 0 (misaligned bit)
- bit 24 = x (read; 1 if read, 0 if write)
+ bit 27 = 0 (misaligned bit)
+ bit 24 = x (read; 1 if read, 0 if write)
bit 23 = x (write; 1 if write, 0 if read)
bit 22:21 = xx (SIZE; see MC68060 User's Manual)
bit 20:19 = 00 (TT)
diff -puN arch/m68k/ifpsp060/fplsp.doc~m68k-superfluous-whitespace arch/m68k/ifpsp060/fplsp.doc
--- 25/arch/m68k/ifpsp060/fplsp.doc~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/ifpsp060/fplsp.doc Thu Apr 22 13:43:13 2004
@@ -5,10 +5,10 @@ M68060 Software Package
Production Release P1.00 -- October 10, 1994
M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved.
-
+
THE SOFTWARE is provided on an "AS IS" basis and without warranty.
To the maximum extent permitted by applicable law,
-MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
+MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
and any warranty against infringement with regard to the SOFTWARE
(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
@@ -34,7 +34,7 @@ The file fplsp.sa contains the "Library
68060SP Floating-Point Software Package. The routines
included in this module can be used to emulate the
FP instructions not implemented in 68060 hardware. These
-instructions normally take exception vector #11
+instructions normally take exception vector #11
"FP Unimplemented Instruction".
By re-compiling a program that uses these instructions, and
diff -puN arch/m68k/ifpsp060/fpsp.doc~m68k-superfluous-whitespace arch/m68k/ifpsp060/fpsp.doc
--- 25/arch/m68k/ifpsp060/fpsp.doc~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/ifpsp060/fpsp.doc Thu Apr 22 13:43:13 2004
@@ -5,10 +5,10 @@ M68060 Software Package
Production Release P1.00 -- October 10, 1994
M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved.
-
+
THE SOFTWARE is provided on an "AS IS" basis and without warranty.
To the maximum extent permitted by applicable law,
-MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
+MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
and any warranty against infringement with regard to the SOFTWARE
(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
@@ -31,7 +31,7 @@ or trademarks of Motorola, Inc.
The file fpsp.sa contains the 68060 Floating-Point Software
Package. This package is essentially a set of exception handlers
-that can be integrated into an operating system.
+that can be integrated into an operating system.
These exception handlers emulate Unimplemented FP instructions,
instructions using unimplemented data types, and instructions
using unimplemented addressing modes. In addition, this package
@@ -62,14 +62,14 @@ Release file structure:
-----------------------
(top of module)
- -----------------
+ -----------------
| | - 128 byte-sized section
(1) | Call-Out | - 4 bytes per entry (user fills these in)
| | - example routines in fskeleton.s
-----------------
| | - 8 bytes per entry
(2) | Entry Point | - user does "bra" or "jmp" to this address
- | |
+ | |
-----------------
| | - code section
(3) ~ ~
@@ -79,14 +79,14 @@ Release file structure:
The first section of this module is the "Call-out" section. This section
is NOT INCLUDED in fpsp.sa (an example "Call-out" section is provided at
-the end of the file fskeleton.s). The purpose of this section is to allow
-the FPSP routines to reference external functions that must be provided
-by the host operating system. This section MUST be exactly 128 bytes in
+the end of the file fskeleton.s). The purpose of this section is to allow
+the FPSP routines to reference external functions that must be provided
+by the host operating system. This section MUST be exactly 128 bytes in
size. There are 32 fields, each 4 bytes in size. Each field corresponds
to a function required by the FPSP (these functions and their location are
listed in "68060FPSP call-outs" below). Each field entry should contain
the address of the corresponding function RELATIVE to the starting address
-of the "call-out" section. The "Call-out" section must sit adjacent to the
+of the "call-out" section. The "Call-out" section must sit adjacent to the
fpsp.sa image in memory.
The second section, the "Entry-point" section, is used by external routines
@@ -97,7 +97,7 @@ are listed in section "68060 FPSP entry
would simply execute a "bra" or "jmp" that jumped to the selected function
entry-point.
-For example, if the 68060 hardware took a "Line-F Emulator" exception
+For example, if the 68060 hardware took a "Line-F Emulator" exception
(vector #11), the operating system should execute something similar to:
bra _060FPSP_TOP+128+48
diff -puN arch/m68k/ifpsp060/fskeleton.S~m68k-superfluous-whitespace arch/m68k/ifpsp060/fskeleton.S
--- 25/arch/m68k/ifpsp060/fskeleton.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/ifpsp060/fskeleton.S Thu Apr 22 13:43:13 2004
@@ -5,10 +5,10 @@
|Production Release P1.00 -- October 10, 1994
|
|M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved.
-|
+|
|THE SOFTWARE is provided on an "AS IS" basis and without warranty.
|To the maximum extent permitted by applicable law,
-|MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
+|MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
|INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
|and any warranty against infringement with regard to the SOFTWARE
|(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
@@ -68,7 +68,7 @@ _060_fpsp_done:
| _060_real_ovfl():
|
| This is the exit point for the 060FPSP when an enabled overflow exception
-| is present. The routine below should point to the operating system handler
+| is present. The routine below should point to the operating system handler
| for enabled overflow conditions. The exception stack frame is an overflow
| stack frame. The FP state frame holds the EXCEPTIONAL OPERAND.
|
@@ -87,7 +87,7 @@ _060_real_ovfl:
| _060_real_unfl():
|
| This is the exit point for the 060FPSP when an enabled underflow exception
-| is present. The routine below should point to the operating system handler
+| is present. The routine below should point to the operating system handler
| for enabled underflow conditions. The exception stack frame is an underflow
| stack frame. The FP state frame holds the EXCEPTIONAL OPERAND.
|
@@ -105,7 +105,7 @@ _060_real_unfl:
| _060_real_operr():
|
| This is the exit point for the 060FPSP when an enabled operand error exception
-| is present. The routine below should point to the operating system handler
+| is present. The routine below should point to the operating system handler
| for enabled operand error exceptions. The exception stack frame is an operand error
| stack frame. The FP state frame holds the source operand of the faulting
| instruction.
@@ -124,7 +124,7 @@ _060_real_operr:
| _060_real_snan():
|
| This is the exit point for the 060FPSP when an enabled signalling NaN exception
-| is present. The routine below should point to the operating system handler
+| is present. The routine below should point to the operating system handler
| for enabled signalling NaN exceptions. The exception stack frame is a signalling NaN
| stack frame. The FP state frame holds the source operand of the faulting
| instruction.
@@ -143,7 +143,7 @@ _060_real_snan:
| _060_real_dz():
|
| This is the exit point for the 060FPSP when an enabled divide-by-zero exception
-| is present. The routine below should point to the operating system handler
+| is present. The routine below should point to the operating system handler
| for enabled divide-by-zero exceptions. The exception stack frame is a divide-by-zero
| stack frame. The FP state frame holds the source operand of the faulting
| instruction.
@@ -162,7 +162,7 @@ _060_real_dz:
| _060_real_inex():
|
| This is the exit point for the 060FPSP when an enabled inexact exception
-| is present. The routine below should point to the operating system handler
+| is present. The routine below should point to the operating system handler
| for enabled inexact exceptions. The exception stack frame is an inexact
| stack frame. The FP state frame holds the source operand of the faulting
| instruction.
@@ -181,12 +181,12 @@ _060_real_inex:
| _060_real_bsun():
|
| This is the exit point for the 060FPSP when an enabled bsun exception
-| is present. The routine below should point to the operating system handler
+| is present. The routine below should point to the operating system handler
| for enabled bsun exceptions. The exception stack frame is a bsun
| stack frame.
|
| The sample routine below clears the exception status bit, clears the NaN
-| bit in the FPSR, and does an "rte". The instruction that caused the
+| bit in the FPSR, and does an "rte". The instruction that caused the
| bsun will now be re-executed but with the NaN FPSR bit cleared.
|
.global _060_real_bsun
@@ -202,13 +202,13 @@ _060_real_bsun:
|
| _060_real_fline():
|
-| This is the exit point for the 060FPSP when an F-Line Illegal exception is
+| This is the exit point for the 060FPSP when an F-Line Illegal exception is
| encountered. Three different types of exceptions can enter the F-Line exception
| vector number 11: FP Unimplemented Instructions, FP implemented instructions when
| the FPU is disabled, and F-Line Illegal instructions. The 060FPSP module
| _fpsp_fline() distinguishes between the three and acts appropriately. F-Line
| Illegals branch here.
-|
+|
.global _060_real_fline
_060_real_fline:
bral trap | jump to trap handler
@@ -216,7 +216,7 @@ _060_real_fline:
|
| _060_real_fpu_disabled():
|
-| This is the exit point for the 060FPSP when an FPU disabled exception is
+| This is the exit point for the 060FPSP when an FPU disabled exception is
| encountered. Three different types of exceptions can enter the F-Line exception
| vector number 11: FP Unimplemented Instructions, FP implemented instructions when
| the FPU is disabled, and F-Line Illegal instructions. The 060FPSP module
diff -puN arch/m68k/ifpsp060/ilsp.doc~m68k-superfluous-whitespace arch/m68k/ifpsp060/ilsp.doc
--- 25/arch/m68k/ifpsp060/ilsp.doc~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/ifpsp060/ilsp.doc Thu Apr 22 13:43:13 2004
@@ -5,10 +5,10 @@ M68060 Software Package
Production Release P1.00 -- October 10, 1994
M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved.
-
+
THE SOFTWARE is provided on an "AS IS" basis and without warranty.
To the maximum extent permitted by applicable law,
-MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
+MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
and any warranty against infringement with regard to the SOFTWARE
(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
@@ -32,11 +32,11 @@ or trademarks of Motorola, Inc.
The file ilsp.s contains the "Library version" of the
68060 Integer Software Package. Routines included in this
module can be used to emulate 64-bit divide and multiply,
-and the "cmp2" instruction. These instructions are not
-implemented in hardware on the 68060 and normally take
+and the "cmp2" instruction. These instructions are not
+implemented in hardware on the 68060 and normally take
exception vector #61 "Unimplemented Integer Instruction".
-By re-compiling a program that uses these instructions, and
+By re-compiling a program that uses these instructions, and
making subroutine calls in place of the unimplemented
instructions, a program can avoid the overhead associated with
taking the exception.
@@ -63,7 +63,7 @@ documentation purposes.
Release file structure:
-----------------------
-The file ilsp.sa contains an "Entry-Point" section and a
+The file ilsp.sa contains an "Entry-Point" section and a
code section. The ILSP has no "Call-Out" section. The first section
is the "Entry-Point" section. In order to access a function in the
package, a program must "bsr" or "jsr" to the location listed
@@ -77,7 +77,7 @@ re-compiled with every new 68060ILSP rel
For example, to use a 64-bit multiply instruction,
do a "bsr" or "jsr" to the entry point defined by
-the 060ILSP entry table. A compiler generated code sequence
+the 060ILSP entry table. A compiler generated code sequence
for unsigned multiply could look like:
# mulu.l <ea>,Dh:Dl
@@ -107,7 +107,7 @@ For a divide:
mov.l (%sp)+,%d1 # load remainder
mov.l (%sp)+,%d0 # load quotient
-The library routines also return the correct condition code
+The library routines also return the correct condition code
register value. If this is important, then the caller of the library
routine must make sure that the value isn't lost while popping
other items off of the stack.
diff -puN arch/m68k/ifpsp060/iskeleton.S~m68k-superfluous-whitespace arch/m68k/ifpsp060/iskeleton.S
--- 25/arch/m68k/ifpsp060/iskeleton.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/ifpsp060/iskeleton.S Thu Apr 22 13:43:13 2004
@@ -5,10 +5,10 @@
|Production Release P1.00 -- October 10, 1994
|
|M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved.
-|
+|
|THE SOFTWARE is provided on an "AS IS" basis and without warranty.
|To the maximum extent permitted by applicable law,
-|MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
+|MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
|INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
|and any warranty against infringement with regard to the SOFTWARE
|(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
@@ -40,7 +40,7 @@
|################################
-| (1) EXAMPLE CALL-OUTS #
+| (1) EXAMPLE CALL-OUTS #
| #
| _060_isp_done() #
| _060_real_chk() #
@@ -56,7 +56,7 @@
| _060_isp_done():
|
| This is and example main exit point for the Unimplemented Integer
-| Instruction exception handler. For a normal exit, the
+| Instruction exception handler. For a normal exit, the
| _isp_unimp() branches to here so that the operating system
| can do any clean-up desired. The stack frame is the
| Unimplemented Integer Instruction stack frame with
@@ -118,9 +118,9 @@ real_chk_end:
|
| _060_real_divbyzero:
|
-| This is an alternate exit point for the Unimplemented Integer
+| This is an alternate exit point for the Unimplemented Integer
| Instruction exception handler isp_unimp(). If the instruction is a 64-bit
-| integer divide where the source operand is a zero, then the _isp_unimp()
+| integer divide where the source operand is a zero, then the _isp_unimp()
| creates a Divide-by-zero exception stack frame from the Unimplemented
| Integer Instruction stack frame and branches to this routine.
|
@@ -128,7 +128,7 @@ real_chk_end:
| no action associated with the "chk" exception. If tracing is enabled,
| then it create a Trace exception stack frame from the "chk" exception
| stack frame and branches to the _real_trace() entry point.
-|
+|
| Linux/68k: commented out test for tracing
.global _060_real_divbyzero
@@ -185,7 +185,7 @@ _060_real_cas2:
| Entry point for the operating system`s routine to "lock" a page
| from being paged out. This routine is needed by the cas/cas2
| algorithms so that no page faults occur within the "core" code
-| region. Note: the routine must lock two pages if the operand
+| region. Note: the routine must lock two pages if the operand
| spans two pages.
| NOTE: THE ROUTINE SHOULD RETURN AN FSLW VALUE IN D0 ON FAILURE
| SO THAT THE 060SP CAN CREATE A PROPER ACCESS ERROR FRAME.
@@ -212,7 +212,7 @@ _060_real_lock_page:
| Note: the routine must unlock two pages if the operand spans
| two pages.
| Arguments:
-| a0 = operand address
+| a0 = operand address
| d0 = `xxxxxxff -> supervisor; `xxxxxx00 -> user
| d1 = `xxxxxxff -> longword; `xxxxxx00 -> word
|
diff -puN arch/m68k/ifpsp060/isp.doc~m68k-superfluous-whitespace arch/m68k/ifpsp060/isp.doc
--- 25/arch/m68k/ifpsp060/isp.doc~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/ifpsp060/isp.doc Thu Apr 22 13:43:13 2004
@@ -5,10 +5,10 @@ M68060 Software Package
Production Release P1.00 -- October 10, 1994
M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved.
-
+
THE SOFTWARE is provided on an "AS IS" basis and without warranty.
To the maximum extent permitted by applicable law,
-MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
+MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
and any warranty against infringement with regard to the SOFTWARE
(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
@@ -77,7 +77,7 @@ Release file structure:
-----------------
| | - 8 bytes per entry
(2) | Entry Point | - user does a "bra" or "jmp" to this address
- | |
+ | |
-----------------
| | - code section
(3) ~ ~
@@ -87,14 +87,14 @@ Release file structure:
The first section of this module is the "Call-out" section. This section
is NOT INCLUDED in isp.sa (an example "Call-out" section is provided at
-the end of the file iskeleton.s). The purpose of this section is to allow
-the ISP routines to reference external functions that must be provided
-by the host operating system. This section MUST be exactly 128 bytes in
+the end of the file iskeleton.s). The purpose of this section is to allow
+the ISP routines to reference external functions that must be provided
+by the host operating system. This section MUST be exactly 128 bytes in
size. There are 32 fields, each 4 bytes in size. Each field corresponds
to a function required by the ISP (these functions and their location are
listed in "68060ISP call-outs" below). Each field entry should contain
the address of the corresponding function RELATIVE to the starting address
-of the "call-out" section. The "Call-out" section must sit adjacent to the
+of the "call-out" section. The "Call-out" section must sit adjacent to the
isp.sa image in memory.
The second section, the "Entry-point" section, is used by external routines
@@ -112,7 +112,7 @@ similar to:
bra _060ISP_TOP+128+0
(_060ISP_TOP is the starting address of the "Call-out" section; the "Call-out"
-section is 128 bytes long; and the Unimplemented Integer ISP handler entry
+section is 128 bytes long; and the Unimplemented Integer ISP handler entry
point is located 0 bytes from the top of the "Entry-point" section.)
The third section is the code section. After entering through an "Entry-point",
@@ -177,7 +177,7 @@ address) take the Unimplemented Integer
_060_isp_unimp() entry point of the ISP.
After the 060ISP decodes the instruction type and fetches the appropriate
-data registers, and BEFORE the actual emulated transfers occur, the
+data registers, and BEFORE the actual emulated transfers occur, the
package calls either the "Call-out" _060_real_cas() or _060_real_cas2().
If the emulation code provided by the 060ISP is sufficient for the
host system (see isp.s source code), then these "Call-out"s should be
diff -puN arch/m68k/ifpsp060/MISC~m68k-superfluous-whitespace arch/m68k/ifpsp060/MISC
--- 25/arch/m68k/ifpsp060/MISC~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/ifpsp060/MISC Thu Apr 22 13:43:13 2004
@@ -5,10 +5,10 @@ M68060 Software Package
Production Release P1.00 -- October 10, 1994
M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved.
-
+
THE SOFTWARE is provided on an "AS IS" basis and without warranty.
To the maximum extent permitted by applicable law,
-MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
+MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
and any warranty against infringement with regard to the SOFTWARE
(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
@@ -176,7 +176,7 @@ icalc_ea.s : 2.11
imovep.s : 2.8
ichk2cmp2.s : 2.6
idiv64.s : 2.10
-imul64.s :
+imul64.s :
icas2.s : 2.11
icas.s : 2.12
icas2_core.s: 2.6
diff -puN arch/m68k/ifpsp060/os.S~m68k-superfluous-whitespace arch/m68k/ifpsp060/os.S
--- 25/arch/m68k/ifpsp060/os.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/ifpsp060/os.S Thu Apr 22 13:43:13 2004
@@ -5,10 +5,10 @@
|Production Release P1.00 -- October 10, 1994
|
|M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved.
-|
+|
|THE SOFTWARE is provided on an "AS IS" basis and without warranty.
|To the maximum extent permitted by applicable law,
-|MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
+|MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
|INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
|and any warranty against infringement with regard to the SOFTWARE
|(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
@@ -35,8 +35,8 @@
#include <linux/linkage.h>
|################################
-| EXAMPLE CALL-OUTS #
-| #
+| EXAMPLE CALL-OUTS #
+| #
| _060_dmem_write() #
| _060_dmem_read() #
| _060_imem_read() #
@@ -53,12 +53,12 @@
| _060_real_access() #
|################################
-|
+|
| Each IO routine checks to see if the memory write/read is to/from user
| or supervisor application space. The examples below use simple "move"
| instructions for supervisor mode applications and call _copyin()/_copyout()
| for user mode applications.
-| When installing the 060SP, the _copyin()/_copyout() equivalents for a
+| When installing the 060SP, the _copyin()/_copyout() equivalents for a
| given operating system should be substituted.
|
| The addresses within the 060SP are guaranteed to be on the stack.
@@ -76,10 +76,10 @@
| Writes to data memory while in supervisor mode.
|
| INPUTS:
-| a0 - supervisor source address
+| a0 - supervisor source address
| a1 - user destination address
-| d0 - number of bytes to write
-| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode
+| d0 - number of bytes to write
+| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode
| OUTPUTS:
| d1 - 0 = success, !0 = failure
|
@@ -110,11 +110,11 @@ copyoutae:
| a0 - user source address
| a1 - supervisor destination address
| d0 - number of bytes to read
-| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode
+| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode
| OUTPUTS:
| d1 - 0 = success, !0 = failure
|
- .global _060_imem_read
+ .global _060_imem_read
.global _060_dmem_read
_060_imem_read:
_060_dmem_read:
@@ -136,17 +136,17 @@ copyinae:
|
| _060_dmem_read_byte():
-|
+|
| Read a data byte from user memory.
|
| INPUTS:
| a0 - user source address
-| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode
+| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode
| OUTPUTS:
| d0 - data byte in d0
| d1 - 0 = success, !0 = failure
|
- .global _060_dmem_read_byte
+ .global _060_dmem_read_byte
_060_dmem_read_byte:
clr.l %d0 | clear whole longword
clr.l %d1 | assume success
@@ -159,29 +159,29 @@ dmrbs: move.b (%a0),%d0 | fetch super
|
| _060_dmem_read_word():
-|
+|
| Read a data word from user memory.
|
| INPUTS:
| a0 - user source address
-| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode
+| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode
| OUTPUTS:
| d0 - data word in d0
| d1 - 0 = success, !0 = failure
|
| _060_imem_read_word():
-|
+|
| Read an instruction word from user memory.
|
| INPUTS:
| a0 - user source address
-| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode
+| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode
| OUTPUTS:
| d0 - instruction word in d0
| d1 - 0 = success, !0 = failure
|
- .global _060_dmem_read_word
- .global _060_imem_read_word
+ .global _060_dmem_read_word
+ .global _060_imem_read_word
_060_dmem_read_word:
_060_imem_read_word:
clr.l %d1 | assume success
@@ -195,29 +195,29 @@ dmrws: move.w (%a0), %d0 | fetch super
|
| _060_dmem_read_long():
-|
+|
|
| INPUTS:
| a0 - user source address
-| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode
+| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode
| OUTPUTS:
| d0 - data longword in d0
| d1 - 0 = success, !0 = failure
|
| _060_imem_read_long():
-|
+|
| Read an instruction longword from user memory.
|
| INPUTS:
| a0 - user source address
-| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode
+| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode
| OUTPUTS:
| d0 - instruction longword in d0
| d1 - 0 = success, !0 = failure
|
- .global _060_dmem_read_long
- .global _060_imem_read_long
+ .global _060_dmem_read_long
+ .global _060_imem_read_long
_060_dmem_read_long:
_060_imem_read_long:
clr.l %d1 | assume success
@@ -235,12 +235,12 @@ dmrls: move.l (%a0),%d0 | fetch super
|
| INPUTS:
| a0 - user destination address
-| d0 - data byte in d0
-| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode
+| d0 - data byte in d0
+| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode
| OUTPUTS:
| d1 - 0 = success, !0 = failure
|
- .global _060_dmem_write_byte
+ .global _060_dmem_write_byte
_060_dmem_write_byte:
clr.l %d1 | assume success
btst #0x5,0x4(%a6) | check for supervisor state
@@ -257,12 +257,12 @@ dmwbs: move.b %d0,(%a0) | store super
|
| INPUTS:
| a0 - user destination address
-| d0 - data word in d0
-| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode
+| d0 - data word in d0
+| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode
| OUTPUTS:
| d1 - 0 = success, !0 = failure
|
- .global _060_dmem_write_word
+ .global _060_dmem_write_word
_060_dmem_write_word:
clr.l %d1 | assume success
btst #0x5,0x4(%a6) | check for supervisor state
@@ -281,12 +281,12 @@ dmwwr: clr.l %d1 | return success
|
| INPUTS:
| a0 - user destination address
-| d0 - data longword in d0
-| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode
+| d0 - data longword in d0
+| 0x4(%a6),bit5 - 1 = supervisor mode, 0 = user mode
| OUTPUTS:
| d1 - 0 = success, !0 = failure
|
- .global _060_dmem_write_long
+ .global _060_dmem_write_long
_060_dmem_write_long:
clr.l %d1 | assume success
btst #0x5,0x4(%a6) | check for supervisor state
@@ -313,7 +313,7 @@ dmwls: move.l %d0,(%a0) | store super
|
| int _copyout(supervisor_addr, user_addr, nbytes)
|
- .global _copyout
+ .global _copyout
_copyout:
move.l 4(%sp),%a0 | source
move.l 8(%sp),%a1 | destination
@@ -330,14 +330,14 @@ copyoutae:
|
| int _copyin(user_addr, supervisor_addr, nbytes)
|
- .global _copyin
+ .global _copyin
_copyin:
move.l 4(%sp),%a0 | source
move.l 8(%sp),%a1 | destination
move.l 12(%sp),%d0 | count
subq.l #1,%d0
morein:
-copyinae:
+copyinae:
movs.b (%a0)+,%d1 | fetch user byte
move.b %d1,(%a1)+ | write supervisor byte
dbra %d0,morein | are we through yet?
@@ -378,7 +378,7 @@ _060_real_access:
-| Execption handling for movs access to illegal memory
+| Execption handling for movs access to illegal memory
.section .fixup,#alloc,#execinstr
.even
1: moveq #-1,%d1
diff -puN arch/m68k/ifpsp060/README~m68k-superfluous-whitespace arch/m68k/ifpsp060/README
--- 25/arch/m68k/ifpsp060/README~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/ifpsp060/README Thu Apr 22 13:43:13 2004
@@ -5,10 +5,10 @@ M68060 Software Package
Production Release P1.00 -- October 10, 1994
M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved.
-
+
THE SOFTWARE is provided on an "AS IS" basis and without warranty.
To the maximum extent permitted by applicable law,
-MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
+MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
and any warranty against infringement with regard to the SOFTWARE
(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
diff -puN arch/m68k/ifpsp060/src/fplsp.S~m68k-superfluous-whitespace arch/m68k/ifpsp060/src/fplsp.S
--- 25/arch/m68k/ifpsp060/src/fplsp.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/ifpsp060/src/fplsp.S Thu Apr 22 13:43:13 2004
@@ -5,10 +5,10 @@ M68060 Software Package
Production Release P1.00 -- October 10, 1994
M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved.
-
+
THE SOFTWARE is provided on an "AS IS" basis and without warranty.
To the maximum extent permitted by applicable law,
-MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
+MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
and any warranty against infringement with regard to the SOFTWARE
(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
@@ -304,33 +304,33 @@ set EXC_D2, EXC_DREGS+(2*4)
set EXC_D1, EXC_DREGS+(1*4)
set EXC_D0, EXC_DREGS+(0*4)
-set EXC_FP0, EXC_FPREGS+(0*12) # offset of saved fp0
-set EXC_FP1, EXC_FPREGS+(1*12) # offset of saved fp1
-set EXC_FP2, EXC_FPREGS+(2*12) # offset of saved fp2 (not used)
+set EXC_FP0, EXC_FPREGS+(0*12) # offset of saved fp0
+set EXC_FP1, EXC_FPREGS+(1*12) # offset of saved fp1
+set EXC_FP2, EXC_FPREGS+(2*12) # offset of saved fp2 (not used)
-set FP_SCR1, LV+80 # fp scratch 1
-set FP_SCR1_EX, FP_SCR1+0
+set FP_SCR1, LV+80 # fp scratch 1
+set FP_SCR1_EX, FP_SCR1+0
set FP_SCR1_SGN, FP_SCR1+2
-set FP_SCR1_HI, FP_SCR1+4
-set FP_SCR1_LO, FP_SCR1+8
+set FP_SCR1_HI, FP_SCR1+4
+set FP_SCR1_LO, FP_SCR1+8
-set FP_SCR0, LV+68 # fp scratch 0
-set FP_SCR0_EX, FP_SCR0+0
+set FP_SCR0, LV+68 # fp scratch 0
+set FP_SCR0_EX, FP_SCR0+0
set FP_SCR0_SGN, FP_SCR0+2
-set FP_SCR0_HI, FP_SCR0+4
-set FP_SCR0_LO, FP_SCR0+8
+set FP_SCR0_HI, FP_SCR0+4
+set FP_SCR0_LO, FP_SCR0+8
-set FP_DST, LV+56 # fp destination operand
-set FP_DST_EX, FP_DST+0
+set FP_DST, LV+56 # fp destination operand
+set FP_DST_EX, FP_DST+0
set FP_DST_SGN, FP_DST+2
-set FP_DST_HI, FP_DST+4
-set FP_DST_LO, FP_DST+8
+set FP_DST_HI, FP_DST+4
+set FP_DST_LO, FP_DST+8
-set FP_SRC, LV+44 # fp source operand
-set FP_SRC_EX, FP_SRC+0
+set FP_SRC, LV+44 # fp source operand
+set FP_SRC_EX, FP_SRC+0
set FP_SRC_SGN, FP_SRC+2
-set FP_SRC_HI, FP_SRC+4
-set FP_SRC_LO, FP_SRC+8
+set FP_SRC_HI, FP_SRC+4
+set FP_SRC_LO, FP_SRC+8
set USER_FPIAR, LV+40 # FP instr address register
@@ -354,7 +354,7 @@ set EXC_TEMP2, LV+24 # temporary spac
set EXC_TEMP, LV+16 # temporary space
set DTAG, LV+15 # destination operand type
-set STAG, LV+14 # source operand type
+set STAG, LV+14 # source operand type
set SPCOND_FLG, LV+10 # flag: special case (see below)
@@ -369,17 +369,17 @@ set EXC_OPWORD, LV+0 # saved operatio
# Helpful macros
set FTEMP, 0 # offsets within an
-set FTEMP_EX, 0 # extended precision
+set FTEMP_EX, 0 # extended precision
set FTEMP_SGN, 2 # value saved in memory.
-set FTEMP_HI, 4
-set FTEMP_LO, 8
+set FTEMP_HI, 4
+set FTEMP_LO, 8
set FTEMP_GRS, 12
set LOCAL, 0 # offsets within an
-set LOCAL_EX, 0 # extended precision
+set LOCAL_EX, 0 # extended precision
set LOCAL_SGN, 2 # value saved in memory.
-set LOCAL_HI, 4
-set LOCAL_LO, 8
+set LOCAL_HI, 4
+set LOCAL_LO, 8
set LOCAL_GRS, 12
set DST, 0 # offsets within an
@@ -469,17 +469,17 @@ set ainex_mask, 0x00000008 # accrued i
######################################
set dzinf_mask, inf_mask+dz_mask+adz_mask
set opnan_mask, nan_mask+operr_mask+aiop_mask
-set nzi_mask, 0x01ffffff #clears N, Z, and I
+set nzi_mask, 0x01ffffff #clears N, Z, and I
set unfinx_mask, unfl_mask+inex2_mask+aunfl_mask+ainex_mask
set unf2inx_mask, unfl_mask+inex2_mask+ainex_mask
set ovfinx_mask, ovfl_mask+inex2_mask+aovfl_mask+ainex_mask
set inx1a_mask, inex1_mask+ainex_mask
set inx2a_mask, inex2_mask+ainex_mask
-set snaniop_mask, nan_mask+snan_mask+aiop_mask
+set snaniop_mask, nan_mask+snan_mask+aiop_mask
set snaniop2_mask, snan_mask+aiop_mask
set naniop_mask, nan_mask+aiop_mask
set neginf_mask, neg_mask+inf_mask
-set infaiop_mask, inf_mask+aiop_mask
+set infaiop_mask, inf_mask+aiop_mask
set negz_mask, neg_mask+z_mask
set opaop_mask, operr_mask+aiop_mask
set unfl_inx_mask, unfl_mask+aunfl_mask+ainex_mask
@@ -508,8 +508,8 @@ set rp_mode, 0x3 # round-to-plus-infi
set mantissalen, 64 # length of mantissa in bits
set BYTE, 1 # len(byte) == 1 byte
-set WORD, 2 # len(word) == 2 bytes
-set LONG, 4 # len(longword) == 2 bytes
+set WORD, 2 # len(word) == 2 bytes
+set LONG, 4 # len(longword) == 2 bytes
set BSUN_VEC, 0xc0 # bsun vector offset
set INEX_VEC, 0xc4 # inexact vector offset
@@ -4903,7 +4903,7 @@ _L23_6x:
# d0 = round precision,mode #
# #
# OUTPUT ************************************************************** #
-# fp0 = sin(X) or cos(X) #
+# fp0 = sin(X) or cos(X) #
# #
# For ssincos(X): #
# fp0 = sin(X) #
@@ -4911,7 +4911,7 @@ _L23_6x:
# #
# ACCURACY and MONOTONICITY ******************************************* #
# The returned result is within 1 ulp in 64 significant bit, i.e. #
-# within 0.5001 ulp to 53 bits if the result is subsequently #
+# within 0.5001 ulp to 53 bits if the result is subsequently #
# rounded to double precision. The result is provably monotonic #
# in double precision. #
# #
@@ -4928,8 +4928,8 @@ _L23_6x:
# #
# 4. If k is even, go to 6. #
# #
-# 5. (k is odd) Set j := (k-1)/2, sgn := (-1)**j. #
-# Return sgn*cos(r) where cos(r) is approximated by an #
+# 5. (k is odd) Set j := (k-1)/2, sgn := (-1)**j. #
+# Return sgn*cos(r) where cos(r) is approximated by an #
# even polynomial in r, 1 + r*r*(B1+s*(B2+ ... + s*B8)), #
# s = r*r. #
# Exit. #
@@ -4941,10 +4941,10 @@ _L23_6x:
# #
# 7. If |X| > 1, go to 9. #
# #
-# 8. (|X|<2**(-40)) If SIN is invoked, return X; #
+# 8. (|X|<2**(-40)) If SIN is invoked, return X; #
# otherwise return 1. #
# #
-# 9. Overwrite X by X := X rem 2Pi. Now that |X| <= Pi, #
+# 9. Overwrite X by X := X rem 2Pi. Now that |X| <= Pi, #
# go back to 3. #
# #
# SINCOS: #
@@ -4959,19 +4959,19 @@ _L23_6x:
# j1 exclusive or with the l.s.b. of k. #
# sgn1 := (-1)**j1, sgn2 := (-1)**j2. #
# SIN(X) = sgn1 * cos(r) and COS(X) = sgn2*sin(r) where #
-# sin(r) and cos(r) are computed as odd and even #
+# sin(r) and cos(r) are computed as odd and even #
# polynomials in r, respectively. Exit #
# #
# 5. (k is even) Set j1 := k/2, sgn1 := (-1)**j1. #
# SIN(X) = sgn1 * sin(r) and COS(X) = sgn1*cos(r) where #
-# sin(r) and cos(r) are computed as odd and even #
+# sin(r) and cos(r) are computed as odd and even #
# polynomials in r, respectively. Exit #
# #
# 6. If |X| > 1, go to 8. #
# #
# 7. (|X|<2**(-40)) SIN(X) = X and COS(X) = 1. Exit. #
# #
-# 8. Overwrite X by X := X rem 2Pi. Now that |X| <= Pi, #
+# 8. Overwrite X by X := X rem 2Pi. Now that |X| <= Pi, #
# go back to 2. #
# #
#########################################################################
@@ -5046,9 +5046,9 @@ SOK1:
#--THE ARGUMENT REDUCTION IS DONE BY TABLE LOOK UP.
SINMAIN:
fmov.x %fp0,%fp1
- fmul.d TWOBYPI(%pc),%fp1 # X*2/PI
+ fmul.d TWOBYPI(%pc),%fp1 # X*2/PI
- lea PITBL+0x200(%pc),%a1 # TABLE OF N*PI/2, N = -32,...,32
+ lea PITBL+0x200(%pc),%a1 # TABLE OF N*PI/2, N = -32,...,32
fmov.l %fp1,INT(%a6) # CONVERT TO INTEGER
@@ -5058,8 +5058,8 @@ SINMAIN:
# A1 IS THE ADDRESS OF N*PIBY2
# ...WHICH IS IN TWO PIECES Y1 & Y2
- fsub.x (%a1)+,%fp0 # X-Y1
- fsub.s (%a1),%fp0 # fp0 = R = (X-Y1)-Y2
+ fsub.x (%a1)+,%fp0 # X-Y1
+ fsub.s (%a1),%fp0 # fp0 = R = (X-Y1)-Y2
SINCONT:
#--continuation from REDUCEX
@@ -5213,7 +5213,7 @@ SINTINY:
COSTINY:
fmov.s &0x3F800000,%fp0 # fp0 = 1.0
fmov.l %d0,%fpcr # restore users round mode,prec
- fadd.s &0x80800000,%fp0 # last inst - possible exception set
+ fadd.s &0x80800000,%fp0 # last inst - possible exception set
bra t_pinx2
################################################
@@ -5645,7 +5645,7 @@ SRESTORE:
# #
# 7. (|X|<2**(-40)) Tan(X) = X. Exit. #
# #
-# 8. Overwrite X by X := X rem 2Pi. Now that |X| <= Pi, go back #
+# 8. Overwrite X by X := X rem 2Pi. Now that |X| <= Pi, go back #
# to 2. #
# #
#########################################################################
@@ -6048,27 +6048,27 @@ RESTORE:
# The returned result is within 2 ulps in 64 significant bit, #
# i.e. within 0.5001 ulp to 53 bits if the result is subsequently #
# rounded to double precision. The result is provably monotonic #
-# in double precision. #
+# in double precision. #
# #
# ALGORITHM *********************************************************** #
# Step 1. If |X| >= 16 or |X| < 1/16, go to Step 5. #
# #
-# Step 2. Let X = sgn * 2**k * 1.xxxxxxxx...x. #
+# Step 2. Let X = sgn * 2**k * 1.xxxxxxxx...x. #
# Note that k = -4, -3,..., or 3. #
-# Define F = sgn * 2**k * 1.xxxx1, i.e. the first 5 #
+# Define F = sgn * 2**k * 1.xxxx1, i.e. the first 5 #
# significant bits of X with a bit-1 attached at the 6-th #
# bit position. Define u to be u = (X-F) / (1 + X*F). #
# #
# Step 3. Approximate arctan(u) by a polynomial poly. #
# #
-# Step 4. Return arctan(F) + poly, arctan(F) is fetched from a #
+# Step 4. Return arctan(F) + poly, arctan(F) is fetched from a #
# table of values calculated beforehand. Exit. #
# #
# Step 5. If |X| >= 16, go to Step 7. #
# #
# Step 6. Approximate arctan(X) by an odd polynomial in X. Exit. #
# #
-# Step 7. Define X' = -1/X. Approximate arctan(X') by an odd #
+# Step 7. Define X' = -1/X. Approximate arctan(X') by an odd #
# polynomial in X'. #
# Arctan(X) = sign(X)*Pi/2 + arctan(X'). Exit. #
# #
@@ -6334,7 +6334,7 @@ ATANMAIN:
fmul.x %fp2,%fp1 # A1*U*V*(A2+V*(A3+V))
fadd.x %fp1,%fp0 # ATAN(U), FP1 RELEASED
- fmovm.x (%sp)+,&0x20 # restore fp2
+ fmovm.x (%sp)+,&0x20 # restore fp2
fmov.l %d0,%fpcr # restore users rnd mode,prec
fadd.x ATANF(%a6),%fp0 # ATAN(X)
@@ -6491,7 +6491,7 @@ satand:
# a0 = pointer to extended precision input #
# d0 = round precision,mode #
# #
-# OUTPUT ************************************************************** #
+# OUTPUT ************************************************************** #
# fp0 = arcsin(X) #
# #
# ACCURACY and MONOTONICITY ******************************************* #
@@ -6531,7 +6531,7 @@ sasin:
# This catch is added here for the '060 QSP. Originally, the call to
# satan() would handle this case by causing the exception which would
-# not be caught until gen_except(). Now, with the exceptions being
+# not be caught until gen_except(). Now, with the exceptions being
# detected inside of satan(), the exception would have been handled there
# instead of inside sasin() as expected.
cmp.l %d1,&0x3FD78000
@@ -6680,7 +6680,7 @@ sacosd:
#########################################################################
# setox(): computes the exponential for a normalized input #
-# setoxd(): computes the exponential for a denormalized input #
+# setoxd(): computes the exponential for a denormalized input #
# setoxm1(): computes the exponential minus 1 for a normalized input #
# setoxm1d(): computes the exponential minus 1 for a denormalized input #
# #
@@ -6692,9 +6692,9 @@ sacosd:
# fp0 = exp(X) or exp(X)-1 #
# #
# ACCURACY and MONOTONICITY ******************************************* #
-# The returned result is within 0.85 ulps in 64 significant bit, #
+# The returned result is within 0.85 ulps in 64 significant bit, #
# i.e. within 0.5001 ulp to 53 bits if the result is subsequently #
-# rounded to double precision. The result is provably monotonic #
+# rounded to double precision. The result is provably monotonic #
# in double precision. #
# #
# ALGORITHM and IMPLEMENTATION **************************************** #
@@ -6718,14 +6718,14 @@ sacosd:
# Notes: The usual case should take the branches 1.1 -> 1.3 -> 2.#
# To avoid the use of floating-point comparisons, a #
# compact representation of |X| is used. This format is a #
-# 32-bit integer, the upper (more significant) 16 bits #
-# are the sign and biased exponent field of |X|; the #
+# 32-bit integer, the upper (more significant) 16 bits #
+# are the sign and biased exponent field of |X|; the #
# lower 16 bits are the 16 most significant fraction #
# (including the explicit bit) bits of |X|. Consequently, #
# the comparisons in Steps 1.1 and 1.3 can be performed #
# by integer comparison. Note also that the constant #
# 16380 log(2) used in Step 1.3 is also in the compact #
-# form. Thus taking the branch to Step 2 guarantees #
+# form. Thus taking the branch to Step 2 guarantees #
# |X| < 16380 log(2). There is no harm to have a small #
# number of cases where |X| is less than, but close to, #
# 16380 log(2) and the branch to Step 9 is taken. #
@@ -6737,7 +6737,7 @@ sacosd:
# 2.3 Calculate J = N mod 64; so J = 0,1,2,..., #
# or 63. #
# 2.4 Calculate M = (N - J)/64; so N = 64M + J. #
-# 2.5 Calculate the address of the stored value of #
+# 2.5 Calculate the address of the stored value of #
# 2^(J/64). #
# 2.6 Create the value Scale = 2^M. #
# Notes: The calculation in 2.2 is really performed by #
@@ -6746,26 +6746,26 @@ sacosd:
# where #
# constant := single-precision( 64/log 2 ). #
# #
-# Using a single-precision constant avoids memory #
+# Using a single-precision constant avoids memory #
# access. Another effect of using a single-precision #
-# "constant" is that the calculated value Z is #
+# "constant" is that the calculated value Z is #
# #
# Z = X*(64/log2)*(1+eps), |eps| <= 2^(-24). #
# #
# This error has to be considered later in Steps 3 and 4. #
# #
# Step 3. Calculate X - N*log2/64. #
-# 3.1 R := X + N*L1, #
+# 3.1 R := X + N*L1, #
# where L1 := single-precision(-log2/64). #
-# 3.2 R := R + N*L2, #
+# 3.2 R := R + N*L2, #
# L2 := extended-precision(-log2/64 - L1).#
-# Notes: a) The way L1 and L2 are chosen ensures L1+L2 #
+# Notes: a) The way L1 and L2 are chosen ensures L1+L2 #
# approximate the value -log2/64 to 88 bits of accuracy. #
# b) N*L1 is exact because N is no longer than 22 bits #
# and L1 is no longer than 24 bits. #
-# c) The calculation X+N*L1 is also exact due to #
+# c) The calculation X+N*L1 is also exact due to #
# cancellation. Thus, R is practically X+N(L1+L2) to full #
-# 64 bits. #
+# 64 bits. #
# d) It is important to estimate how large can |R| be #
# after Step 3.2. #
# #
@@ -6783,11 +6783,11 @@ sacosd:
# #
# Step 4. Approximate exp(R)-1 by a polynomial #
# p = R + R*R*(A1 + R*(A2 + R*(A3 + R*(A4 + R*A5)))) #
-# Notes: a) In order to reduce memory access, the coefficients #
+# Notes: a) In order to reduce memory access, the coefficients #
# are made as "short" as possible: A1 (which is 1/2), A4 #
# and A5 are single precision; A2 and A3 are double #
-# precision. #
-# b) Even with the restrictions above, #
+# precision. #
+# b) Even with the restrictions above, #
# |p - (exp(R)-1)| < 2^(-68.8) for all |R| <= 0.0062. #
# Note that 0.0062 is slightly bigger than 0.57 log2/64. #
# c) To fully utilize the pipeline, p is separated into #
@@ -6801,11 +6801,11 @@ sacosd:
# where T and t are the stored values for 2^(J/64). #
# Notes: 2^(J/64) is stored as T and t where T+t approximates #
# 2^(J/64) to roughly 85 bits; T is in extended precision #
-# and t is in single precision. Note also that T is #
-# rounded to 62 bits so that the last two bits of T are #
-# zero. The reason for such a special form is that T-1, #
+# and t is in single precision. Note also that T is #
+# rounded to 62 bits so that the last two bits of T are #
+# zero. The reason for such a special form is that T-1, #
# T-2, and T-8 will all be exact --- a property that will #
-# give much more accurate computation of the function #
+# give much more accurate computation of the function #
# EXPM1. #
# #
# Step 6. Reconstruction of exp(X) #
@@ -6821,11 +6821,11 @@ sacosd:
# X = (M1+M)log2 + Jlog2/64 + R, |M1+M| >= 16380. #
# Hence, exp(X) may overflow or underflow or neither. #
# When that is the case, AdjScale = 2^(M1) where M1 is #
-# approximately M. Thus 6.2 will never cause #
+# approximately M. Thus 6.2 will never cause #
# over/underflow. Possible exception in 6.4 is overflow #
# or underflow. The inexact exception is not generated in #
# 6.4. Although one can argue that the inexact flag #
-# should always be raised, to simulate that exception #
+# should always be raised, to simulate that exception #
# cost to much than the flag is worth in practical uses. #
# #
# Step 7. Return 1 + X. #
@@ -6838,7 +6838,7 @@ sacosd:
# in Step 7.1 to avoid unnecessary trapping. (Although #
# the FMOVEM may not seem relevant since X is normalized, #
# the precaution will be useful in the library version of #
-# this code where the separate entry for denormalized #
+# this code where the separate entry for denormalized #
# inputs will be done away with.) #
# #
# Step 8. Handle exp(X) where |X| >= 16380log2. #
@@ -6846,9 +6846,9 @@ sacosd:
# (mimic 2.2 - 2.6) #
# 8.2 N := round-to-integer( X * 64/log2 ) #
# 8.3 Calculate J = N mod 64, J = 0,1,...,63 #
-# 8.4 K := (N-J)/64, M1 := truncate(K/2), M = K-M1, #
+# 8.4 K := (N-J)/64, M1 := truncate(K/2), M = K-M1, #
# AdjFlag := 1. #
-# 8.5 Calculate the address of the stored value #
+# 8.5 Calculate the address of the stored value #
# 2^(J/64). #
# 8.6 Create the values Scale = 2^M, AdjScale = 2^M1. #
# 8.7 Go to Step 3. #
@@ -6885,8 +6885,8 @@ sacosd:
# 1.4 Go to Step 10. #
# Notes: The usual case should take the branches 1.1 -> 1.3 -> 2.#
# However, it is conceivable |X| can be small very often #
-# because EXPM1 is intended to evaluate exp(X)-1 #
-# accurately when |X| is small. For further details on #
+# because EXPM1 is intended to evaluate exp(X)-1 #
+# accurately when |X| is small. For further details on #
# the comparisons, see the notes on Step 1 of setox. #
# #
# Step 2. Calculate N = round-to-nearest-int( X * 64/log2 ). #
@@ -6894,16 +6894,16 @@ sacosd:
# 2.2 Calculate J = N mod 64; so J = 0,1,2,..., #
# or 63. #
# 2.3 Calculate M = (N - J)/64; so N = 64M + J. #
-# 2.4 Calculate the address of the stored value of #
+# 2.4 Calculate the address of the stored value of #
# 2^(J/64). #
-# 2.5 Create the values Sc = 2^M and #
+# 2.5 Create the values Sc = 2^M and #
# OnebySc := -2^(-M). #
# Notes: See the notes on Step 2 of setox. #
# #
# Step 3. Calculate X - N*log2/64. #
-# 3.1 R := X + N*L1, #
+# 3.1 R := X + N*L1, #
# where L1 := single-precision(-log2/64). #
-# 3.2 R := R + N*L2, #
+# 3.2 R := R + N*L2, #
# L2 := extended-precision(-log2/64 - L1).#
# Notes: Applying the analysis of Step 3 of setox in this case #
# shows that |R| <= 0.0055 (note that |X| <= 70 log2 in #
@@ -6911,10 +6911,10 @@ sacosd:
# #
# Step 4. Approximate exp(R)-1 by a polynomial #
# p = R+R*R*(A1+R*(A2+R*(A3+R*(A4+R*(A5+R*A6))))) #
-# Notes: a) In order to reduce memory access, the coefficients #
-# are made as "short" as possible: A1 (which is 1/2), A5 #
-# and A6 are single precision; A2, A3 and A4 are double #
-# precision. #
+# Notes: a) In order to reduce memory access, the coefficients #
+# are made as "short" as possible: A1 (which is 1/2), A5 #
+# and A6 are single precision; A2, A3 and A4 are double #
+# precision. #
# b) Even with the restriction above, #
# |p - (exp(R)-1)| < |R| * 2^(-72.7) #
# for all |R| <= 0.0055. #
@@ -6929,9 +6929,9 @@ sacosd:
# where T and t are the stored values for 2^(J/64). #
# Notes: 2^(J/64) is stored as T and t where T+t approximates #
# 2^(J/64) to roughly 85 bits; T is in extended precision #
-# and t is in single precision. Note also that T is #
-# rounded to 62 bits so that the last two bits of T are #
-# zero. The reason for such a special form is that T-1, #
+# and t is in single precision. Note also that T is #
+# rounded to 62 bits so that the last two bits of T are #
+# zero. The reason for such a special form is that T-1, #
# T-2, and T-8 will all be exact --- a property that will #
# be exploited in Step 6 below. The total relative error #
# in p is no bigger than 2^(-67.7) compared to the final #
@@ -6946,7 +6946,7 @@ sacosd:
# 6.5 ans := (T + OnebySc) + (p + t). #
# 6.6 Restore user FPCR. #
# 6.7 Return ans := Sc * ans. Exit. #
-# Notes: The various arrangements of the expressions give #
+# Notes: The various arrangements of the expressions give #
# accurate evaluations. #
# #
# Step 7. exp(X)-1 for |X| < 1/4. #
@@ -6962,8 +6962,8 @@ sacosd:
# Return ans := ans*2^(140). Exit #
# Notes: The idea is to return "X - tiny" under the user #
# precision and rounding modes. To avoid unnecessary #
-# inefficiency, we stay away from denormalized numbers #
-# the best we can. For |X| >= 2^(-16312), the #
+# inefficiency, we stay away from denormalized numbers #
+# the best we can. For |X| >= 2^(-16312), the #
# straightforward 8.2 generates the inexact exception as #
# the case warrants. #
# #
@@ -6971,13 +6971,13 @@ sacosd:
# p = X + X*X*(B1 + X*(B2 + ... + X*B12)) #
# Notes: a) In order to reduce memory access, the coefficients #
# are made as "short" as possible: B1 (which is 1/2), B9 #
-# to B12 are single precision; B3 to B8 are double #
+# to B12 are single precision; B3 to B8 are double #
# precision; and B2 is double extended. #
# b) Even with the restriction above, #
# |p - (exp(X)-1)| < |X| 2^(-70.6) #
# for all |X| <= 0.251. #
# Note that 0.251 is slightly bigger than 1/4. #
-# c) To fully preserve accuracy, the polynomial is #
+# c) To fully preserve accuracy, the polynomial is #
# computed as #
# X + ( S*B1 + Q ) where S = X*X and #
# Q = X*S*(B2 + X*(B3 + ... + X*B12)) #
@@ -6987,11 +6987,11 @@ sacosd:
# [ S*S*(B3 + S*(B5 + ... + S*B11)) ] #
# #
# Step 10. Calculate exp(X)-1 for |X| >= 70 log 2. #
-# 10.1 If X >= 70log2 , exp(X) - 1 = exp(X) for all #
+# 10.1 If X >= 70log2 , exp(X) - 1 = exp(X) for all #
# practical purposes. Therefore, go to Step 1 of setox. #
# 10.2 If X <= -70log2, exp(X) - 1 = -1 for all practical #
-# purposes. #
-# ans := -1 #
+# purposes. #
+# ans := -1 #
# Restore user FPCR #
# Return ans := ans + 2^(-126). Exit. #
# Notes: 10.2 will always create an inexact and return -1 + tiny #
@@ -7496,10 +7496,10 @@ setoxm1d:
# sgetexp(): returns the exponent portion of the input argument. #
# The exponent bias is removed and the exponent value is #
# returned as an extended precision number in fp0. #
-# sgetexpd(): handles denormalized numbers. #
+# sgetexpd(): handles denormalized numbers. #
# #
-# sgetman(): extracts the mantissa of the input argument. The #
-# mantissa is converted to an extended precision number w/ #
+# sgetman(): extracts the mantissa of the input argument. The #
+# mantissa is converted to an extended precision number w/ #
# an exponent of $3fff and is returned in fp0. The range of #
# the result is [1.0 - 2.0). #
# sgetmand(): handles denormalized numbers. #
@@ -7573,9 +7573,9 @@ sgetmand:
# fp0 = cosh(X) #
# #
# ACCURACY and MONOTONICITY ******************************************* #
-# The returned result is within 3 ulps in 64 significant bit, #
+# The returned result is within 3 ulps in 64 significant bit, #
# i.e. within 0.5001 ulp to 53 bits if the result is subsequently #
-# rounded to double precision. The result is provably monotonic #
+# rounded to double precision. The result is provably monotonic #
# in double precision. #
# #
# ALGORITHM *********************************************************** #
@@ -7592,7 +7592,7 @@ sgetmand:
# #
# 4. (16380 log2 < |X| <= 16480 log2) #
# cosh(X) = sign(X) * exp(|X|)/2. #
-# However, invoking exp(|X|) may cause premature #
+# However, invoking exp(|X|) may cause premature #
# overflow. Thus, we calculate sinh(X) as follows: #
# Y := |X| #
# Fact := 2**(16380) #
@@ -7687,7 +7687,7 @@ scoshd:
# fp0 = sinh(X) #
# #
# ACCURACY and MONOTONICITY ******************************************* #
-# The returned result is within 3 ulps in 64 significant bit, #
+# The returned result is within 3 ulps in 64 significant bit, #
# i.e. within 0.5001 ulp to 53 bits if the result is subsequently #
# rounded to double precision. The result is provably monotonic #
# in double precision. #
@@ -7805,7 +7805,7 @@ ssinhd:
# fp0 = tanh(X) #
# #
# ACCURACY and MONOTONICITY ******************************************* #
-# The returned result is within 3 ulps in 64 significant bit, #
+# The returned result is within 3 ulps in 64 significant bit, #
# i.e. within 0.5001 ulp to 53 bits if the result is subsequently #
# rounded to double precision. The result is provably monotonic #
# in double precision. #
@@ -7971,51 +7971,51 @@ stanhd:
# fp0 = log(X) or log(1+X) #
# #
# ACCURACY and MONOTONICITY ******************************************* #
-# The returned result is within 2 ulps in 64 significant bit, #
+# The returned result is within 2 ulps in 64 significant bit, #
# i.e. within 0.5001 ulp to 53 bits if the result is subsequently #
# rounded to double precision. The result is provably monotonic #
# in double precision. #
# #
# ALGORITHM *********************************************************** #
# LOGN: #
-# Step 1. If |X-1| < 1/16, approximate log(X) by an odd #
-# polynomial in u, where u = 2(X-1)/(X+1). Otherwise, #
+# Step 1. If |X-1| < 1/16, approximate log(X) by an odd #
+# polynomial in u, where u = 2(X-1)/(X+1). Otherwise, #
# move on to Step 2. #
# #
# Step 2. X = 2**k * Y where 1 <= Y < 2. Define F to be the first #
-# seven significant bits of Y plus 2**(-7), i.e. #
-# F = 1.xxxxxx1 in base 2 where the six "x" match those #
+# seven significant bits of Y plus 2**(-7), i.e. #
+# F = 1.xxxxxx1 in base 2 where the six "x" match those #
# of Y. Note that |Y-F| <= 2**(-7). #
# #
-# Step 3. Define u = (Y-F)/F. Approximate log(1+u) by a #
+# Step 3. Define u = (Y-F)/F. Approximate log(1+u) by a #
# polynomial in u, log(1+u) = poly. #
# #
-# Step 4. Reconstruct #
+# Step 4. Reconstruct #
# log(X) = log( 2**k * Y ) = k*log(2) + log(F) + log(1+u) #
# by k*log(2) + (log(F) + poly). The values of log(F) are #
# calculated beforehand and stored in the program. #
# #
# lognp1: #
-# Step 1: If |X| < 1/16, approximate log(1+X) by an odd #
+# Step 1: If |X| < 1/16, approximate log(1+X) by an odd #
# polynomial in u where u = 2X/(2+X). Otherwise, move on #
# to Step 2. #
# #
# Step 2: Let 1+X = 2**k * Y, where 1 <= Y < 2. Define F as done #
-# in Step 2 of the algorithm for LOGN and compute #
-# log(1+X) as k*log(2) + log(F) + poly where poly #
-# approximates log(1+u), u = (Y-F)/F. #
+# in Step 2 of the algorithm for LOGN and compute #
+# log(1+X) as k*log(2) + log(F) + poly where poly #
+# approximates log(1+u), u = (Y-F)/F. #
# #
# Implementation Notes: #
-# Note 1. There are 64 different possible values for F, thus 64 #
+# Note 1. There are 64 different possible values for F, thus 64 #
# log(F)'s need to be tabulated. Moreover, the values of #
# 1/F are also tabulated so that the division in (Y-F)/F #
# can be performed by a multiplication. #
# #
-# Note 2. In Step 2 of lognp1, in order to preserved accuracy, #
-# the value Y-F has to be calculated carefully when #
-# 1/2 <= X < 3/2. #
+# Note 2. In Step 2 of lognp1, in order to preserved accuracy, #
+# the value Y-F has to be calculated carefully when #
+# 1/2 <= X < 3/2. #
# #
-# Note 3. To fully exploit the pipeline, polynomials are usually #
+# Note 3. To fully exploit the pipeline, polynomials are usually #
# separated into two parts evaluated independently before #
# being added up. #
# #
@@ -8228,9 +8228,9 @@ LOGBGN:
cmp.l %d1,&0 # CHECK IF X IS NEGATIVE
blt.w LOGNEG # LOG OF NEGATIVE ARGUMENT IS INVALID
# X IS POSITIVE, CHECK IF X IS NEAR 1
- cmp.l %d1,&0x3ffef07d # IS X < 15/16?
+ cmp.l %d1,&0x3ffef07d # IS X < 15/16?
blt.b LOGMAIN # YES
- cmp.l %d1,&0x3fff8841 # IS X > 17/16?
+ cmp.l %d1,&0x3fff8841 # IS X > 17/16?
ble.w LOGNEAR1 # NO
LOGMAIN:
@@ -8243,7 +8243,7 @@ LOGMAIN:
#--NOTE THAT U = (Y-F)/F IS VERY SMALL AND THUS APPROXIMATING
#--LOG(1+U) CAN BE VERY EFFICIENT.
#--ALSO NOTE THAT THE VALUE 1/F IS STORED IN A TABLE SO THAT NO
-#--DIVISION IS NEEDED TO CALCULATE (Y-F)/F.
+#--DIVISION IS NEEDED TO CALCULATE (Y-F)/F.
#--GET K, Y, F, AND ADDRESS OF 1/F.
asr.l &8,%d1
@@ -8458,10 +8458,10 @@ LP1REAL:
mov.l X(%a6),%d1
cmp.l %d1,&0
ble.w LP1NEG0 # LOG OF ZERO OR -VE
- cmp.l %d1,&0x3ffe8000 # IS BOUNDS [1/2,3/2]?
+ cmp.l %d1,&0x3ffe8000 # IS BOUNDS [1/2,3/2]?
blt.w LOGMAIN
cmp.l %d1,&0x3fffc000
- bgt.w LOGMAIN
+ bgt.w LOGMAIN
#--IF 1+Z > 3/2 OR 1+Z < 1/2, THEN X, WHICH IS ROUNDING 1+Z,
#--CONTAINS AT LEAST 63 BITS OF INFORMATION OF Z. IN THAT CASE,
#--SIMPLY INVOKE LOG(X) FOR LOG(1+Z).
@@ -8562,7 +8562,7 @@ slognp1d:
# a0 = pointer to extended precision input #
# d0 = round precision,mode #
# #
-# OUTPUT ************************************************************** #
+# OUTPUT ************************************************************** #
# fp0 = arctanh(X) #
# #
# ACCURACY and MONOTONICITY ******************************************* #
@@ -8677,7 +8677,7 @@ satanhd:
# 2.1 Restore the user FPCR #
# 2.2 Return ans := Y * INV_L10. #
# #
-# slog10: #
+# slog10: #
# #
# Step 0. If X < 0, create a NaN and raise the invalid operation #
# flag. Otherwise, save FPCR in D1; set FpCR to default. #
@@ -8820,7 +8820,7 @@ slog2d:
# fp0 = 2**X or 10**X #
# #
# ACCURACY and MONOTONICITY ******************************************* #
-# The returned result is within 2 ulps in 64 significant bit, #
+# The returned result is within 2 ulps in 64 significant bit, #
# i.e. within 0.5001 ulp to 53 bits if the result is subsequently #
# rounded to double precision. The result is provably monotonic #
# in double precision. #
@@ -8851,7 +8851,7 @@ slog2d:
# #
# 4. Define r as #
# r := ((X - N*L1)-N*L2) * L10 #
-# where L1, L2 are the leading and trailing parts of #
+# where L1, L2 are the leading and trailing parts of #
# log_10(2)/64 and L10 is the natural log of 10. Then #
# 10**X = 2**(M') * 2**(M) * 2**(j/64) * exp(r). #
# Go to expr to compute that expression. #
@@ -8872,7 +8872,7 @@ slog2d:
# Exit. #
# #
# ExpBig #
-# 1. Generate overflow by Huge * Huge if X > 0; otherwise, #
+# 1. Generate overflow by Huge * Huge if X > 0; otherwise, #
# generate underflow by Tiny * Tiny. #
# #
# ExpSm #
@@ -9203,7 +9203,7 @@ stentoxd:
#########################################################################
# sscale(): computes the destination operand scaled by the source #
-# operand. If the absoulute value of the source operand is #
+# operand. If the absoulute value of the source operand is #
# >= 2^14, an overflow or underflow is returned. #
# #
# INPUT *************************************************************** #
@@ -9265,7 +9265,7 @@ sok_dnrm:
bge.b sok_norm2 # thank goodness no
# the multiply factor that we're trying to create should be a denorm
-# for the multiply to work. therefore, we're going to actually do a
+# for the multiply to work. therefore, we're going to actually do a
# multiply with a denorm which will cause an unimplemented data type
# exception to be put into the machine which will be caught and corrected
# later. we don't do this with the DENORMs above because this method
@@ -9280,7 +9280,7 @@ sok_dnrm:
clr.l -(%sp) # insert zero low mantissa
mov.l %d1,-(%sp) # insert new high mantissa
clr.l -(%sp) # make zero exponent
- bra.b sok_norm_cont
+ bra.b sok_norm_cont
sok_dnrm_32:
subi.b &0x20,%d0 # get shift count
lsr.l %d0,%d1 # make low mantissa longword
@@ -9288,7 +9288,7 @@ sok_dnrm_32:
clr.l -(%sp) # insert zero high mantissa
clr.l -(%sp) # make zero exponent
bra.b sok_norm_cont
-
+
# the src will force the dst to a DENORM value or worse. so, let's
# create an fp multiply that will create the result.
sok_norm:
@@ -9346,7 +9346,7 @@ ssmall_done:
# a1 = pointer to extended precision input Y #
# d0 = round precision,mode #
# #
-# The input operands X and Y can be either normalized or #
+# The input operands X and Y can be either normalized or #
# denormalized. #
# #
# OUTPUT ************************************************************** #
@@ -9355,7 +9355,7 @@ ssmall_done:
# ALGORITHM *********************************************************** #
# #
# Step 1. Save and strip signs of X and Y: signX := sign(X), #
-# signY := sign(Y), X := |X|, Y := |Y|, #
+# signY := sign(Y), X := |X|, Y := |Y|, #
# signQ := signX EOR signY. Record whether MOD or REM #
# is requested. #
# #
@@ -9375,7 +9375,7 @@ ssmall_done:
# #
# Step 4. At this point, R = X - QY = MOD(X,Y). Set #
# Last_Subtract := false (used in Step 7 below). If #
-# MOD is requested, go to Step 6. #
+# MOD is requested, go to Step 6. #
# #
# Step 5. R = MOD(X,Y), but REM(X,Y) is requested. #
# 5.1 If R < Y/2, then R = MOD(X,Y) = REM(X,Y). Go to #
@@ -9701,8 +9701,8 @@ Restore:
mov.b &FMUL_OP,%d1 # last inst is MUL
fmul.x Scale(%pc),%fp0 # may cause underflow
bra t_catch2
-# the '040 package did this apparently to see if the dst operand for the
-# preceding fmul was a denorm. but, it better not have been since the
+# the '040 package did this apparently to see if the dst operand for the
+# preceding fmul was a denorm. but, it better not have been since the
# algorithm just got done playing with fp0 and expected no exceptions
# as a result. trust me...
# bra t_avoid_unsupp # check for denorm as a
@@ -9716,7 +9716,7 @@ Finish:
Rem_is_0:
#..R = 2^(-j)X - Q Y = Y, thus R = 0 and quotient = 2^j (Q+1)
addq.l &1,%d3
- cmp.l %d0,&8 # D0 is j
+ cmp.l %d0,&8 # D0 is j
bge.b Q_Big
lsl.l %d0,%d3
@@ -9746,7 +9746,7 @@ Tie_Case:
#########################################################################
# XDEF **************************************************************** #
-# tag(): return the optype of the input ext fp number #
+# tag(): return the optype of the input ext fp number #
# #
# This routine is used by the 060FPLSP. #
# #
@@ -9755,13 +9755,13 @@ Tie_Case:
# #
# INPUT *************************************************************** #
# a0 = pointer to extended precision operand #
-# #
+# #
# OUTPUT ************************************************************** #
# d0 = value of type tag #
-# one of: NORM, INF, QNAN, SNAN, DENORM, ZERO #
+# one of: NORM, INF, QNAN, SNAN, DENORM, ZERO #
# #
# ALGORITHM *********************************************************** #
-# Simply test the exponent, j-bit, and mantissa values to #
+# Simply test the exponent, j-bit, and mantissa values to #
# determine the type of operand. #
# If it's an unnormalized zero, alter the operand and force it #
# to be a normal zero. #
@@ -9829,15 +9829,15 @@ qnan: long 0x7fff0000, 0xffffffff, 0xff
# #
# INPUT *************************************************************** #
# a0 = pointer to extended precision source operand. #
-# #
+# #
# OUTPUT ************************************************************** #
# fp0 = default DZ result. #
# #
# ALGORITHM *********************************************************** #
-# Transcendental emulation for the 060FPLSP has detected that #
+# Transcendental emulation for the 060FPLSP has detected that #
# a DZ exception should occur for the instruction. If DZ is disabled, #
# return the default result. #
-# If DZ is enabled, the dst operand should be returned unscathed #
+# If DZ is enabled, the dst operand should be returned unscathed #
# in fp0 while fp1 is used to create a DZ exception so that the #
# operating system can log that such an event occurred. #
# #
@@ -9898,7 +9898,7 @@ dz_pinf_ena:
# #
# INPUT *************************************************************** #
# fp1 = source operand #
-# #
+# #
# OUTPUT ************************************************************** #
# fp0 = default result #
# fp1 = unchanged #
@@ -9927,7 +9927,7 @@ t_operr:
# but use fp2 instead. return the dst operand unscathed in fp0.
operr_ena:
fmovm.x EXC_FP0(%a6),&0x80 # return fp0 unscathed
- fmov.l USER_FPCR(%a6),%fpcr
+ fmov.l USER_FPCR(%a6),%fpcr
fmovm.x &0x04,-(%sp) # save fp2
fmov.s &0x7f800000,%fp2 # load +INF
fmul.s &0x00000000,%fp2 # +INF x 0
@@ -9956,7 +9956,7 @@ mns_tiny:
# #
# INPUT *************************************************************** #
# a0 = pointer to extended precision source operand #
-# #
+# #
# OUTPUT ************************************************************** #
# fp0 = default underflow result #
# #
@@ -10003,8 +10003,8 @@ unf_pos:
# (monadic) #
# t_ovfl2(): Handle 060FPLSP overflow exception during #
# emulation. result always positive. (dyadic) #
-# t_ovfl_sc(): Handle 060FPLSP overflow exception during #
-# emulation for "fscale". #
+# t_ovfl_sc(): Handle 060FPLSP overflow exception during #
+# emulation for "fscale". #
# #
# This routine is used by the 060FPLSP package. #
# #
@@ -10013,7 +10013,7 @@ unf_pos:
# #
# INPUT *************************************************************** #
# a0 = pointer to extended precision source operand #
-# #
+# #
# OUTPUT ************************************************************** #
# fp0 = default underflow result #
# #
@@ -10113,12 +10113,12 @@ t_ovfl2:
# #
# INPUT *************************************************************** #
# fp0 = default underflow or overflow result #
-# #
+# #
# OUTPUT ************************************************************** #
# fp0 = default result #
# #
# ALGORITHM *********************************************************** #
-# If an overflow or underflow occurred during the last #
+# If an overflow or underflow occurred during the last #
# instruction of transcendental 060FPLSP emulation, then it has already #
# occurred and has been logged. Now we need to see if an inexact #
# exception should occur. #
@@ -10147,16 +10147,16 @@ t_catch:
# #
# INPUT *************************************************************** #
# fp0 = default result #
-# #
+# #
# OUTPUT ************************************************************** #
# fp0 = default result #
# #
# ALGORITHM *********************************************************** #
-# The last instruction of transcendental emulation for the #
+# The last instruction of transcendental emulation for the #
# 060FPLSP should be inexact. So, if inexact is enabled, then we create #
# the event here by adding a large and very small number together #
# so that the operating system can log the event. #
-# Must check, too, if the result was zero, in which case we just #
+# Must check, too, if the result was zero, in which case we just #
# set the FPSR bits and return. #
# #
#########################################################################
@@ -10178,7 +10178,7 @@ t_minx2:
inx2_work:
btst &inex2_bit,FPCR_ENABLE(%a6) # is inexact enabled?
bne.b inx2_work_ena # yes
- rts
+ rts
inx2_work_ena:
fmov.l USER_FPCR(%a6),%fpcr # insert user's exceptions
fmov.s &0x3f800000,%fp1 # load +1
@@ -10202,7 +10202,7 @@ inx2_zero:
# #
# INPUT *************************************************************** #
# a0 = pointer to extended precision input operand #
-# #
+# #
# OUTPUT ************************************************************** #
# fp0 = default result #
# #
@@ -10235,7 +10235,7 @@ t_resdnrm:
#
# sto_cos:
-# This is used by fsincos library emulation. The correct
+# This is used by fsincos library emulation. The correct
# values are already in fp0 and fp1 so we do nothing here.
#
global sto_cos
@@ -10485,7 +10485,7 @@ ld_mzero:
#########################################################################
global dst_zero
dst_zero:
- tst.b DST_EX(%a1) # get sign of dst operand
+ tst.b DST_EX(%a1) # get sign of dst operand
bmi.b ld_mzero # if neg, load neg zero
bra.b ld_pzero # load positive zero
@@ -10494,7 +10494,7 @@ dst_zero:
#########################################################################
global src_inf
src_inf:
- tst.b SRC_EX(%a0) # get sign of src operand
+ tst.b SRC_EX(%a0) # get sign of src operand
bmi.b ld_minf # if negative branch
#
@@ -10520,7 +10520,7 @@ ld_minf:
#########################################################################
global dst_inf
dst_inf:
- tst.b DST_EX(%a1) # get sign of dst operand
+ tst.b DST_EX(%a1) # get sign of dst operand
bmi.b ld_minf # if negative branch
bra.b ld_pinf
@@ -10562,7 +10562,7 @@ setoxm1i:
#########################################################################
global src_one
src_one:
- tst.b SRC_EX(%a0) # check sign of source
+ tst.b SRC_EX(%a0) # check sign of source
bmi.b ld_mone
#
@@ -10591,7 +10591,7 @@ mpiby2: long 0xbfff0000, 0xc90fdaa2, 0x
#################################################################
global spi_2
spi_2:
- tst.b SRC_EX(%a0) # check sign of source
+ tst.b SRC_EX(%a0) # check sign of source
bmi.b ld_mpi2
#
@@ -10618,7 +10618,7 @@ ld_mpi2:
#
# ssincosz(): When the src operand is ZERO, store a one in the
-# cosine register and return a ZERO in fp0 w/ the same sign
+# cosine register and return a ZERO in fp0 w/ the same sign
# as the src operand.
#
global ssincosz
@@ -10646,7 +10646,7 @@ ssincosi:
#
# ssincosqnan(): When the src operand is a QNAN, store the QNAN in the cosine
-# register and branch to the src QNAN routine.
+# register and branch to the src QNAN routine.
#
global ssincosqnan
ssincosqnan:
@@ -10827,7 +10827,7 @@ sop_sqnan:
# a0 = pointer fp extended precision operand to normalize #
# #
# OUTPUT ************************************************************** #
-# d0 = number of bit positions the mantissa was shifted #
+# d0 = number of bit positions the mantissa was shifted #
# a0 = the input operand's mantissa is normalized; the exponent #
# is unchanged. #
# #
@@ -10854,7 +10854,7 @@ norm_hi:
mov.l %d1, FTEMP_LO(%a0) # store new lo(man)
mov.l %d2, %d0 # return shift amount
-
+
mov.l (%sp)+, %d3 # restore temp regs
mov.l (%sp)+, %d2
@@ -10869,7 +10869,7 @@ norm_lo:
clr.l FTEMP_LO(%a0) # lo(man) is now zero
mov.l %d2, %d0 # return shift amount
-
+
mov.l (%sp)+, %d3 # restore temp regs
mov.l (%sp)+, %d2
@@ -10974,7 +10974,7 @@ unnorm_nrm_zero_lrg:
# whole mantissa is zero so this UNNORM is actually a zero
#
unnorm_zero:
- and.w &0x8000, FTEMP_EX(%a0) # force exponent to zero
+ and.w &0x8000, FTEMP_EX(%a0) # force exponent to zero
mov.b &ZERO, %d0 # fix optype tag
rts
diff -puN arch/m68k/ifpsp060/src/fpsp.S~m68k-superfluous-whitespace arch/m68k/ifpsp060/src/fpsp.S
--- 25/arch/m68k/ifpsp060/src/fpsp.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/ifpsp060/src/fpsp.S Thu Apr 22 13:43:13 2004
@@ -5,10 +5,10 @@ M68060 Software Package
Production Release P1.00 -- October 10, 1994
M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved.
-
+
THE SOFTWARE is provided on an "AS IS" basis and without warranty.
To the maximum extent permitted by applicable law,
-MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
+MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
and any warranty against infringement with regard to the SOFTWARE
(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
@@ -90,7 +90,7 @@ _060FPSP_TABLE:
bra.l _fpsp_effadd
short 0x0000
- space 56
+ space 56
###############################################################
global _fpsp_done
@@ -324,33 +324,33 @@ set EXC_D2, EXC_DREGS+(2*4)
set EXC_D1, EXC_DREGS+(1*4)
set EXC_D0, EXC_DREGS+(0*4)
-set EXC_FP0, EXC_FPREGS+(0*12) # offset of saved fp0
-set EXC_FP1, EXC_FPREGS+(1*12) # offset of saved fp1
-set EXC_FP2, EXC_FPREGS+(2*12) # offset of saved fp2 (not used)
+set EXC_FP0, EXC_FPREGS+(0*12) # offset of saved fp0
+set EXC_FP1, EXC_FPREGS+(1*12) # offset of saved fp1
+set EXC_FP2, EXC_FPREGS+(2*12) # offset of saved fp2 (not used)
-set FP_SCR1, LV+80 # fp scratch 1
-set FP_SCR1_EX, FP_SCR1+0
+set FP_SCR1, LV+80 # fp scratch 1
+set FP_SCR1_EX, FP_SCR1+0
set FP_SCR1_SGN, FP_SCR1+2
-set FP_SCR1_HI, FP_SCR1+4
-set FP_SCR1_LO, FP_SCR1+8
+set FP_SCR1_HI, FP_SCR1+4
+set FP_SCR1_LO, FP_SCR1+8
-set FP_SCR0, LV+68 # fp scratch 0
-set FP_SCR0_EX, FP_SCR0+0
+set FP_SCR0, LV+68 # fp scratch 0
+set FP_SCR0_EX, FP_SCR0+0
set FP_SCR0_SGN, FP_SCR0+2
-set FP_SCR0_HI, FP_SCR0+4
-set FP_SCR0_LO, FP_SCR0+8
+set FP_SCR0_HI, FP_SCR0+4
+set FP_SCR0_LO, FP_SCR0+8
-set FP_DST, LV+56 # fp destination operand
-set FP_DST_EX, FP_DST+0
+set FP_DST, LV+56 # fp destination operand
+set FP_DST_EX, FP_DST+0
set FP_DST_SGN, FP_DST+2
-set FP_DST_HI, FP_DST+4
-set FP_DST_LO, FP_DST+8
+set FP_DST_HI, FP_DST+4
+set FP_DST_LO, FP_DST+8
-set FP_SRC, LV+44 # fp source operand
-set FP_SRC_EX, FP_SRC+0
+set FP_SRC, LV+44 # fp source operand
+set FP_SRC_EX, FP_SRC+0
set FP_SRC_SGN, FP_SRC+2
-set FP_SRC_HI, FP_SRC+4
-set FP_SRC_LO, FP_SRC+8
+set FP_SRC_HI, FP_SRC+4
+set FP_SRC_LO, FP_SRC+8
set USER_FPIAR, LV+40 # FP instr address register
@@ -374,7 +374,7 @@ set EXC_TEMP2, LV+24 # temporary spac
set EXC_TEMP, LV+16 # temporary space
set DTAG, LV+15 # destination operand type
-set STAG, LV+14 # source operand type
+set STAG, LV+14 # source operand type
set SPCOND_FLG, LV+10 # flag: special case (see below)
@@ -389,17 +389,17 @@ set EXC_OPWORD, LV+0 # saved operatio
# Helpful macros
set FTEMP, 0 # offsets within an
-set FTEMP_EX, 0 # extended precision
+set FTEMP_EX, 0 # extended precision
set FTEMP_SGN, 2 # value saved in memory.
-set FTEMP_HI, 4
-set FTEMP_LO, 8
+set FTEMP_HI, 4
+set FTEMP_LO, 8
set FTEMP_GRS, 12
set LOCAL, 0 # offsets within an
-set LOCAL_EX, 0 # extended precision
+set LOCAL_EX, 0 # extended precision
set LOCAL_SGN, 2 # value saved in memory.
-set LOCAL_HI, 4
-set LOCAL_LO, 8
+set LOCAL_HI, 4
+set LOCAL_LO, 8
set LOCAL_GRS, 12
set DST, 0 # offsets within an
@@ -489,17 +489,17 @@ set ainex_mask, 0x00000008 # accrued i
######################################
set dzinf_mask, inf_mask+dz_mask+adz_mask
set opnan_mask, nan_mask+operr_mask+aiop_mask
-set nzi_mask, 0x01ffffff #clears N, Z, and I
+set nzi_mask, 0x01ffffff #clears N, Z, and I
set unfinx_mask, unfl_mask+inex2_mask+aunfl_mask+ainex_mask
set unf2inx_mask, unfl_mask+inex2_mask+ainex_mask
set ovfinx_mask, ovfl_mask+inex2_mask+aovfl_mask+ainex_mask
set inx1a_mask, inex1_mask+ainex_mask
set inx2a_mask, inex2_mask+ainex_mask
-set snaniop_mask, nan_mask+snan_mask+aiop_mask
+set snaniop_mask, nan_mask+snan_mask+aiop_mask
set snaniop2_mask, snan_mask+aiop_mask
set naniop_mask, nan_mask+aiop_mask
set neginf_mask, neg_mask+inf_mask
-set infaiop_mask, inf_mask+aiop_mask
+set infaiop_mask, inf_mask+aiop_mask
set negz_mask, neg_mask+z_mask
set opaop_mask, operr_mask+aiop_mask
set unfl_inx_mask, unfl_mask+aunfl_mask+ainex_mask
@@ -528,8 +528,8 @@ set rp_mode, 0x3 # round-to-plus-infi
set mantissalen, 64 # length of mantissa in bits
set BYTE, 1 # len(byte) == 1 byte
-set WORD, 2 # len(word) == 2 bytes
-set LONG, 4 # len(longword) == 2 bytes
+set WORD, 2 # len(word) == 2 bytes
+set LONG, 4 # len(longword) == 2 bytes
set BSUN_VEC, 0xc0 # bsun vector offset
set INEX_VEC, 0xc4 # inexact vector offset
@@ -599,7 +599,7 @@ TWOBYPI:
# INPUT *************************************************************** #
# - The system stack contains the FP Ovfl exception stack frame #
# - The fsave frame contains the source operand #
-# #
+# #
# OUTPUT ************************************************************** #
# Overflow Exception enabled: #
# - The system stack is unchanged #
@@ -610,24 +610,24 @@ TWOBYPI:
# #
# ALGORITHM *********************************************************** #
# On the 060, if an FP overflow is present as the result of any #
-# instruction, the 060 will take an overflow exception whether the #
-# exception is enabled or disabled in the FPCR. For the disabled case, #
+# instruction, the 060 will take an overflow exception whether the #
+# exception is enabled or disabled in the FPCR. For the disabled case, #
# This handler emulates the instruction to determine what the correct #
# default result should be for the operation. This default result is #
-# then stored in either the FP regfile, data regfile, or memory. #
-# Finally, the handler exits through the "callout" _fpsp_done() #
+# then stored in either the FP regfile, data regfile, or memory. #
+# Finally, the handler exits through the "callout" _fpsp_done() #
# denoting that no exceptional conditions exist within the machine. #
-# If the exception is enabled, then this handler must create the #
+# If the exception is enabled, then this handler must create the #
# exceptional operand and plave it in the fsave state frame, and store #
-# the default result (only if the instruction is opclass 3). For #
-# exceptions enabled, this handler must exit through the "callout" #
+# the default result (only if the instruction is opclass 3). For #
+# exceptions enabled, this handler must exit through the "callout" #
# _real_ovfl() so that the operating system enabled overflow handler #
# can handle this case. #
-# Two other conditions exist. First, if overflow was disabled #
-# but the inexact exception was enabled, this handler must exit #
+# Two other conditions exist. First, if overflow was disabled #
+# but the inexact exception was enabled, this handler must exit #
# through the "callout" _real_inex() regardless of whether the result #
# was inexact. #
-# Also, in the case of an opclass three instruction where #
+# Also, in the case of an opclass three instruction where #
# overflow was disabled and the trace exception was enabled, this #
# handler must exit through the "callout" _real_trace(). #
# #
@@ -642,9 +642,9 @@ _fpsp_ovfl:
fsave FP_SRC(%a6) # grab the "busy" frame
- movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
+ movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs
- fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
+ fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
# the FPIAR holds the "current PC" of the faulting instruction
mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6)
@@ -668,7 +668,7 @@ _fpsp_ovfl:
bsr.l set_tag_x # tag the operand type
mov.b %d0,STAG(%a6) # maybe NORM,DENORM
-# bit five of the fp extension word separates the monadic and dyadic operations
+# bit five of the fp extension word separates the monadic and dyadic operations
# that can pass through fpsp_ovfl(). remember that fcmp, ftst, and fsincos
# will never take this exception.
btst &0x5,1+EXC_CMDREG(%a6) # is operation monadic or dyadic?
@@ -741,7 +741,7 @@ fovfl_extract:
fovfl_ovfl_on:
fmovm.x &0x40,FP_SRC(%a6) # save EXOP (fp1) to stack
- mov.w &0xe005,2+FP_SRC(%a6) # save exc status
+ mov.w &0xe005,2+FP_SRC(%a6) # save exc status
fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
@@ -757,10 +757,10 @@ fovfl_ovfl_on:
# we must jump to real_inex().
fovfl_inex_on:
- fmovm.x &0x40,FP_SRC(%a6) # save EXOP (fp1) to stack
+ fmovm.x &0x40,FP_SRC(%a6) # save EXOP (fp1) to stack
mov.b &0xc4,1+EXC_VOFF(%a6) # vector offset = 0xc4
- mov.w &0xe001,2+FP_SRC(%a6) # save exc status
+ mov.w &0xe001,2+FP_SRC(%a6) # save exc status
fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
@@ -811,7 +811,7 @@ fovfl_out:
btst &0x7,(%sp) # is trace on?
beq.l _fpsp_done # no
- fmov.l %fpiar,0x8(%sp) # "Current PC" is in FPIAR
+ fmov.l %fpiar,0x8(%sp) # "Current PC" is in FPIAR
mov.w &0x2024,0x6(%sp) # stk fmt = 0x2; voff = 0x024
bra.l _real_trace
@@ -839,7 +839,7 @@ fovfl_out:
# INPUT *************************************************************** #
# - The system stack contains the FP Unfl exception stack frame #
# - The fsave frame contains the source operand #
-# #
+# #
# OUTPUT ************************************************************** #
# Underflow Exception enabled: #
# - The system stack is unchanged #
@@ -850,24 +850,24 @@ fovfl_out:
# #
# ALGORITHM *********************************************************** #
# On the 060, if an FP underflow is present as the result of any #
-# instruction, the 060 will take an underflow exception whether the #
-# exception is enabled or disabled in the FPCR. For the disabled case, #
+# instruction, the 060 will take an underflow exception whether the #
+# exception is enabled or disabled in the FPCR. For the disabled case, #
# This handler emulates the instruction to determine what the correct #
# default result should be for the operation. This default result is #
-# then stored in either the FP regfile, data regfile, or memory. #
-# Finally, the handler exits through the "callout" _fpsp_done() #
+# then stored in either the FP regfile, data regfile, or memory. #
+# Finally, the handler exits through the "callout" _fpsp_done() #
# denoting that no exceptional conditions exist within the machine. #
-# If the exception is enabled, then this handler must create the #
+# If the exception is enabled, then this handler must create the #
# exceptional operand and plave it in the fsave state frame, and store #
-# the default result (only if the instruction is opclass 3). For #
-# exceptions enabled, this handler must exit through the "callout" #
+# the default result (only if the instruction is opclass 3). For #
+# exceptions enabled, this handler must exit through the "callout" #
# _real_unfl() so that the operating system enabled overflow handler #
# can handle this case. #
-# Two other conditions exist. First, if underflow was disabled #
-# but the inexact exception was enabled and the result was inexact, #
+# Two other conditions exist. First, if underflow was disabled #
+# but the inexact exception was enabled and the result was inexact, #
# this handler must exit through the "callout" _real_inex(). #
# was inexact. #
-# Also, in the case of an opclass three instruction where #
+# Also, in the case of an opclass three instruction where #
# underflow was disabled and the trace exception was enabled, this #
# handler must exit through the "callout" _real_trace(). #
# #
@@ -882,12 +882,12 @@ _fpsp_unfl:
fsave FP_SRC(%a6) # grab the "busy" frame
- movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
+ movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs
- fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
+ fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
# the FPIAR holds the "current PC" of the faulting instruction
- mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6)
+ mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6)
mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
bsr.l _imem_read_long # fetch the instruction words
@@ -906,13 +906,13 @@ _fpsp_unfl:
bsr.l set_tag_x # tag the operand type
mov.b %d0,STAG(%a6) # maybe NORM,DENORM
-# bit five of the fp ext word separates the monadic and dyadic operations
+# bit five of the fp ext word separates the monadic and dyadic operations
# that can pass through fpsp_unfl(). remember that fcmp, and ftst
# will never take this exception.
btst &0x5,1+EXC_CMDREG(%a6) # is op monadic or dyadic?
beq.b funfl_extract # monadic
-# now, what's left that's not dyadic is fsincos. we can distinguish it
+# now, what's left that's not dyadic is fsincos. we can distinguish it
# from all dyadics by the '0110xxx pattern
btst &0x4,1+EXC_CMDREG(%a6) # is op an fsincos?
bne.b funfl_extract # yes
@@ -963,7 +963,7 @@ funfl_extract:
# (0x00000000_80000000_00000000), then the machine will take an
# underflow exception. Since this is incorrect, we need to check
# if our emulation, after re-doing the operation, decided that
-# no underflow was called for. We do these checks only in
+# no underflow was called for. We do these checks only in
# funfl_{unfl,inex}_on() because w/ both exceptions disabled, this
# special case will simply exit gracefully with the correct result.
@@ -1003,7 +1003,7 @@ funfl_unfl_on:
funfl_unfl_on2:
fmovm.x &0x40,FP_SRC(%a6) # save EXOP (fp1) to stack
- mov.w &0xe003,2+FP_SRC(%a6) # save exc status
+ mov.w &0xe003,2+FP_SRC(%a6) # save exc status
fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
@@ -1022,7 +1022,7 @@ funfl_inex_on:
# The `060 FPU multiplier hardware is such that if the result of a
# multiply operation is the smallest possible normalized number
# (0x00000000_80000000_00000000), then the machine will take an
-# underflow exception.
+# underflow exception.
# But, whether bogus or not, if inexact is enabled AND it occurred,
# then we have to branch to real_inex.
@@ -1031,10 +1031,10 @@ funfl_inex_on:
funfl_inex_on2:
- fmovm.x &0x40,FP_SRC(%a6) # save EXOP to stack
+ fmovm.x &0x40,FP_SRC(%a6) # save EXOP to stack
mov.b &0xc4,1+EXC_VOFF(%a6) # vector offset = 0xc4
- mov.w &0xe001,2+FP_SRC(%a6) # save exc status
+ mov.w &0xe001,2+FP_SRC(%a6) # save exc status
fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
@@ -1120,7 +1120,7 @@ funfl_out:
# INPUT *************************************************************** #
# - The system stack contains the "Unimp Data Type" stk frame #
# - The fsave frame contains the ssrc op (for UNNORM/DENORM) #
-# #
+# #
# OUTPUT ************************************************************** #
# If Inexact exception (opclass 3): #
# - The system stack is changed to an Inexact exception stk frame #
@@ -1139,12 +1139,12 @@ funfl_out:
# #
# ALGORITHM *********************************************************** #
# Two main instruction types can enter here: (1) DENORM or UNNORM #
-# unimplemented data types. These can be either opclass 0,2 or 3 #
+# unimplemented data types. These can be either opclass 0,2 or 3 #
# instructions, and (2) PACKED unimplemented data format instructions #
# also of opclasses 0,2, or 3. #
# For UNNORM/DENORM opclass 0 and 2, the handler fetches the src #
# operand from the fsave state frame and the dst operand (if dyadic) #
-# from the FP register file. The instruction is then emulated by #
+# from the FP register file. The instruction is then emulated by #
# choosing an emulation routine from a table of routines indexed by #
# instruction type. Once the instruction has been emulated and result #
# saved, then we check to see if any enabled exceptions resulted from #
@@ -1166,7 +1166,7 @@ funfl_out:
# (a Trace stack frame must be created here, too). If an FP exception #
# should occur, then we must create an exception stack frame of that #
# type and jump to either _real_snan(), _real_operr(), _real_inex(), #
-# _real_unfl(), or _real_ovfl() as appropriate. PACKED opclass 3 #
+# _real_unfl(), or _real_ovfl() as appropriate. PACKED opclass 3 #
# emulation is performed in a similar manner. #
# #
#########################################################################
@@ -1178,7 +1178,7 @@ funfl_out:
# *****************
# * EA *
# pre-instruction * *
-# ***************** *****************
+# ***************** *****************
# * 0x0 * 0x0dc * * 0x3 * 0x0dc *
# ***************** *****************
# * Next * * Next *
@@ -1207,9 +1207,9 @@ _fpsp_unsupp:
fsave FP_SRC(%a6) # save fp state
- movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
+ movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs
- fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
+ fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
btst &0x5,EXC_SR(%a6) # user or supervisor mode?
bne.b fu_s
@@ -1258,7 +1258,7 @@ fu_cont:
fmov.l &0x0,%fpsr
# Opclass two w/ memory-to-fpn operation will have an incorrect extended
-# precision format if the src format was single or double and the
+# precision format if the src format was single or double and the
# source data type was an INF, NAN, DENORM, or UNNORM
lea FP_SRC(%a6),%a0 # pass ptr to input
bsr.l fix_skewed_ops
@@ -1277,7 +1277,7 @@ fu_op2:
bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg
-# bit five of the fp extension word separates the monadic and dyadic operations
+# bit five of the fp extension word separates the monadic and dyadic operations
# at this point
btst &0x5,1+EXC_CMDREG(%a6) # is operation monadic or dyadic?
beq.b fu_extract # monadic
@@ -1308,13 +1308,13 @@ fu_extract:
#
# Exceptions in order of precedence:
-# BSUN : none
+# BSUN : none
# SNAN : all dyadic ops
# OPERR : fsqrt(-NORM)
# OVFL : all except ftst,fcmp
# UNFL : all except ftst,fcmp
# DZ : fdiv
-# INEX2 : all except ftst,fcmp
+# INEX2 : all except ftst,fcmp
# INEX1 : none (packed doesn't go through here)
#
@@ -1351,16 +1351,16 @@ fu_in_ena:
#
# No exceptions occurred that were also enabled. Now:
#
-# if (OVFL && ovfl_disabled && inexact_enabled) {
+# if (OVFL && ovfl_disabled && inexact_enabled) {
# branch to _real_inex() (even if the result was exact!);
-# } else {
+# } else {
# save the result in the proper fp reg (unless the op is fcmp or ftst);
# return;
-# }
+# }
#
btst &ovfl_bit,FPSR_EXCEPT(%a6) # was overflow set?
beq.b fu_in_cont # no
-
+
fu_in_ovflchk:
btst &inex2_bit,FPCR_ENABLE(%a6) # was inexact enabled?
beq.b fu_in_cont # no
@@ -1380,7 +1380,7 @@ fu_in_ovflchk:
# } else {
# restore exc state (SNAN||OPERR||OVFL||UNFL||DZ||INEX) into the FPU;
# }
-#
+#
fu_in_exc:
subi.l &24,%d0 # fix offset to be 0-8
cmpi.b %d0,&0x6 # is exception INEX? (6)
@@ -1393,7 +1393,7 @@ fu_in_exc:
bne.w fu_in_exc_ovfl # yes
# here, we insert the correct fsave status value into the fsave frame for the
-# corresponding exception. the operand in the fsave frame should be the original
+# corresponding exception. the operand in the fsave frame should be the original
# src operand.
fu_in_exc_exit:
mov.l %d0,-(%sp) # save d0
@@ -1424,8 +1424,8 @@ fu_in_exc_ovfl:
bra.b fu_in_exc_exit
# If the input operand to this operation was opclass two and a single
-# or double precision denorm, inf, or nan, the operand needs to be
-# "corrected" in order to have the proper equivalent extended precision
+# or double precision denorm, inf, or nan, the operand needs to be
+# "corrected" in order to have the proper equivalent extended precision
# number.
global fix_skewed_ops
fix_skewed_ops:
@@ -1453,7 +1453,7 @@ fso_sgl_dnrm:
bsr.l norm # normalize mantissa
neg.w %d0 # -shft amt
addi.w &0x3f81,%d0 # adjust new exponent
- andi.w &0x8000,LOCAL_EX(%a0) # clear old exponent
+ andi.w &0x8000,LOCAL_EX(%a0) # clear old exponent
or.w %d0,LOCAL_EX(%a0) # insert new exponent
rts
@@ -1462,7 +1462,7 @@ fso_zero:
rts
fso_infnan:
- andi.b &0x7f,LOCAL_HI(%a0) # clear j-bit
+ andi.b &0x7f,LOCAL_HI(%a0) # clear j-bit
ori.w &0x7fff,LOCAL_EX(%a0) # make exponent = $7fff
rts
@@ -1485,7 +1485,7 @@ fso_dbl_dnrm:
bsr.l norm # normalize mantissa
neg.w %d0 # -shft amt
addi.w &0x3c01,%d0 # adjust new exponent
- andi.w &0x8000,LOCAL_EX(%a0) # clear old exponent
+ andi.w &0x8000,LOCAL_EX(%a0) # clear old exponent
or.w %d0,LOCAL_EX(%a0) # insert new exponent
rts
@@ -1537,13 +1537,13 @@ fu_out_cont:
bsr.l fout # call fmove out routine
# Exceptions in order of precedence:
-# BSUN : none
+# BSUN : none
# SNAN : none
# OPERR : fmove.{b,w,l} out of large UNNORM
# OVFL : fmove.{s,d}
# UNFL : fmove.{s,d,x}
# DZ : none
-# INEX2 : all
+# INEX2 : all
# INEX1 : none (packed doesn't travel through here)
# determine the highest priority exception(if any) set by the
@@ -1555,7 +1555,7 @@ fu_out_done:
mov.l EXC_A6(%a6),(%a6) # in case a6 changed
-# on extended precision opclass three instructions using pre-decrement or
+# on extended precision opclass three instructions using pre-decrement or
# post-increment addressing mode, the address register is not updated. is the
# address register was the stack pointer used from user mode, then let's update
# it here. if it was used from supervisor mode, then we have to handle this
@@ -1579,7 +1579,7 @@ fu_out_done_cont:
bra.l _fpsp_done
# is the ea mode pre-decrement of the stack pointer from supervisor mode?
-# ("fmov.x fpm,-(a7)") if so,
+# ("fmov.x fpm,-(a7)") if so,
fu_out_done_s:
cmpi.b SPCOND_FLG(%a6),&mda7_flg
bne.b fu_out_done_cont
@@ -1617,7 +1617,7 @@ fu_out_ena:
bfffo %d0{&24:&8},%d0 # find highest priority exception
bne.b fu_out_exc # there is at least one set
-# no exceptions were set.
+# no exceptions were set.
# if a disabled overflow occurred and inexact was enabled but the result
# was exact, then a branch to _real_inex() is made.
btst &ovfl_bit,FPSR_EXCEPT(%a6) # was overflow set?
@@ -1634,7 +1634,7 @@ fu_out_ovflchk:
# from FPIAR and put it in the trace stack frame then jump to _real_trace().
#
# UNSUPP FRAME TRACE FRAME
-# ***************** *****************
+# ***************** *****************
# * EA * * Current *
# * * * PC *
# ***************** *****************
@@ -1651,7 +1651,7 @@ fu_out_trace:
fmov.l %fpiar,0x8(%sp)
bra.l _real_trace
-# an exception occurred and that exception was enabled.
+# an exception occurred and that exception was enabled.
fu_out_exc:
subi.l &24,%d0 # fix offset to be 0-8
@@ -1663,15 +1663,15 @@ fu_out_exc:
swbeg &0x8
tbl_fu_out:
short tbl_fu_out - tbl_fu_out # BSUN can't happen
- short tbl_fu_out - tbl_fu_out # SNAN can't happen
+ short tbl_fu_out - tbl_fu_out # SNAN can't happen
short fu_operr - tbl_fu_out # OPERR
- short fu_ovfl - tbl_fu_out # OVFL
- short fu_unfl - tbl_fu_out # UNFL
+ short fu_ovfl - tbl_fu_out # OVFL
+ short fu_unfl - tbl_fu_out # UNFL
short tbl_fu_out - tbl_fu_out # DZ can't happen
- short fu_inex - tbl_fu_out # INEX2
+ short fu_inex - tbl_fu_out # INEX2
short tbl_fu_out - tbl_fu_out # INEX1 won't make it here
-# for snan,operr,ovfl,unfl, src op is still in FP_SRC so just
+# for snan,operr,ovfl,unfl, src op is still in FP_SRC so just
# frestore it.
fu_snan:
fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1
@@ -1722,7 +1722,7 @@ fu_ovfl:
# underflow can happen for extended precision. extended precision opclass
# three instruction exceptions don't update the stack pointer. so, if the
# exception occurred from user mode, then simply update a7 and exit normally.
-# if the exception occurred from supervisor mode, check if
+# if the exception occurred from supervisor mode, check if
fu_unfl:
mov.l EXC_A6(%a6),(%a6) # restore a6
@@ -1731,7 +1731,7 @@ fu_unfl:
mov.l EXC_A7(%a6),%a0 # restore a7 whether we need
mov.l %a0,%usp # to or not...
-
+
fu_unfl_cont:
fmovm.x &0x40,FP_SRC(%a6) # save EXOP to the stack
@@ -1822,7 +1822,7 @@ fu_in_pack:
bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg
-# bit five of the fp extension word separates the monadic and dyadic operations
+# bit five of the fp extension word separates the monadic and dyadic operations
# at this point
btst &0x5,1+EXC_CMDREG(%a6) # is operation monadic or dyadic?
beq.b fu_extract_p # monadic
@@ -1853,13 +1853,13 @@ fu_extract_p:
#
# Exceptions in order of precedence:
-# BSUN : none
+# BSUN : none
# SNAN : all dyadic ops
# OPERR : fsqrt(-NORM)
# OVFL : all except ftst,fcmp
# UNFL : all except ftst,fcmp
# DZ : fdiv
-# INEX2 : all except ftst,fcmp
+# INEX2 : all except ftst,fcmp
# INEX1 : all
#
@@ -1929,16 +1929,16 @@ fu_in_ena_p:
#
# No exceptions occurred that were also enabled. Now:
#
-# if (OVFL && ovfl_disabled && inexact_enabled) {
+# if (OVFL && ovfl_disabled && inexact_enabled) {
# branch to _real_inex() (even if the result was exact!);
-# } else {
+# } else {
# save the result in the proper fp reg (unless the op is fcmp or ftst);
# return;
-# }
+# }
#
btst &ovfl_bit,FPSR_EXCEPT(%a6) # was overflow set?
beq.w fu_in_cont_p # no
-
+
fu_in_ovflchk_p:
btst &inex2_bit,FPCR_ENABLE(%a6) # was inexact enabled?
beq.w fu_in_cont_p # no
@@ -1958,7 +1958,7 @@ fu_in_ovflchk_p:
# } else {
# restore exc state (SNAN||OPERR||OVFL||UNFL||DZ||INEX) into the FPU;
# }
-#
+#
fu_in_exc_p:
subi.l &24,%d0 # fix offset to be 0-8
cmpi.b %d0,&0x6 # is exception INEX? (6 or 7)
@@ -1971,7 +1971,7 @@ fu_in_exc_p:
bne.w fu_in_exc_ovfl_p # yes
# here, we insert the correct fsave status value into the fsave frame for the
-# corresponding exception. the operand in the fsave frame should be the original
+# corresponding exception. the operand in the fsave frame should be the original
# src operand.
# as a reminder for future predicted pain and agony, we are passing in fsave the
# "non-skewed" operand for cases of sgl and dbl src INFs,NANs, and DENORMs.
@@ -2034,21 +2034,21 @@ fu_in_exc_exit_s_p:
bne.b fu_trace_p # yes
bra.l _fpsp_done # exit to os
-
+
#
-# The opclass two PACKED instruction that took an "Unimplemented Data Type"
-# exception was being traced. Make the "current" PC the FPIAR and put it in the
+# The opclass two PACKED instruction that took an "Unimplemented Data Type"
+# exception was being traced. Make the "current" PC the FPIAR and put it in the
# trace stack frame then jump to _real_trace().
-#
+#
# UNSUPP FRAME TRACE FRAME
# ***************** *****************
# * EA * * Current *
# * * * PC *
# ***************** *****************
-# * 0x2 * 0x0dc * * 0x2 * 0x024 *
+# * 0x2 * 0x0dc * * 0x2 * 0x024 *
# ***************** *****************
# * Next * * Next *
-# * PC * * PC *
+# * PC * * PC *
# ***************** *****************
# * SR * * SR *
# ***************** *****************
@@ -2094,13 +2094,13 @@ fu_op2_p:
bsr.l fout # call fmove out routine
# Exceptions in order of precedence:
-# BSUN : no
+# BSUN : no
# SNAN : yes
# OPERR : if ((k_factor > +17) || (dec. exp exceeds 3 digits))
# OVFL : no
# UNFL : no
# DZ : no
-# INEX2 : yes
+# INEX2 : yes
# INEX1 : no
# determine the highest priority exception(if any) set by the
@@ -2164,7 +2164,7 @@ fu_out_ena_p:
mov.l EXC_A6(%a6),(%a6) # restore a6
-# an exception occurred and that exception was enabled.
+# an exception occurred and that exception was enabled.
# the only exception possible on packed move out are INEX, OPERR, and SNAN.
fu_out_exc_p:
cmpi.b %d0,&0x1a
@@ -2191,7 +2191,7 @@ fu_snan_s_p:
movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
mov.w &0x30d8,EXC_VOFF(%a6) # vector offset = 0xd0
- mov.w &0xe006,2+FP_SRC(%a6) # set fsave status
+ mov.w &0xe006,2+FP_SRC(%a6) # set fsave status
frestore FP_SRC(%a6) # restore src operand
@@ -2231,7 +2231,7 @@ fu_operr_p_s:
movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
mov.w &0x30d0,EXC_VOFF(%a6) # vector offset = 0xd0
- mov.w &0xe004,2+FP_SRC(%a6) # set fsave status
+ mov.w &0xe004,2+FP_SRC(%a6) # set fsave status
frestore FP_SRC(%a6) # restore src operand
@@ -2270,8 +2270,8 @@ fu_inex_s_p2:
fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
- mov.w &0x30c4,EXC_VOFF(%a6) # vector offset = 0xc4
- mov.w &0xe001,2+FP_SRC(%a6) # set fsave status
+ mov.w &0x30c4,EXC_VOFF(%a6) # vector offset = 0xc4
+ mov.w &0xe001,2+FP_SRC(%a6) # set fsave status
frestore FP_SRC(%a6) # restore src operand
@@ -2312,7 +2312,7 @@ funimp_skew_sgl:
andi.w &0x7fff,%d0 # strip sign
beq.b funimp_skew_sgl_not
cmpi.w %d0,&0x3f80
- bgt.b funimp_skew_sgl_not
+ bgt.b funimp_skew_sgl_not
neg.w %d0 # make exponent negative
addi.w &0x3f81,%d0 # find amt to shift
mov.l FP_SRC_HI(%a6),%d1 # fetch DENORM hi(man)
@@ -2329,7 +2329,7 @@ funimp_skew_dbl:
andi.w &0x7fff,%d0 # strip sign
beq.b funimp_skew_dbl_not
cmpi.w %d0,&0x3c00
- bgt.b funimp_skew_dbl_not
+ bgt.b funimp_skew_dbl_not
tst.b FP_SRC_EX(%a6) # make "internal format"
smi.b 0x2+FP_SRC(%a6)
@@ -2362,7 +2362,7 @@ _mem_write2:
#########################################################################
# XDEF **************************************************************** #
# _fpsp_effadd(): 060FPSP entry point for FP "Unimplemented #
-# effective address" exception. #
+# effective address" exception. #
# #
# This handler should be the first code executed upon taking the #
# FP Unimplemented Effective Address exception in an operating #
@@ -2387,7 +2387,7 @@ _mem_write2:
# #
# INPUT *************************************************************** #
# - The system stack contains the "Unimplemented <ea>" stk frame #
-# #
+# #
# OUTPUT ************************************************************** #
# If access error: #
# - The system stack is changed to an access error stack frame #
@@ -2408,17 +2408,17 @@ _mem_write2:
# For immediate data operations, the data is read in w/ a #
# _mem_read() "callout", converted to FP binary (if packed), and used #
# as the source operand to the instruction specified by the instruction #
-# word. If no FP exception should be reported ads a result of the #
+# word. If no FP exception should be reported ads a result of the #
# emulation, then the result is stored to the destination register and #
# the handler exits through _fpsp_done(). If an enabled exc has been #
# signalled as a result of emulation, then an fsave state frame #
# corresponding to the FP exception type must be entered into the 060 #
-# FPU before exiting. In either the enabled or disabled cases, we #
+# FPU before exiting. In either the enabled or disabled cases, we #
# must also check if a Trace exception is pending, in which case, we #
# must create a Trace exception stack frame from the current exception #
# stack frame. If no Trace is pending, we simply exit through #
# _fpsp_done(). #
-# For "fmovm.x", call the routine fmovm_dynamic() which will #
+# For "fmovm.x", call the routine fmovm_dynamic() which will #
# decode and emulate the instruction. No FP exceptions can be pending #
# as a result of this operation emulation. A Trace exception can be #
# pending, though, which means the current stack frame must be changed #
@@ -2437,11 +2437,11 @@ _mem_write2:
# before the "FPU disabled" exception, but the "FPU disabled" exception #
# has higher priority, we check the disabled bit in the PCR. If set, #
# then we must create an 8 word "FPU disabled" exception stack frame #
-# from the current 4 word exception stack frame. This includes #
-# reproducing the effective address of the instruction to put on the #
+# from the current 4 word exception stack frame. This includes #
+# reproducing the effective address of the instruction to put on the #
# new stack frame. #
# #
-# In the process of all emulation work, if a _mem_read() #
+# In the process of all emulation work, if a _mem_read() #
# "callout" returns a failing result indicating an access error, then #
# we must create an access error stack frame from the current stack #
# frame. This information includes a faulting address and a fault- #
@@ -2482,18 +2482,18 @@ _fpsp_effadd:
#
# here, we will have:
-# fabs fdabs fsabs facos fmod
+# fabs fdabs fsabs facos fmod
# fadd fdadd fsadd fasin frem
-# fcmp fatan fscale
+# fcmp fatan fscale
# fdiv fddiv fsdiv fatanh fsin
# fint fcos fsincos
# fintrz fcosh fsinh
# fmove fdmove fsmove fetox ftan
-# fmul fdmul fsmul fetoxm1 ftanh
+# fmul fdmul fsmul fetoxm1 ftanh
# fneg fdneg fsneg fgetexp ftentox
# fsgldiv fgetman ftwotox
-# fsglmul flog10
-# fsqrt flog2
+# fsglmul flog10
+# fsqrt flog2
# fsub fdsub fssub flogn
# ftst flognp1
# which can all use f<op>.{x,p}
@@ -2585,8 +2585,8 @@ iea_op_spec:
# store a result. then, only fcmp will branch back and pick up a dst operand.
st STORE_FLG(%a6) # don't store a final result
btst &0x1,1+EXC_CMDREG(%a6) # is operation fcmp?
- beq.b iea_op_loaddst # yes
-
+ beq.b iea_op_loaddst # yes
+
iea_op_extract:
clr.l %d0
mov.b FPCR_MODE(%a6),%d0 # pass: rnd mode,prec
@@ -2659,7 +2659,7 @@ iea_op_ovfl:
btst &inex2_bit,FPCR_ENABLE(%a6) # is inexact enabled?
beq.b iea_op_store # no
bra.b iea_op_exc_ovfl # yes
-
+
# an enabled exception occurred. we have to insert the exception type back into
# the machine.
iea_op_exc:
@@ -2698,7 +2698,7 @@ iea_op_exit2:
fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
- frestore FP_SRC(%a6) # restore exceptional state
+ frestore FP_SRC(%a6) # restore exceptional state
unlk %a6 # unravel the frame
@@ -2706,12 +2706,12 @@ iea_op_exit2:
bne.b iea_op_trace # yes
bra.l _fpsp_done # exit to os
-
+
#
# The opclass two instruction that took an "Unimplemented Effective Address"
# exception was being traced. Make the "current" PC the FPIAR and put it in
# the trace stack frame then jump to _real_trace().
-#
+#
# UNIMP EA FRAME TRACE FRAME
# ***************** *****************
# * 0x0 * 0x0f0 * * Current *
@@ -2744,7 +2744,7 @@ iea_fmovm_data:
iea_fmovm_data_u:
mov.l %usp,%a0
- mov.l %a0,EXC_A7(%a6) # store current a7
+ mov.l %a0,EXC_A7(%a6) # store current a7
bsr.l fmovm_dynamic # do dynamic fmovm
mov.l EXC_A7(%a6),%a0 # load possibly new a7
mov.l %a0,%usp # update usp
@@ -2775,10 +2775,10 @@ iea_fmovm_data_postinc:
lea (EXC_SR,%a6,%d0),%a0
mov.l %a0,EXC_SR(%a6)
-
+
fmovm.x EXC_FP0(%a6),&0xc0 # restore fp0-fp1
fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
- movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
+ movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
unlk %a6
mov.l (%sp)+,%sp
@@ -2792,15 +2792,15 @@ iea_fmovm_data_pi_trace:
lea (EXC_SR-0x4,%a6,%d0),%a0
mov.l %a0,EXC_SR(%a6)
-
+
fmovm.x EXC_FP0(%a6),&0xc0 # restore fp0-fp1
fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
- movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
+ movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
unlk %a6
mov.l (%sp)+,%sp
bra.l _real_trace
-
+
# right now, d1 = size and d0 = the strg.
iea_fmovm_data_predec:
mov.b %d1,EXC_VOFF(%a6) # store strg
@@ -2808,7 +2808,7 @@ iea_fmovm_data_predec:
fmovm.x EXC_FP0(%a6),&0xc0 # restore fp0-fp1
fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
- movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
+ movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
mov.l (%a6),-(%sp) # make a copy of a6
mov.l %d0,-(%sp) # save d0
@@ -2910,10 +2910,10 @@ iea_fmovm_exit:
#
# The control reg instruction that took an "Unimplemented Effective Address"
-# exception was being traced. The "Current PC" for the trace frame is the
+# exception was being traced. The "Current PC" for the trace frame is the
# PC stacked for Unimp EA. The "Next PC" is in EXC_EXTWPTR.
# After fixing the stack frame, jump to _real_trace().
-#
+#
# UNIMP EA FRAME TRACE FRAME
# ***************** *****************
# * 0x0 * 0x0f0 * * Current *
@@ -3066,7 +3066,7 @@ iea_dacc_cont:
# _fpsp_operr(): 060FPSP entry point for FP Operr exception. #
# #
# This handler should be the first code executed upon taking the #
-# FP Operand Error exception in an operating system. #
+# FP Operand Error exception in an operating system. #
# #
# XREF **************************************************************** #
# _imem_read_long() - read instruction longword #
@@ -3079,7 +3079,7 @@ iea_dacc_cont:
# INPUT *************************************************************** #
# - The system stack contains the FP Operr exception frame #
# - The fsave frame contains the source operand #
-# #
+# #
# OUTPUT ************************************************************** #
# No access error: #
# - The system stack is unchanged #
@@ -3088,16 +3088,16 @@ iea_dacc_cont:
# ALGORITHM *********************************************************** #
# In a system where the FP Operr exception is enabled, the goal #
# is to get to the handler specified at _real_operr(). But, on the 060, #
-# for opclass zero and two instruction taking this exception, the #
+# for opclass zero and two instruction taking this exception, the #
# input operand in the fsave frame may be incorrect for some cases #
# and needs to be corrected. This handler calls fix_skewed_ops() to #
# do just this and then exits through _real_operr(). #
# For opclass 3 instructions, the 060 doesn't store the default #
# operr result out to memory or data register file as it should. #
# This code must emulate the move out before finally exiting through #
-# _real_inex(). The move out, if to memory, is performed using #
+# _real_inex(). The move out, if to memory, is performed using #
# _mem_write() "callout" routines that may return a failing result. #
-# In this special case, the handler must exit through facc_out() #
+# In this special case, the handler must exit through facc_out() #
# which creates an access error stack frame from the current operr #
# stack frame. #
# #
@@ -3110,13 +3110,13 @@ _fpsp_operr:
fsave FP_SRC(%a6) # grab the "busy" frame
- movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
+ movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs
- fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
+ fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
# the FPIAR holds the "current PC" of the faulting instruction
mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6)
-
+
mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
bsr.l _imem_read_long # fetch the instruction words
@@ -3130,7 +3130,7 @@ _fpsp_operr:
# here, we simply see if the operand in the fsave frame needs to be "unskewed".
# this would be the case for opclass two operations with a source infinity or
-# denorm operand in the sgl or dbl format. NANs also become skewed, but can't
+# denorm operand in the sgl or dbl format. NANs also become skewed, but can't
# cause an operr so we don't need to check for them here.
lea FP_SRC(%a6),%a0 # pass: ptr to src op
bsr.l fix_skewed_ops # fix src op
@@ -3201,7 +3201,7 @@ tbl_operr:
short tbl_operr - tbl_operr # dbl prec shouldn't happen
short foperr_out_b - tbl_operr # byte integer
short tbl_operr - tbl_operr # packed won't enter here
-
+
foperr_out_b:
mov.b L_SCR1(%a6),%d0 # load positive default result
cmpi.b %d1,&0x7 # is <ea> mode a data reg?
@@ -3255,7 +3255,7 @@ foperr_out_l_save_dn:
# _fpsp_snan(): 060FPSP entry point for FP SNAN exception. #
# #
# This handler should be the first code executed upon taking the #
-# FP Signalling NAN exception in an operating system. #
+# FP Signalling NAN exception in an operating system. #
# #
# XREF **************************************************************** #
# _imem_read_long() - read instruction longword #
@@ -3269,7 +3269,7 @@ foperr_out_l_save_dn:
# INPUT *************************************************************** #
# - The system stack contains the FP SNAN exception frame #
# - The fsave frame contains the source operand #
-# #
+# #
# OUTPUT ************************************************************** #
# No access error: #
# - The system stack is unchanged #
@@ -3278,16 +3278,16 @@ foperr_out_l_save_dn:
# ALGORITHM *********************************************************** #
# In a system where the FP SNAN exception is enabled, the goal #
# is to get to the handler specified at _real_snan(). But, on the 060, #
-# for opclass zero and two instructions taking this exception, the #
+# for opclass zero and two instructions taking this exception, the #
# input operand in the fsave frame may be incorrect for some cases #
# and needs to be corrected. This handler calls fix_skewed_ops() to #
# do just this and then exits through _real_snan(). #
# For opclass 3 instructions, the 060 doesn't store the default #
# SNAN result out to memory or data register file as it should. #
# This code must emulate the move out before finally exiting through #
-# _real_snan(). The move out, if to memory, is performed using #
+# _real_snan(). The move out, if to memory, is performed using #
# _mem_write() "callout" routines that may return a failing result. #
-# In this special case, the handler must exit through facc_out() #
+# In this special case, the handler must exit through facc_out() #
# which creates an access error stack frame from the current SNAN #
# stack frame. #
# For the case of an extended precision opclass 3 instruction, #
@@ -3306,13 +3306,13 @@ _fpsp_snan:
fsave FP_SRC(%a6) # grab the "busy" frame
- movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
+ movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs
- fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
+ fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
# the FPIAR holds the "current PC" of the faulting instruction
mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6)
-
+
mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
bsr.l _imem_read_long # fetch the instruction words
@@ -3340,7 +3340,7 @@ fsnan_exit:
unlk %a6
bra.l _real_snan
-
+
########################################################################
#
@@ -3350,7 +3350,7 @@ fsnan_exit:
#
# byte, word, long, and packed destination format operations can pass
# through here. since packed format operations already were handled by
-# fpsp_unsupp(), then we need to do nothing else for them here.
+# fpsp_unsupp(), then we need to do nothing else for them here.
# for byte, word, and long, we simply need to test the sign of the src
# operand and save the appropriate minimum or maximum integer value
# to the effective address as pointed to by the stacked effective address.
@@ -3371,7 +3371,7 @@ tbl_snan:
short fsnan_out_d - tbl_snan # dbl prec shouldn't happen
short fsnan_out_b - tbl_snan # byte integer
short tbl_snan - tbl_snan # packed needs no help
-
+
fsnan_out_b:
mov.b FP_SRC_HI(%a6),%d0 # load upper byte of SNAN
bset &6,%d0 # set SNAN bit
@@ -3497,7 +3497,7 @@ fsnan_out_x:
mov.l %usp,%a0 # fetch user stack pointer
mov.l %a0,EXC_A7(%a6) # save on stack for calc_ea()
mov.l (%a6),EXC_A6(%a6)
-
+
bsr.l _calc_ea_fout # find the correct ea,update An
mov.l %a0,%a1
mov.l %a0,EXC_EA(%a6) # stack correct <ea>
@@ -3546,7 +3546,7 @@ fsnan_out_x_s:
mov.l LOCAL_SIZE+FP_SCR0_LO(%sp),LOCAL_SIZE+EXC_EA(%sp)
add.l &LOCAL_SIZE-0x8,%sp
-
+
bra.l _real_snan
#########################################################################
@@ -3554,7 +3554,7 @@ fsnan_out_x_s:
# _fpsp_inex(): 060FPSP entry point for FP Inexact exception. #
# #
# This handler should be the first code executed upon taking the #
-# FP Inexact exception in an operating system. #
+# FP Inexact exception in an operating system. #
# #
# XREF **************************************************************** #
# _imem_read_long() - read instruction longword #
@@ -3571,7 +3571,7 @@ fsnan_out_x_s:
# INPUT *************************************************************** #
# - The system stack contains the FP Inexact exception frame #
# - The fsave frame contains the source operand #
-# #
+# #
# OUTPUT ************************************************************** #
# - The system stack is unchanged #
# - The fsave frame contains the adjusted src op for opclass 0,2 #
@@ -3579,10 +3579,10 @@ fsnan_out_x_s:
# ALGORITHM *********************************************************** #
# In a system where the FP Inexact exception is enabled, the goal #
# is to get to the handler specified at _real_inex(). But, on the 060, #
-# for opclass zero and two instruction taking this exception, the #
+# for opclass zero and two instruction taking this exception, the #
# hardware doesn't store the correct result to the destination FP #
-# register as did the '040 and '881/2. This handler must emulate the #
-# instruction in order to get this value and then store it to the #
+# register as did the '040 and '881/2. This handler must emulate the #
+# instruction in order to get this value and then store it to the #
# correct register before calling _real_inex(). #
# For opclass 3 instructions, the 060 doesn't store the default #
# inexact result out to memory or data register file as it should. #
@@ -3598,13 +3598,13 @@ _fpsp_inex:
fsave FP_SRC(%a6) # grab the "busy" frame
- movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
+ movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs
- fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
+ fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
# the FPIAR holds the "current PC" of the faulting instruction
mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6)
-
+
mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
bsr.l _imem_read_long # fetch the instruction words
@@ -3616,7 +3616,7 @@ _fpsp_inex:
bne.w finex_out # fmove out
-# the hardware, for "fabs" and "fneg" w/ a long source format, puts the
+# the hardware, for "fabs" and "fneg" w/ a long source format, puts the
# longword integer directly into the upper longword of the mantissa along
# w/ an exponent value of 0x401e. we convert this to extended precision here.
bfextu %d0{&19:&3},%d0 # fetch instr size
@@ -3750,7 +3750,7 @@ finex_out:
# INPUT *************************************************************** #
# - The system stack contains the FP DZ exception stack. #
# - The fsave frame contains the source operand. #
-# #
+# #
# OUTPUT ************************************************************** #
# - The system stack contains the FP DZ exception stack. #
# - The fsave frame contains the adjusted source operand. #
@@ -3761,7 +3761,7 @@ finex_out:
# exception is taken, the input operand in the fsave state frame may #
# be incorrect for some cases and need to be adjusted. So, this package #
# adjusts the operand using fix_skewed_ops() and then branches to #
-# _real_dz(). #
+# _real_dz(). #
# #
#########################################################################
@@ -3772,13 +3772,13 @@ _fpsp_dz:
fsave FP_SRC(%a6) # grab the "busy" frame
- movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
+ movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs
- fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
+ fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
# the FPIAR holds the "current PC" of the faulting instruction
mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6)
-
+
mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
bsr.l _imem_read_long # fetch the instruction words
@@ -3819,7 +3819,7 @@ fdz_exit:
# INPUT *************************************************************** #
# - The system stack contains a "Line F Emulator" exception #
# stack frame. #
-# #
+# #
# OUTPUT ************************************************************** #
# - The system stack is unchanged #
# #
@@ -3830,7 +3830,7 @@ fdz_exit:
# (2) FPU disabled (8 word stack frame) #
# (3) Line F (4 word stack frame) #
# #
-# This module determines which and forks the flow off to the #
+# This module determines which and forks the flow off to the #
# appropriate "callout" (for "disabled" and "Line F") or to the #
# correct emulation code (for "FPU unimplemented"). #
# This code also must check for "fmovecr" instructions w/ a #
@@ -3943,11 +3943,11 @@ fline_fline:
# _fdbcc() - emulate an "fdbcc" instruction #
# _fscc() - emulate an "fscc" instruction #
# _real_trap() - "callout" for Trap exception #
-# _real_bsun() - "callout" for enabled Bsun exception #
+# _real_bsun() - "callout" for enabled Bsun exception #
# #
# INPUT *************************************************************** #
# - The system stack contains the "Unimplemented Instr" stk frame #
-# #
+# #
# OUTPUT ************************************************************** #
# If access error: #
# - The system stack is changed to an access error stack frame #
@@ -3962,21 +3962,21 @@ fline_fline:
# unimplemented on the 040, and (2) "ftrapcc", "fscc", and "fdbcc". #
# For the first set, this handler calls the routine load_fop() #
# to load the source and destination (for dyadic) operands to be used #
-# for instruction emulation. The correct emulation routine is then #
-# chosen by decoding the instruction type and indexing into an #
-# emulation subroutine index table. After emulation returns, this #
+# for instruction emulation. The correct emulation routine is then #
+# chosen by decoding the instruction type and indexing into an #
+# emulation subroutine index table. After emulation returns, this #
# handler checks to see if an exception should occur as a result of the #
# FP instruction emulation. If so, then an FP exception of the correct #
# type is inserted into the FPU state frame using the "frestore" #
-# instruction before exiting through _fpsp_done(). In either the #
+# instruction before exiting through _fpsp_done(). In either the #
# exceptional or non-exceptional cases, we must check to see if the #
# Trace exception is enabled. If so, then we must create a Trace #
# exception frame from the current exception frame and exit through #
# _real_trace(). #
-# For "fdbcc", "ftrapcc", and "fscc", the emulation subroutines #
+# For "fdbcc", "ftrapcc", and "fscc", the emulation subroutines #
# _fdbcc(), _ftrapcc(), and _fscc() respectively are used. All three #
-# may flag that a BSUN exception should be taken. If so, then the #
-# current exception stack frame is converted into a BSUN exception #
+# may flag that a BSUN exception should be taken. If so, then the #
+# current exception stack frame is converted into a BSUN exception #
# stack frame and an exit is made through _real_bsun(). If the #
# instruction was "ftrapcc" and a Trap exception should result, a Trap #
# exception stack frame is created from the current frame and an exit #
@@ -3985,7 +3985,7 @@ fline_fline:
# is made to _real_trace(). Finally, if none of these conditions exist, #
# then the handler exits though the callout _fpsp_done(). #
# #
-# In any of the above scenarios, if a _mem_read() or _mem_write() #
+# In any of the above scenarios, if a _mem_read() or _mem_write() #
# "callout" returns a failing value, then an access error stack frame #
# is created from the current stack frame and an exit is made through #
# _real_access(). #
@@ -4077,7 +4077,7 @@ funimp_gen:
beq.w funimp_fmovcr # yes
funimp_gen_op:
- bsr.l _load_fop # load
+ bsr.l _load_fop # load
clr.l %d0
mov.b FPCR_MODE(%a6),%d0 # fetch rnd mode
@@ -4104,7 +4104,7 @@ funimp_store:
funimp_gen_exit:
fmovm.x EXC_FP0(%a6),&0xc0 # restore fp0-fp1
fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
- movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
+ movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
funimp_gen_exit_cmp:
cmpi.b SPCOND_FLG(%a6),&mia7_flg # was the ea mode (sp)+ ?
@@ -4129,7 +4129,7 @@ funimp_gen_exit_cont2:
frestore (%sp)+
mov.w &0x2024,0x6(%sp) # stk fmt = 0x2; voff = 0x24
bra.l _real_trace
-
+
funimp_gen_exit_a7:
btst &0x5,EXC_SR(%a6) # supervisor or user mode?
bne.b funimp_gen_exit_a7_s # supervisor
@@ -4156,7 +4156,7 @@ funimp_gen_exit_a7_s:
unlk %a6
add.w (%sp),%sp # stack frame shifted
- bra.b funimp_gen_exit_cont2
+ bra.b funimp_gen_exit_cont2
######################
# fmovecr.x #ccc,fpn #
@@ -4212,7 +4212,7 @@ funimp_exc:
btst &unfl_bit,FPSR_EXCEPT(%a6) # did underflow occur?
bne.b funimp_exc_unfl # yes
-# force the fsave exception status bits to signal an exception of the
+# force the fsave exception status bits to signal an exception of the
# appropriate type. don't forget to "skew" the source operand in case we
# "unskewed" the one the hardware initially gave us.
funimp_exc_force:
@@ -4242,7 +4242,7 @@ funimp_exc_unfl:
funimp_gen_exit2:
fmovm.x EXC_FP0(%a6),&0xc0 # restore fp0-fp1
fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
- movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
+ movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
frestore FP_SRC(%a6) # insert exceptional status
@@ -4262,7 +4262,7 @@ funimp_misc:
beq.w funimp_fdbcc # yes
cmpi.b %d1,&0x7 # is it an fs<cc>?
bne.w funimp_fscc # yes
- bfextu %d0{&13:&3},%d1
+ bfextu %d0{&13:&3},%d1
cmpi.b %d1,&0x2 # is it an fs<cc>?
blt.w funimp_fscc # yes
@@ -4302,7 +4302,7 @@ funimp_ftrapcc_tp:
fmovm.x EXC_FP0(%a6),&0xc0 # restore fp0-fp1
fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
- movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
+ movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
unlk %a6
bra.l _real_trap
@@ -4346,7 +4346,7 @@ funimp_fscc:
funimp_fscc_u:
mov.l EXC_A7(%a6),%a0 # yes; set new USP
mov.l %a0,%usp
- bra.w funimp_done # branch to finish
+ bra.w funimp_done # branch to finish
# remember, I'm assuming that post-increment is bogus...(it IS!!!)
# so, the least significant WORD of the stacked effective address got
@@ -4361,7 +4361,7 @@ funimp_fscc_s:
fmovm.x EXC_FP0(%a6),&0xc0 # restore fp0-fp1
fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
- movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
+ movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
unlk %a6
@@ -4381,7 +4381,7 @@ funimp_fscc_s_trace:
fmov.l %fpiar,0x8(%sp) # insert "current PC"
bra.l _real_trace
-
+
#
# The ftrap<cc>, fs<cc>, or fdb<cc> is to take an enabled bsun. we must convert
# the fp unimplemented instruction exception stack frame into a bsun stack frame,
@@ -4409,7 +4409,7 @@ funimp_bsun:
fmovm.x EXC_FP0(%a6),&0xc0 # restore fp0-fp1
fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
- movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
+ movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
frestore FP_SRC(%a6) # restore bsun exception
@@ -4424,13 +4424,13 @@ funimp_bsun:
# and return.
#
# as usual, we have to check for trace mode being on here. since instructions
-# modifying the supervisor stack frame don't pass through here, this is a
+# modifying the supervisor stack frame don't pass through here, this is a
# relatively easy task.
#
funimp_done:
fmovm.x EXC_FP0(%a6),&0xc0 # restore fp0-fp1
fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
- movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
+ movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
unlk %a6
@@ -4465,16 +4465,16 @@ funimp_trace:
global tbl_trans
swbeg &0x1c0
tbl_trans:
- short tbl_trans - tbl_trans # $00-0 fmovecr all
- short tbl_trans - tbl_trans # $00-1 fmovecr all
- short tbl_trans - tbl_trans # $00-2 fmovecr all
- short tbl_trans - tbl_trans # $00-3 fmovecr all
- short tbl_trans - tbl_trans # $00-4 fmovecr all
- short tbl_trans - tbl_trans # $00-5 fmovecr all
- short tbl_trans - tbl_trans # $00-6 fmovecr all
- short tbl_trans - tbl_trans # $00-7 fmovecr all
+ short tbl_trans - tbl_trans # $00-0 fmovecr all
+ short tbl_trans - tbl_trans # $00-1 fmovecr all
+ short tbl_trans - tbl_trans # $00-2 fmovecr all
+ short tbl_trans - tbl_trans # $00-3 fmovecr all
+ short tbl_trans - tbl_trans # $00-4 fmovecr all
+ short tbl_trans - tbl_trans # $00-5 fmovecr all
+ short tbl_trans - tbl_trans # $00-6 fmovecr all
+ short tbl_trans - tbl_trans # $00-7 fmovecr all
- short tbl_trans - tbl_trans # $01-0 fint norm
+ short tbl_trans - tbl_trans # $01-0 fint norm
short tbl_trans - tbl_trans # $01-1 fint zero
short tbl_trans - tbl_trans # $01-2 fint inf
short tbl_trans - tbl_trans # $01-3 fint qnan
@@ -4599,7 +4599,7 @@ tbl_trans:
short src_snan - tbl_trans # $0e-4 fsin snan
short tbl_trans - tbl_trans # $0e-6 fsin unnorm
short tbl_trans - tbl_trans # $0e-7 ERROR
-
+
short stan - tbl_trans # $0f-0 ftan norm
short src_zero - tbl_trans # $0f-1 ftan zero
short t_operr - tbl_trans # $0f-2 ftan inf
@@ -5009,7 +5009,7 @@ funimp_iacc_end:
# d0 = round precision,mode #
# #
# OUTPUT ************************************************************** #
-# fp0 = sin(X) or cos(X) #
+# fp0 = sin(X) or cos(X) #
# #
# For ssincos(X): #
# fp0 = sin(X) #
@@ -5017,7 +5017,7 @@ funimp_iacc_end:
# #
# ACCURACY and MONOTONICITY ******************************************* #
# The returned result is within 1 ulp in 64 significant bit, i.e. #
-# within 0.5001 ulp to 53 bits if the result is subsequently #
+# within 0.5001 ulp to 53 bits if the result is subsequently #
# rounded to double precision. The result is provably monotonic #
# in double precision. #
# #
@@ -5034,8 +5034,8 @@ funimp_iacc_end:
# #
# 4. If k is even, go to 6. #
# #
-# 5. (k is odd) Set j := (k-1)/2, sgn := (-1)**j. #
-# Return sgn*cos(r) where cos(r) is approximated by an #
+# 5. (k is odd) Set j := (k-1)/2, sgn := (-1)**j. #
+# Return sgn*cos(r) where cos(r) is approximated by an #
# even polynomial in r, 1 + r*r*(B1+s*(B2+ ... + s*B8)), #
# s = r*r. #
# Exit. #
@@ -5047,10 +5047,10 @@ funimp_iacc_end:
# #
# 7. If |X| > 1, go to 9. #
# #
-# 8. (|X|<2**(-40)) If SIN is invoked, return X; #
+# 8. (|X|<2**(-40)) If SIN is invoked, return X; #
# otherwise return 1. #
# #
-# 9. Overwrite X by X := X rem 2Pi. Now that |X| <= Pi, #
+# 9. Overwrite X by X := X rem 2Pi. Now that |X| <= Pi, #
# go back to 3. #
# #
# SINCOS: #
@@ -5065,19 +5065,19 @@ funimp_iacc_end:
# j1 exclusive or with the l.s.b. of k. #
# sgn1 := (-1)**j1, sgn2 := (-1)**j2. #
# SIN(X) = sgn1 * cos(r) and COS(X) = sgn2*sin(r) where #
-# sin(r) and cos(r) are computed as odd and even #
+# sin(r) and cos(r) are computed as odd and even #
# polynomials in r, respectively. Exit #
# #
# 5. (k is even) Set j1 := k/2, sgn1 := (-1)**j1. #
# SIN(X) = sgn1 * sin(r) and COS(X) = sgn1*cos(r) where #
-# sin(r) and cos(r) are computed as odd and even #
+# sin(r) and cos(r) are computed as odd and even #
# polynomials in r, respectively. Exit #
# #
# 6. If |X| > 1, go to 8. #
# #
# 7. (|X|<2**(-40)) SIN(X) = X and COS(X) = 1. Exit. #
# #
-# 8. Overwrite X by X := X rem 2Pi. Now that |X| <= Pi, #
+# 8. Overwrite X by X := X rem 2Pi. Now that |X| <= Pi, #
# go back to 2. #
# #
#########################################################################
@@ -5152,9 +5152,9 @@ SOK1:
#--THE ARGUMENT REDUCTION IS DONE BY TABLE LOOK UP.
SINMAIN:
fmov.x %fp0,%fp1
- fmul.d TWOBYPI(%pc),%fp1 # X*2/PI
+ fmul.d TWOBYPI(%pc),%fp1 # X*2/PI
- lea PITBL+0x200(%pc),%a1 # TABLE OF N*PI/2, N = -32,...,32
+ lea PITBL+0x200(%pc),%a1 # TABLE OF N*PI/2, N = -32,...,32
fmov.l %fp1,INT(%a6) # CONVERT TO INTEGER
@@ -5164,8 +5164,8 @@ SINMAIN:
# A1 IS THE ADDRESS OF N*PIBY2
# ...WHICH IS IN TWO PIECES Y1 & Y2
- fsub.x (%a1)+,%fp0 # X-Y1
- fsub.s (%a1),%fp0 # fp0 = R = (X-Y1)-Y2
+ fsub.x (%a1)+,%fp0 # X-Y1
+ fsub.s (%a1),%fp0 # fp0 = R = (X-Y1)-Y2
SINCONT:
#--continuation from REDUCEX
@@ -5319,7 +5319,7 @@ SINTINY:
COSTINY:
fmov.s &0x3F800000,%fp0 # fp0 = 1.0
fmov.l %d0,%fpcr # restore users round mode,prec
- fadd.s &0x80800000,%fp0 # last inst - possible exception set
+ fadd.s &0x80800000,%fp0 # last inst - possible exception set
bra t_pinx2
################################################
@@ -5751,7 +5751,7 @@ SRESTORE:
# #
# 7. (|X|<2**(-40)) Tan(X) = X. Exit. #
# #
-# 8. Overwrite X by X := X rem 2Pi. Now that |X| <= Pi, go back #
+# 8. Overwrite X by X := X rem 2Pi. Now that |X| <= Pi, go back #
# to 2. #
# #
#########################################################################
@@ -6154,27 +6154,27 @@ RESTORE:
# The returned result is within 2 ulps in 64 significant bit, #
# i.e. within 0.5001 ulp to 53 bits if the result is subsequently #
# rounded to double precision. The result is provably monotonic #
-# in double precision. #
+# in double precision. #
# #
# ALGORITHM *********************************************************** #
# Step 1. If |X| >= 16 or |X| < 1/16, go to Step 5. #
# #
-# Step 2. Let X = sgn * 2**k * 1.xxxxxxxx...x. #
+# Step 2. Let X = sgn * 2**k * 1.xxxxxxxx...x. #
# Note that k = -4, -3,..., or 3. #
-# Define F = sgn * 2**k * 1.xxxx1, i.e. the first 5 #
+# Define F = sgn * 2**k * 1.xxxx1, i.e. the first 5 #
# significant bits of X with a bit-1 attached at the 6-th #
# bit position. Define u to be u = (X-F) / (1 + X*F). #
# #
# Step 3. Approximate arctan(u) by a polynomial poly. #
# #
-# Step 4. Return arctan(F) + poly, arctan(F) is fetched from a #
+# Step 4. Return arctan(F) + poly, arctan(F) is fetched from a #
# table of values calculated beforehand. Exit. #
# #
# Step 5. If |X| >= 16, go to Step 7. #
# #
# Step 6. Approximate arctan(X) by an odd polynomial in X. Exit. #
# #
-# Step 7. Define X' = -1/X. Approximate arctan(X') by an odd #
+# Step 7. Define X' = -1/X. Approximate arctan(X') by an odd #
# polynomial in X'. #
# Arctan(X) = sign(X)*Pi/2 + arctan(X'). Exit. #
# #
@@ -6440,7 +6440,7 @@ ATANMAIN:
fmul.x %fp2,%fp1 # A1*U*V*(A2+V*(A3+V))
fadd.x %fp1,%fp0 # ATAN(U), FP1 RELEASED
- fmovm.x (%sp)+,&0x20 # restore fp2
+ fmovm.x (%sp)+,&0x20 # restore fp2
fmov.l %d0,%fpcr # restore users rnd mode,prec
fadd.x ATANF(%a6),%fp0 # ATAN(X)
@@ -6597,7 +6597,7 @@ satand:
# a0 = pointer to extended precision input #
# d0 = round precision,mode #
# #
-# OUTPUT ************************************************************** #
+# OUTPUT ************************************************************** #
# fp0 = arcsin(X) #
# #
# ACCURACY and MONOTONICITY ******************************************* #
@@ -6637,7 +6637,7 @@ sasin:
# This catch is added here for the '060 QSP. Originally, the call to
# satan() would handle this case by causing the exception which would
-# not be caught until gen_except(). Now, with the exceptions being
+# not be caught until gen_except(). Now, with the exceptions being
# detected inside of satan(), the exception would have been handled there
# instead of inside sasin() as expected.
cmp.l %d1,&0x3FD78000
@@ -6786,7 +6786,7 @@ sacosd:
#########################################################################
# setox(): computes the exponential for a normalized input #
-# setoxd(): computes the exponential for a denormalized input #
+# setoxd(): computes the exponential for a denormalized input #
# setoxm1(): computes the exponential minus 1 for a normalized input #
# setoxm1d(): computes the exponential minus 1 for a denormalized input #
# #
@@ -6798,9 +6798,9 @@ sacosd:
# fp0 = exp(X) or exp(X)-1 #
# #
# ACCURACY and MONOTONICITY ******************************************* #
-# The returned result is within 0.85 ulps in 64 significant bit, #
+# The returned result is within 0.85 ulps in 64 significant bit, #
# i.e. within 0.5001 ulp to 53 bits if the result is subsequently #
-# rounded to double precision. The result is provably monotonic #
+# rounded to double precision. The result is provably monotonic #
# in double precision. #
# #
# ALGORITHM and IMPLEMENTATION **************************************** #
@@ -6824,14 +6824,14 @@ sacosd:
# Notes: The usual case should take the branches 1.1 -> 1.3 -> 2.#
# To avoid the use of floating-point comparisons, a #
# compact representation of |X| is used. This format is a #
-# 32-bit integer, the upper (more significant) 16 bits #
-# are the sign and biased exponent field of |X|; the #
+# 32-bit integer, the upper (more significant) 16 bits #
+# are the sign and biased exponent field of |X|; the #
# lower 16 bits are the 16 most significant fraction #
# (including the explicit bit) bits of |X|. Consequently, #
# the comparisons in Steps 1.1 and 1.3 can be performed #
# by integer comparison. Note also that the constant #
# 16380 log(2) used in Step 1.3 is also in the compact #
-# form. Thus taking the branch to Step 2 guarantees #
+# form. Thus taking the branch to Step 2 guarantees #
# |X| < 16380 log(2). There is no harm to have a small #
# number of cases where |X| is less than, but close to, #
# 16380 log(2) and the branch to Step 9 is taken. #
@@ -6843,7 +6843,7 @@ sacosd:
# 2.3 Calculate J = N mod 64; so J = 0,1,2,..., #
# or 63. #
# 2.4 Calculate M = (N - J)/64; so N = 64M + J. #
-# 2.5 Calculate the address of the stored value of #
+# 2.5 Calculate the address of the stored value of #
# 2^(J/64). #
# 2.6 Create the value Scale = 2^M. #
# Notes: The calculation in 2.2 is really performed by #
@@ -6852,26 +6852,26 @@ sacosd:
# where #
# constant := single-precision( 64/log 2 ). #
# #
-# Using a single-precision constant avoids memory #
+# Using a single-precision constant avoids memory #
# access. Another effect of using a single-precision #
-# "constant" is that the calculated value Z is #
+# "constant" is that the calculated value Z is #
# #
# Z = X*(64/log2)*(1+eps), |eps| <= 2^(-24). #
# #
# This error has to be considered later in Steps 3 and 4. #
# #
# Step 3. Calculate X - N*log2/64. #
-# 3.1 R := X + N*L1, #
+# 3.1 R := X + N*L1, #
# where L1 := single-precision(-log2/64). #
-# 3.2 R := R + N*L2, #
+# 3.2 R := R + N*L2, #
# L2 := extended-precision(-log2/64 - L1).#
-# Notes: a) The way L1 and L2 are chosen ensures L1+L2 #
+# Notes: a) The way L1 and L2 are chosen ensures L1+L2 #
# approximate the value -log2/64 to 88 bits of accuracy. #
# b) N*L1 is exact because N is no longer than 22 bits #
# and L1 is no longer than 24 bits. #
-# c) The calculation X+N*L1 is also exact due to #
+# c) The calculation X+N*L1 is also exact due to #
# cancellation. Thus, R is practically X+N(L1+L2) to full #
-# 64 bits. #
+# 64 bits. #
# d) It is important to estimate how large can |R| be #
# after Step 3.2. #
# #
@@ -6889,11 +6889,11 @@ sacosd:
# #
# Step 4. Approximate exp(R)-1 by a polynomial #
# p = R + R*R*(A1 + R*(A2 + R*(A3 + R*(A4 + R*A5)))) #
-# Notes: a) In order to reduce memory access, the coefficients #
+# Notes: a) In order to reduce memory access, the coefficients #
# are made as "short" as possible: A1 (which is 1/2), A4 #
# and A5 are single precision; A2 and A3 are double #
-# precision. #
-# b) Even with the restrictions above, #
+# precision. #
+# b) Even with the restrictions above, #
# |p - (exp(R)-1)| < 2^(-68.8) for all |R| <= 0.0062. #
# Note that 0.0062 is slightly bigger than 0.57 log2/64. #
# c) To fully utilize the pipeline, p is separated into #
@@ -6907,11 +6907,11 @@ sacosd:
# where T and t are the stored values for 2^(J/64). #
# Notes: 2^(J/64) is stored as T and t where T+t approximates #
# 2^(J/64) to roughly 85 bits; T is in extended precision #
-# and t is in single precision. Note also that T is #
-# rounded to 62 bits so that the last two bits of T are #
-# zero. The reason for such a special form is that T-1, #
+# and t is in single precision. Note also that T is #
+# rounded to 62 bits so that the last two bits of T are #
+# zero. The reason for such a special form is that T-1, #
# T-2, and T-8 will all be exact --- a property that will #
-# give much more accurate computation of the function #
+# give much more accurate computation of the function #
# EXPM1. #
# #
# Step 6. Reconstruction of exp(X) #
@@ -6927,11 +6927,11 @@ sacosd:
# X = (M1+M)log2 + Jlog2/64 + R, |M1+M| >= 16380. #
# Hence, exp(X) may overflow or underflow or neither. #
# When that is the case, AdjScale = 2^(M1) where M1 is #
-# approximately M. Thus 6.2 will never cause #
+# approximately M. Thus 6.2 will never cause #
# over/underflow. Possible exception in 6.4 is overflow #
# or underflow. The inexact exception is not generated in #
# 6.4. Although one can argue that the inexact flag #
-# should always be raised, to simulate that exception #
+# should always be raised, to simulate that exception #
# cost to much than the flag is worth in practical uses. #
# #
# Step 7. Return 1 + X. #
@@ -6944,7 +6944,7 @@ sacosd:
# in Step 7.1 to avoid unnecessary trapping. (Although #
# the FMOVEM may not seem relevant since X is normalized, #
# the precaution will be useful in the library version of #
-# this code where the separate entry for denormalized #
+# this code where the separate entry for denormalized #
# inputs will be done away with.) #
# #
# Step 8. Handle exp(X) where |X| >= 16380log2. #
@@ -6952,9 +6952,9 @@ sacosd:
# (mimic 2.2 - 2.6) #
# 8.2 N := round-to-integer( X * 64/log2 ) #
# 8.3 Calculate J = N mod 64, J = 0,1,...,63 #
-# 8.4 K := (N-J)/64, M1 := truncate(K/2), M = K-M1, #
+# 8.4 K := (N-J)/64, M1 := truncate(K/2), M = K-M1, #
# AdjFlag := 1. #
-# 8.5 Calculate the address of the stored value #
+# 8.5 Calculate the address of the stored value #
# 2^(J/64). #
# 8.6 Create the values Scale = 2^M, AdjScale = 2^M1. #
# 8.7 Go to Step 3. #
@@ -6991,8 +6991,8 @@ sacosd:
# 1.4 Go to Step 10. #
# Notes: The usual case should take the branches 1.1 -> 1.3 -> 2.#
# However, it is conceivable |X| can be small very often #
-# because EXPM1 is intended to evaluate exp(X)-1 #
-# accurately when |X| is small. For further details on #
+# because EXPM1 is intended to evaluate exp(X)-1 #
+# accurately when |X| is small. For further details on #
# the comparisons, see the notes on Step 1 of setox. #
# #
# Step 2. Calculate N = round-to-nearest-int( X * 64/log2 ). #
@@ -7000,16 +7000,16 @@ sacosd:
# 2.2 Calculate J = N mod 64; so J = 0,1,2,..., #
# or 63. #
# 2.3 Calculate M = (N - J)/64; so N = 64M + J. #
-# 2.4 Calculate the address of the stored value of #
+# 2.4 Calculate the address of the stored value of #
# 2^(J/64). #
-# 2.5 Create the values Sc = 2^M and #
+# 2.5 Create the values Sc = 2^M and #
# OnebySc := -2^(-M). #
# Notes: See the notes on Step 2 of setox. #
# #
# Step 3. Calculate X - N*log2/64. #
-# 3.1 R := X + N*L1, #
+# 3.1 R := X + N*L1, #
# where L1 := single-precision(-log2/64). #
-# 3.2 R := R + N*L2, #
+# 3.2 R := R + N*L2, #
# L2 := extended-precision(-log2/64 - L1).#
# Notes: Applying the analysis of Step 3 of setox in this case #
# shows that |R| <= 0.0055 (note that |X| <= 70 log2 in #
@@ -7017,10 +7017,10 @@ sacosd:
# #
# Step 4. Approximate exp(R)-1 by a polynomial #
# p = R+R*R*(A1+R*(A2+R*(A3+R*(A4+R*(A5+R*A6))))) #
-# Notes: a) In order to reduce memory access, the coefficients #
-# are made as "short" as possible: A1 (which is 1/2), A5 #
-# and A6 are single precision; A2, A3 and A4 are double #
-# precision. #
+# Notes: a) In order to reduce memory access, the coefficients #
+# are made as "short" as possible: A1 (which is 1/2), A5 #
+# and A6 are single precision; A2, A3 and A4 are double #
+# precision. #
# b) Even with the restriction above, #
# |p - (exp(R)-1)| < |R| * 2^(-72.7) #
# for all |R| <= 0.0055. #
@@ -7035,9 +7035,9 @@ sacosd:
# where T and t are the stored values for 2^(J/64). #
# Notes: 2^(J/64) is stored as T and t where T+t approximates #
# 2^(J/64) to roughly 85 bits; T is in extended precision #
-# and t is in single precision. Note also that T is #
-# rounded to 62 bits so that the last two bits of T are #
-# zero. The reason for such a special form is that T-1, #
+# and t is in single precision. Note also that T is #
+# rounded to 62 bits so that the last two bits of T are #
+# zero. The reason for such a special form is that T-1, #
# T-2, and T-8 will all be exact --- a property that will #
# be exploited in Step 6 below. The total relative error #
# in p is no bigger than 2^(-67.7) compared to the final #
@@ -7052,7 +7052,7 @@ sacosd:
# 6.5 ans := (T + OnebySc) + (p + t). #
# 6.6 Restore user FPCR. #
# 6.7 Return ans := Sc * ans. Exit. #
-# Notes: The various arrangements of the expressions give #
+# Notes: The various arrangements of the expressions give #
# accurate evaluations. #
# #
# Step 7. exp(X)-1 for |X| < 1/4. #
@@ -7068,8 +7068,8 @@ sacosd:
# Return ans := ans*2^(140). Exit #
# Notes: The idea is to return "X - tiny" under the user #
# precision and rounding modes. To avoid unnecessary #
-# inefficiency, we stay away from denormalized numbers #
-# the best we can. For |X| >= 2^(-16312), the #
+# inefficiency, we stay away from denormalized numbers #
+# the best we can. For |X| >= 2^(-16312), the #
# straightforward 8.2 generates the inexact exception as #
# the case warrants. #
# #
@@ -7077,13 +7077,13 @@ sacosd:
# p = X + X*X*(B1 + X*(B2 + ... + X*B12)) #
# Notes: a) In order to reduce memory access, the coefficients #
# are made as "short" as possible: B1 (which is 1/2), B9 #
-# to B12 are single precision; B3 to B8 are double #
+# to B12 are single precision; B3 to B8 are double #
# precision; and B2 is double extended. #
# b) Even with the restriction above, #
# |p - (exp(X)-1)| < |X| 2^(-70.6) #
# for all |X| <= 0.251. #
# Note that 0.251 is slightly bigger than 1/4. #
-# c) To fully preserve accuracy, the polynomial is #
+# c) To fully preserve accuracy, the polynomial is #
# computed as #
# X + ( S*B1 + Q ) where S = X*X and #
# Q = X*S*(B2 + X*(B3 + ... + X*B12)) #
@@ -7093,11 +7093,11 @@ sacosd:
# [ S*S*(B3 + S*(B5 + ... + S*B11)) ] #
# #
# Step 10. Calculate exp(X)-1 for |X| >= 70 log 2. #
-# 10.1 If X >= 70log2 , exp(X) - 1 = exp(X) for all #
+# 10.1 If X >= 70log2 , exp(X) - 1 = exp(X) for all #
# practical purposes. Therefore, go to Step 1 of setox. #
# 10.2 If X <= -70log2, exp(X) - 1 = -1 for all practical #
-# purposes. #
-# ans := -1 #
+# purposes. #
+# ans := -1 #
# Restore user FPCR #
# Return ans := ans + 2^(-126). Exit. #
# Notes: 10.2 will always create an inexact and return -1 + tiny #
@@ -7602,10 +7602,10 @@ setoxm1d:
# sgetexp(): returns the exponent portion of the input argument. #
# The exponent bias is removed and the exponent value is #
# returned as an extended precision number in fp0. #
-# sgetexpd(): handles denormalized numbers. #
+# sgetexpd(): handles denormalized numbers. #
# #
-# sgetman(): extracts the mantissa of the input argument. The #
-# mantissa is converted to an extended precision number w/ #
+# sgetman(): extracts the mantissa of the input argument. The #
+# mantissa is converted to an extended precision number w/ #
# an exponent of $3fff and is returned in fp0. The range of #
# the result is [1.0 - 2.0). #
# sgetmand(): handles denormalized numbers. #
@@ -7679,9 +7679,9 @@ sgetmand:
# fp0 = cosh(X) #
# #
# ACCURACY and MONOTONICITY ******************************************* #
-# The returned result is within 3 ulps in 64 significant bit, #
+# The returned result is within 3 ulps in 64 significant bit, #
# i.e. within 0.5001 ulp to 53 bits if the result is subsequently #
-# rounded to double precision. The result is provably monotonic #
+# rounded to double precision. The result is provably monotonic #
# in double precision. #
# #
# ALGORITHM *********************************************************** #
@@ -7698,7 +7698,7 @@ sgetmand:
# #
# 4. (16380 log2 < |X| <= 16480 log2) #
# cosh(X) = sign(X) * exp(|X|)/2. #
-# However, invoking exp(|X|) may cause premature #
+# However, invoking exp(|X|) may cause premature #
# overflow. Thus, we calculate sinh(X) as follows: #
# Y := |X| #
# Fact := 2**(16380) #
@@ -7793,7 +7793,7 @@ scoshd:
# fp0 = sinh(X) #
# #
# ACCURACY and MONOTONICITY ******************************************* #
-# The returned result is within 3 ulps in 64 significant bit, #
+# The returned result is within 3 ulps in 64 significant bit, #
# i.e. within 0.5001 ulp to 53 bits if the result is subsequently #
# rounded to double precision. The result is provably monotonic #
# in double precision. #
@@ -7911,7 +7911,7 @@ ssinhd:
# fp0 = tanh(X) #
# #
# ACCURACY and MONOTONICITY ******************************************* #
-# The returned result is within 3 ulps in 64 significant bit, #
+# The returned result is within 3 ulps in 64 significant bit, #
# i.e. within 0.5001 ulp to 53 bits if the result is subsequently #
# rounded to double precision. The result is provably monotonic #
# in double precision. #
@@ -8077,51 +8077,51 @@ stanhd:
# fp0 = log(X) or log(1+X) #
# #
# ACCURACY and MONOTONICITY ******************************************* #
-# The returned result is within 2 ulps in 64 significant bit, #
+# The returned result is within 2 ulps in 64 significant bit, #
# i.e. within 0.5001 ulp to 53 bits if the result is subsequently #
# rounded to double precision. The result is provably monotonic #
# in double precision. #
# #
# ALGORITHM *********************************************************** #
# LOGN: #
-# Step 1. If |X-1| < 1/16, approximate log(X) by an odd #
-# polynomial in u, where u = 2(X-1)/(X+1). Otherwise, #
+# Step 1. If |X-1| < 1/16, approximate log(X) by an odd #
+# polynomial in u, where u = 2(X-1)/(X+1). Otherwise, #
# move on to Step 2. #
# #
# Step 2. X = 2**k * Y where 1 <= Y < 2. Define F to be the first #
-# seven significant bits of Y plus 2**(-7), i.e. #
-# F = 1.xxxxxx1 in base 2 where the six "x" match those #
+# seven significant bits of Y plus 2**(-7), i.e. #
+# F = 1.xxxxxx1 in base 2 where the six "x" match those #
# of Y. Note that |Y-F| <= 2**(-7). #
# #
-# Step 3. Define u = (Y-F)/F. Approximate log(1+u) by a #
+# Step 3. Define u = (Y-F)/F. Approximate log(1+u) by a #
# polynomial in u, log(1+u) = poly. #
# #
-# Step 4. Reconstruct #
+# Step 4. Reconstruct #
# log(X) = log( 2**k * Y ) = k*log(2) + log(F) + log(1+u) #
# by k*log(2) + (log(F) + poly). The values of log(F) are #
# calculated beforehand and stored in the program. #
# #
# lognp1: #
-# Step 1: If |X| < 1/16, approximate log(1+X) by an odd #
+# Step 1: If |X| < 1/16, approximate log(1+X) by an odd #
# polynomial in u where u = 2X/(2+X). Otherwise, move on #
# to Step 2. #
# #
# Step 2: Let 1+X = 2**k * Y, where 1 <= Y < 2. Define F as done #
-# in Step 2 of the algorithm for LOGN and compute #
-# log(1+X) as k*log(2) + log(F) + poly where poly #
-# approximates log(1+u), u = (Y-F)/F. #
+# in Step 2 of the algorithm for LOGN and compute #
+# log(1+X) as k*log(2) + log(F) + poly where poly #
+# approximates log(1+u), u = (Y-F)/F. #
# #
# Implementation Notes: #
-# Note 1. There are 64 different possible values for F, thus 64 #
+# Note 1. There are 64 different possible values for F, thus 64 #
# log(F)'s need to be tabulated. Moreover, the values of #
# 1/F are also tabulated so that the division in (Y-F)/F #
# can be performed by a multiplication. #
# #
-# Note 2. In Step 2 of lognp1, in order to preserved accuracy, #
-# the value Y-F has to be calculated carefully when #
-# 1/2 <= X < 3/2. #
+# Note 2. In Step 2 of lognp1, in order to preserved accuracy, #
+# the value Y-F has to be calculated carefully when #
+# 1/2 <= X < 3/2. #
# #
-# Note 3. To fully exploit the pipeline, polynomials are usually #
+# Note 3. To fully exploit the pipeline, polynomials are usually #
# separated into two parts evaluated independently before #
# being added up. #
# #
@@ -8334,9 +8334,9 @@ LOGBGN:
cmp.l %d1,&0 # CHECK IF X IS NEGATIVE
blt.w LOGNEG # LOG OF NEGATIVE ARGUMENT IS INVALID
# X IS POSITIVE, CHECK IF X IS NEAR 1
- cmp.l %d1,&0x3ffef07d # IS X < 15/16?
+ cmp.l %d1,&0x3ffef07d # IS X < 15/16?
blt.b LOGMAIN # YES
- cmp.l %d1,&0x3fff8841 # IS X > 17/16?
+ cmp.l %d1,&0x3fff8841 # IS X > 17/16?
ble.w LOGNEAR1 # NO
LOGMAIN:
@@ -8349,7 +8349,7 @@ LOGMAIN:
#--NOTE THAT U = (Y-F)/F IS VERY SMALL AND THUS APPROXIMATING
#--LOG(1+U) CAN BE VERY EFFICIENT.
#--ALSO NOTE THAT THE VALUE 1/F IS STORED IN A TABLE SO THAT NO
-#--DIVISION IS NEEDED TO CALCULATE (Y-F)/F.
+#--DIVISION IS NEEDED TO CALCULATE (Y-F)/F.
#--GET K, Y, F, AND ADDRESS OF 1/F.
asr.l &8,%d1
@@ -8564,10 +8564,10 @@ LP1REAL:
mov.l X(%a6),%d1
cmp.l %d1,&0
ble.w LP1NEG0 # LOG OF ZERO OR -VE
- cmp.l %d1,&0x3ffe8000 # IS BOUNDS [1/2,3/2]?
+ cmp.l %d1,&0x3ffe8000 # IS BOUNDS [1/2,3/2]?
blt.w LOGMAIN
cmp.l %d1,&0x3fffc000
- bgt.w LOGMAIN
+ bgt.w LOGMAIN
#--IF 1+Z > 3/2 OR 1+Z < 1/2, THEN X, WHICH IS ROUNDING 1+Z,
#--CONTAINS AT LEAST 63 BITS OF INFORMATION OF Z. IN THAT CASE,
#--SIMPLY INVOKE LOG(X) FOR LOG(1+Z).
@@ -8668,7 +8668,7 @@ slognp1d:
# a0 = pointer to extended precision input #
# d0 = round precision,mode #
# #
-# OUTPUT ************************************************************** #
+# OUTPUT ************************************************************** #
# fp0 = arctanh(X) #
# #
# ACCURACY and MONOTONICITY ******************************************* #
@@ -8783,7 +8783,7 @@ satanhd:
# 2.1 Restore the user FPCR #
# 2.2 Return ans := Y * INV_L10. #
# #
-# slog10: #
+# slog10: #
# #
# Step 0. If X < 0, create a NaN and raise the invalid operation #
# flag. Otherwise, save FPCR in D1; set FpCR to default. #
@@ -8926,7 +8926,7 @@ slog2d:
# fp0 = 2**X or 10**X #
# #
# ACCURACY and MONOTONICITY ******************************************* #
-# The returned result is within 2 ulps in 64 significant bit, #
+# The returned result is within 2 ulps in 64 significant bit, #
# i.e. within 0.5001 ulp to 53 bits if the result is subsequently #
# rounded to double precision. The result is provably monotonic #
# in double precision. #
@@ -8957,7 +8957,7 @@ slog2d:
# #
# 4. Define r as #
# r := ((X - N*L1)-N*L2) * L10 #
-# where L1, L2 are the leading and trailing parts of #
+# where L1, L2 are the leading and trailing parts of #
# log_10(2)/64 and L10 is the natural log of 10. Then #
# 10**X = 2**(M') * 2**(M) * 2**(j/64) * exp(r). #
# Go to expr to compute that expression. #
@@ -8978,7 +8978,7 @@ slog2d:
# Exit. #
# #
# ExpBig #
-# 1. Generate overflow by Huge * Huge if X > 0; otherwise, #
+# 1. Generate overflow by Huge * Huge if X > 0; otherwise, #
# generate underflow by Tiny * Tiny. #
# #
# ExpSm #
@@ -9309,10 +9309,10 @@ stentoxd:
#########################################################################
# smovcr(): returns the ROM constant at the offset specified in d1 #
-# rounded to the mode and precision specified in d0. #
+# rounded to the mode and precision specified in d0. #
# #
# INPUT *************************************************************** #
-# d0 = rnd prec,mode #
+# d0 = rnd prec,mode #
# d1 = ROM offset #
# #
# OUTPUT ************************************************************** #
@@ -9325,7 +9325,7 @@ smovcr:
mov.l %d1,-(%sp) # save rom offset for a sec
lsr.b &0x4,%d0 # shift ctrl bits to lo
- mov.l %d0,%d1 # make a copy
+ mov.l %d0,%d1 # make a copy
andi.w &0x3,%d1 # extract rnd mode
andi.w &0xc,%d0 # extract rnd prec
swap %d0 # put rnd prec in hi
@@ -9343,7 +9343,7 @@ smovcr:
cmpi.b %d1,&0x0e # check range $0b - $0e
ble.b sm_tbl # valid constants in this range
cmpi.b %d1,&0x2f # check range $10 - $2f
- ble.b z_val # if in this range, return zero
+ ble.b z_val # if in this range, return zero
cmpi.b %d1,&0x3f # check range $30 - $3f
ble.b bg_tbl # valid constants in this range
@@ -9378,7 +9378,7 @@ pi_rp:
# $0C e (inexact)
# $0D log2(e) (inexact)
# $0E log10(e) (exact)
-#
+#
# fetch a pointer to the answer table relating to the proper rounding
# precision.
#
@@ -9465,7 +9465,7 @@ not_ext:
swap %d0 # rnd prec in upper word
# call round() to round the answer to the proper precision.
-# exponents out of range for single or double DO NOT cause underflow
+# exponents out of range for single or double DO NOT cause underflow
# or overflow.
mov.w 0x0(%a0,%d1.w),FP_SCR1_EX(%a6) # load first word
mov.l 0x4(%a0,%d1.w),FP_SCR1_HI(%a6) # load second word
@@ -9562,7 +9562,7 @@ BIGRP:
#########################################################################
# sscale(): computes the destination operand scaled by the source #
-# operand. If the absoulute value of the source operand is #
+# operand. If the absoulute value of the source operand is #
# >= 2^14, an overflow or underflow is returned. #
# #
# INPUT *************************************************************** #
@@ -9624,7 +9624,7 @@ sok_dnrm:
bge.b sok_norm2 # thank goodness no
# the multiply factor that we're trying to create should be a denorm
-# for the multiply to work. therefore, we're going to actually do a
+# for the multiply to work. therefore, we're going to actually do a
# multiply with a denorm which will cause an unimplemented data type
# exception to be put into the machine which will be caught and corrected
# later. we don't do this with the DENORMs above because this method
@@ -9639,7 +9639,7 @@ sok_dnrm:
clr.l -(%sp) # insert zero low mantissa
mov.l %d1,-(%sp) # insert new high mantissa
clr.l -(%sp) # make zero exponent
- bra.b sok_norm_cont
+ bra.b sok_norm_cont
sok_dnrm_32:
subi.b &0x20,%d0 # get shift count
lsr.l %d0,%d1 # make low mantissa longword
@@ -9647,7 +9647,7 @@ sok_dnrm_32:
clr.l -(%sp) # insert zero high mantissa
clr.l -(%sp) # make zero exponent
bra.b sok_norm_cont
-
+
# the src will force the dst to a DENORM value or worse. so, let's
# create an fp multiply that will create the result.
sok_norm:
@@ -9705,7 +9705,7 @@ ssmall_done:
# a1 = pointer to extended precision input Y #
# d0 = round precision,mode #
# #
-# The input operands X and Y can be either normalized or #
+# The input operands X and Y can be either normalized or #
# denormalized. #
# #
# OUTPUT ************************************************************** #
@@ -9714,7 +9714,7 @@ ssmall_done:
# ALGORITHM *********************************************************** #
# #
# Step 1. Save and strip signs of X and Y: signX := sign(X), #
-# signY := sign(Y), X := |X|, Y := |Y|, #
+# signY := sign(Y), X := |X|, Y := |Y|, #
# signQ := signX EOR signY. Record whether MOD or REM #
# is requested. #
# #
@@ -9734,7 +9734,7 @@ ssmall_done:
# #
# Step 4. At this point, R = X - QY = MOD(X,Y). Set #
# Last_Subtract := false (used in Step 7 below). If #
-# MOD is requested, go to Step 6. #
+# MOD is requested, go to Step 6. #
# #
# Step 5. R = MOD(X,Y), but REM(X,Y) is requested. #
# 5.1 If R < Y/2, then R = MOD(X,Y) = REM(X,Y). Go to #
@@ -10060,8 +10060,8 @@ Restore:
mov.b &FMUL_OP,%d1 # last inst is MUL
fmul.x Scale(%pc),%fp0 # may cause underflow
bra t_catch2
-# the '040 package did this apparently to see if the dst operand for the
-# preceding fmul was a denorm. but, it better not have been since the
+# the '040 package did this apparently to see if the dst operand for the
+# preceding fmul was a denorm. but, it better not have been since the
# algorithm just got done playing with fp0 and expected no exceptions
# as a result. trust me...
# bra t_avoid_unsupp # check for denorm as a
@@ -10075,7 +10075,7 @@ Finish:
Rem_is_0:
#..R = 2^(-j)X - Q Y = Y, thus R = 0 and quotient = 2^j (Q+1)
addq.l &1,%d3
- cmp.l %d0,&8 # D0 is j
+ cmp.l %d0,&8 # D0 is j
bge.b Q_Big
lsl.l %d0,%d3
@@ -10117,20 +10117,20 @@ qnan: long 0x7fff0000, 0xffffffff, 0xff
# #
# INPUT *************************************************************** #
# a0 = pointer to source operand #
-# #
+# #
# OUTPUT ************************************************************** #
# fp0 = default result #
# #
# ALGORITHM *********************************************************** #
# - Store properly signed INF into fp0. #
-# - Set FPSR exception status dz bit, ccode inf bit, and #
+# - Set FPSR exception status dz bit, ccode inf bit, and #
# accrued dz bit. #
# #
#########################################################################
global t_dz
t_dz:
- tst.b SRC_EX(%a0) # no; is src negative?
+ tst.b SRC_EX(%a0) # no; is src negative?
bmi.b t_dz2 # yes
dz_pinf:
@@ -10146,7 +10146,7 @@ t_dz2:
#################################################################
# OPERR exception: #
-# - set FPSR exception status operr bit, condition code #
+# - set FPSR exception status operr bit, condition code #
# nan bit; Store default NAN into fp0 #
#################################################################
global t_operr
@@ -10157,7 +10157,7 @@ t_operr:
#################################################################
# Extended DENORM: #
-# - For all functions that have a denormalized input and #
+# - For all functions that have a denormalized input and #
# that f(x)=x, this is the entry point. #
# - we only return the EXOP here if either underflow or #
# inexact is enabled. #
@@ -10224,13 +10224,13 @@ xdnrm_ena:
#################################################################
# UNFL exception: #
-# - This routine is for cases where even an EXOP isn't #
-# large enough to hold the range of this result. #
+# - This routine is for cases where even an EXOP isn't #
+# large enough to hold the range of this result. #
# In such a case, the EXOP equals zero. #
-# - Return the default result to the proper precision #
+# - Return the default result to the proper precision #
# with the sign of this result being the same as that #
# of the src operand. #
-# - t_unfl2() is provided to force the result sign to #
+# - t_unfl2() is provided to force the result sign to #
# positive which is the desired result for fetox(). #
#################################################################
global t_unfl
@@ -10259,15 +10259,15 @@ t_unfl2:
#################################################################
# OVFL exception: #
-# - This routine is for cases where even an EXOP isn't #
-# large enough to hold the range of this result. #
-# - Return the default result to the proper precision #
-# with the sign of this result being the same as that #
+# - This routine is for cases where even an EXOP isn't #
+# large enough to hold the range of this result. #
+# - Return the default result to the proper precision #
+# with the sign of this result being the same as that #
# of the src operand. #
-# - t_ovfl2() is provided to force the result sign to #
+# - t_ovfl2() is provided to force the result sign to #
# positive which is the desired result for fcosh(). #
-# - t_ovfl_sc() is provided for scale() which only sets #
-# the inexact bits if the number is inexact for the #
+# - t_ovfl_sc() is provided for scale() which only sets #
+# the inexact bits if the number is inexact for the #
# precision indicated. #
#################################################################
@@ -10338,10 +10338,10 @@ t_ovfl2:
rts
#################################################################
-# t_catch(): #
+# t_catch(): #
# - the last operation of a transcendental emulation #
-# routine may have caused an underflow or overflow. #
-# we find out if this occurred by doing an fsave and #
+# routine may have caused an underflow or overflow. #
+# we find out if this occurred by doing an fsave and #
# checking the exception bit. if one did occur, then we #
# jump to fgen_except() which creates the default #
# result and EXOP for us. #
@@ -10407,8 +10407,8 @@ t_catch2:
# unf_res(): underflow default result calculation for transcendentals #
# #
# INPUT: #
-# d0 : rnd mode,precision #
-# d1.b : sign bit of result ('11111111 = (-) ; '00000000 = (+)) #
+# d0 : rnd mode,precision #
+# d1.b : sign bit of result ('11111111 = (-) ; '00000000 = (+)) #
# OUTPUT: #
# a0 : points to result (in instruction memory) #
#########################################################################
@@ -10457,7 +10457,7 @@ tbl_unf_result:
long 0x0,0x0,0x0,0x0
long 0x0,0x0,0x0,0x0
long 0x0,0x0,0x0,0x0
-
+
long 0x80000000, 0x00000000, 0x00000000, 0x0 # ZERO;ext
long 0x80000000, 0x00000000, 0x00000000, 0x0 # ZERO;ext
long 0x80000000, 0x00000000, 0x00000001, 0x0 # MIN; ext
@@ -10504,7 +10504,7 @@ ld_mzero:
#########################################################################
global dst_zero
dst_zero:
- tst.b DST_EX(%a1) # get sign of dst operand
+ tst.b DST_EX(%a1) # get sign of dst operand
bmi.b ld_mzero # if neg, load neg zero
bra.b ld_pzero # load positive zero
@@ -10513,7 +10513,7 @@ dst_zero:
#########################################################################
global src_inf
src_inf:
- tst.b SRC_EX(%a0) # get sign of src operand
+ tst.b SRC_EX(%a0) # get sign of src operand
bmi.b ld_minf # if negative branch
#
@@ -10539,7 +10539,7 @@ ld_minf:
#########################################################################
global dst_inf
dst_inf:
- tst.b DST_EX(%a1) # get sign of dst operand
+ tst.b DST_EX(%a1) # get sign of dst operand
bmi.b ld_minf # if negative branch
bra.b ld_pinf
@@ -10581,7 +10581,7 @@ setoxm1i:
#########################################################################
global src_one
src_one:
- tst.b SRC_EX(%a0) # check sign of source
+ tst.b SRC_EX(%a0) # check sign of source
bmi.b ld_mone
#
@@ -10610,7 +10610,7 @@ mpiby2: long 0xbfff0000, 0xc90fdaa2, 0x
#################################################################
global spi_2
spi_2:
- tst.b SRC_EX(%a0) # check sign of source
+ tst.b SRC_EX(%a0) # check sign of source
bmi.b ld_mpi2
#
@@ -10637,7 +10637,7 @@ ld_mpi2:
#
# ssincosz(): When the src operand is ZERO, store a one in the
-# cosine register and return a ZERO in fp0 w/ the same sign
+# cosine register and return a ZERO in fp0 w/ the same sign
# as the src operand.
#
global ssincosz
@@ -10666,7 +10666,7 @@ ssincosi:
#
# ssincosqnan(): When the src operand is a QNAN, store the QNAN in the cosine
-# register and branch to the src QNAN routine.
+# register and branch to the src QNAN routine.
#
global ssincosqnan
ssincosqnan:
@@ -10719,7 +10719,7 @@ sto_cos_1:
fmovm.x &0x40,EXC_FP1(%a6)
rts
sto_cos_2:
- fmov.x %fp1,%fp2
+ fmov.x %fp1,%fp2
rts
sto_cos_3:
fmov.x %fp1,%fp3
@@ -10988,8 +10988,8 @@ src_qnan_m:
# fkern2.s:
# These entry points are used by the exception handler
# routines where an instruction is selected by an index into
-# a large jump table corresponding to a given instruction which
-# has been decoded. Flow continues here where we now decode
+# a large jump table corresponding to a given instruction which
+# has been decoded. Flow continues here where we now decode
# further accoding to the source operand type.
#
@@ -11331,11 +11331,11 @@ fscale:
#########################################################################
# XDEF **************************************************************** #
-# fgen_except(): catch an exception during transcendental #
+# fgen_except(): catch an exception during transcendental #
# emulation #
# #
# XREF **************************************************************** #
-# fmul() - emulate a multiply instruction #
+# fmul() - emulate a multiply instruction #
# fadd() - emulate an add instruction #
# fin() - emulate an fmove instruction #
# #
@@ -11343,16 +11343,16 @@ fscale:
# fp0 = destination operand #
# d0 = type of instruction that took exception #
# fsave frame = source operand #
-# #
+# #
# OUTPUT ************************************************************** #
# fp0 = result #
# fp1 = EXOP #
# #
# ALGORITHM *********************************************************** #
-# An exception occurred on the last instruction of the #
-# transcendental emulation. hopefully, this won't be happening much #
+# An exception occurred on the last instruction of the #
+# transcendental emulation. hopefully, this won't be happening much #
# because it will be VERY slow. #
-# The only exceptions capable of passing through here are #
+# The only exceptions capable of passing through here are #
# Overflow, Underflow, and Unsupported Data Type. #
# #
#########################################################################
@@ -11408,11 +11408,11 @@ fge_unsupp:
swbeg &109
tbl_unsupp:
- long fin - tbl_unsupp # 00: fmove
- long fint - tbl_unsupp # 01: fint
- long fsinh - tbl_unsupp # 02: fsinh
- long fintrz - tbl_unsupp # 03: fintrz
- long fsqrt - tbl_unsupp # 04: fsqrt
+ long fin - tbl_unsupp # 00: fmove
+ long fint - tbl_unsupp # 01: fint
+ long fsinh - tbl_unsupp # 02: fsinh
+ long fintrz - tbl_unsupp # 03: fintrz
+ long fsqrt - tbl_unsupp # 04: fsqrt
long tbl_unsupp - tbl_unsupp
long flognp1 - tbl_unsupp # 06: flognp1
long tbl_unsupp - tbl_unsupp
@@ -11432,23 +11432,23 @@ tbl_unsupp:
long flog10 - tbl_unsupp # 15: flog10
long flog2 - tbl_unsupp # 16: flog2
long tbl_unsupp - tbl_unsupp
- long fabs - tbl_unsupp # 18: fabs
+ long fabs - tbl_unsupp # 18: fabs
long fcosh - tbl_unsupp # 19: fcosh
- long fneg - tbl_unsupp # 1a: fneg
+ long fneg - tbl_unsupp # 1a: fneg
long tbl_unsupp - tbl_unsupp
long facos - tbl_unsupp # 1c: facos
long fcos - tbl_unsupp # 1d: fcos
long fgetexp - tbl_unsupp # 1e: fgetexp
long fgetman - tbl_unsupp # 1f: fgetman
- long fdiv - tbl_unsupp # 20: fdiv
+ long fdiv - tbl_unsupp # 20: fdiv
long fmod - tbl_unsupp # 21: fmod
- long fadd - tbl_unsupp # 22: fadd
- long fmul - tbl_unsupp # 23: fmul
- long fsgldiv - tbl_unsupp # 24: fsgldiv
+ long fadd - tbl_unsupp # 22: fadd
+ long fmul - tbl_unsupp # 23: fmul
+ long fsgldiv - tbl_unsupp # 24: fsgldiv
long frem - tbl_unsupp # 25: frem
long fscale - tbl_unsupp # 26: fscale
- long fsglmul - tbl_unsupp # 27: fsglmul
- long fsub - tbl_unsupp # 28: fsub
+ long fsglmul - tbl_unsupp # 27: fsglmul
+ long fsub - tbl_unsupp # 28: fsub
long tbl_unsupp - tbl_unsupp
long tbl_unsupp - tbl_unsupp
long tbl_unsupp - tbl_unsupp
@@ -11464,20 +11464,20 @@ tbl_unsupp:
long fsincos - tbl_unsupp # 35: fsincos
long fsincos - tbl_unsupp # 36: fsincos
long fsincos - tbl_unsupp # 37: fsincos
- long fcmp - tbl_unsupp # 38: fcmp
+ long fcmp - tbl_unsupp # 38: fcmp
long tbl_unsupp - tbl_unsupp
- long ftst - tbl_unsupp # 3a: ftst
+ long ftst - tbl_unsupp # 3a: ftst
long tbl_unsupp - tbl_unsupp
long tbl_unsupp - tbl_unsupp
long tbl_unsupp - tbl_unsupp
long tbl_unsupp - tbl_unsupp
long tbl_unsupp - tbl_unsupp
- long fsin - tbl_unsupp # 40: fsmove
- long fssqrt - tbl_unsupp # 41: fssqrt
+ long fsin - tbl_unsupp # 40: fsmove
+ long fssqrt - tbl_unsupp # 41: fssqrt
long tbl_unsupp - tbl_unsupp
long tbl_unsupp - tbl_unsupp
long fdin - tbl_unsupp # 44: fdmove
- long fdsqrt - tbl_unsupp # 45: fdsqrt
+ long fdsqrt - tbl_unsupp # 45: fdsqrt
long tbl_unsupp - tbl_unsupp
long tbl_unsupp - tbl_unsupp
long tbl_unsupp - tbl_unsupp
@@ -11496,31 +11496,31 @@ tbl_unsupp:
long tbl_unsupp - tbl_unsupp
long tbl_unsupp - tbl_unsupp
long tbl_unsupp - tbl_unsupp
- long fsabs - tbl_unsupp # 58: fsabs
+ long fsabs - tbl_unsupp # 58: fsabs
long tbl_unsupp - tbl_unsupp
- long fsneg - tbl_unsupp # 5a: fsneg
+ long fsneg - tbl_unsupp # 5a: fsneg
long tbl_unsupp - tbl_unsupp
long fdabs - tbl_unsupp # 5c: fdabs
long tbl_unsupp - tbl_unsupp
- long fdneg - tbl_unsupp # 5e: fdneg
+ long fdneg - tbl_unsupp # 5e: fdneg
long tbl_unsupp - tbl_unsupp
long fsdiv - tbl_unsupp # 60: fsdiv
long tbl_unsupp - tbl_unsupp
long fsadd - tbl_unsupp # 62: fsadd
long fsmul - tbl_unsupp # 63: fsmul
- long fddiv - tbl_unsupp # 64: fddiv
+ long fddiv - tbl_unsupp # 64: fddiv
long tbl_unsupp - tbl_unsupp
long fdadd - tbl_unsupp # 66: fdadd
- long fdmul - tbl_unsupp # 67: fdmul
+ long fdmul - tbl_unsupp # 67: fdmul
long fssub - tbl_unsupp # 68: fssub
long tbl_unsupp - tbl_unsupp
long tbl_unsupp - tbl_unsupp
long tbl_unsupp - tbl_unsupp
- long fdsub - tbl_unsupp # 6c: fdsub
+ long fdsub - tbl_unsupp # 6c: fdsub
#########################################################################
# XDEF **************************************************************** #
-# fmul(): emulates the fmul instruction #
+# fmul(): emulates the fmul instruction #
# fsmul(): emulates the fsmul instruction #
# fdmul(): emulates the fdmul instruction #
# #
@@ -11529,8 +11529,8 @@ tbl_unsupp:
# scale_to_zero_dst() - scale dst exponent to zero #
# unf_res() - return default underflow result #
# ovf_res() - return default overflow result #
-# res_qnan() - return QNAN result #
-# res_snan() - return SNAN result #
+# res_qnan() - return QNAN result #
+# res_snan() - return SNAN result #
# #
# INPUT *************************************************************** #
# a0 = pointer to extended precision source operand #
@@ -11548,12 +11548,12 @@ tbl_unsupp:
# instruction won't cause an exception. Use the regular fmul to #
# compute a result. Check if the regular operands would have taken #
# an exception. If so, return the default overflow/underflow result #
-# and return the EXOP if exceptions are enabled. Else, scale the #
+# and return the EXOP if exceptions are enabled. Else, scale the #
# result operand to the proper exponent. #
# #
#########################################################################
- align 0x10
+ align 0x10
tbl_fmul_ovfl:
long 0x3fff - 0x7ffe # ext_max
long 0x3fff - 0x407e # sgl_max
@@ -11614,7 +11614,7 @@ fmul_norm:
#
# NORMAL:
# - the result of the multiply operation will neither overflow nor underflow.
-# - do the multiply to the proper precision and rounding mode.
+# - do the multiply to the proper precision and rounding mode.
# - scale the result exponent using the scale factor. if both operands were
# normalized then we really don't need to go through this scaling. but for now,
# this will do.
@@ -11625,7 +11625,7 @@ fmul_normal:
fmov.l L_SCR3(%a6),%fpcr # set FPCR
fmov.l &0x0,%fpsr # clear FPSR
- fmul.x FP_SCR0(%a6),%fp0 # execute multiply
+ fmul.x FP_SCR0(%a6),%fp0 # execute multiply
fmov.l %fpsr,%d1 # save status
fmov.l &0x0,%fpcr # clear FPCR
@@ -11665,7 +11665,7 @@ fmul_ovfl:
fmov.l L_SCR3(%a6),%fpcr # set FPCR
fmov.l &0x0,%fpsr # clear FPSR
- fmul.x FP_SCR0(%a6),%fp0 # execute multiply
+ fmul.x FP_SCR0(%a6),%fp0 # execute multiply
fmov.l %fpsr,%d1 # save status
fmov.l &0x0,%fpcr # clear FPCR
@@ -11744,7 +11744,7 @@ fmul_may_ovfl:
fmov.l &0x0,%fpsr # clear FPSR
fmul.x FP_SCR0(%a6),%fp0 # execute multiply
-
+
fmov.l %fpsr,%d1 # save status
fmov.l &0x0,%fpcr # clear FPCR
@@ -11753,7 +11753,7 @@ fmul_may_ovfl:
fabs.x %fp0,%fp1 # make a copy of result
fcmp.b %fp1,&0x2 # is |result| >= 2.b?
fbge.w fmul_ovfl_tst # yes; overflow has occurred
-
+
# no, it didn't overflow; we have correct result
bra.w fmul_normal_exit
@@ -11770,7 +11770,7 @@ fmul_may_ovfl:
# of this operation then has its exponent scaled by -0x6000 to create the
# exceptional operand.
#
-fmul_unfl:
+fmul_unfl:
bset &unfl_bit,FPSR_EXCEPT(%a6) # set unfl exc bit
# for fun, let's use only extended precision, round to zero. then, let
@@ -11803,7 +11803,7 @@ fmul_unfl_dis:
rts
#
-# UNFL is enabled.
+# UNFL is enabled.
#
fmul_unfl_ena:
fmovm.x FP_SCR1(%a6),&0x40 # load dst op
@@ -11819,7 +11819,7 @@ fmul_unfl_ena:
fmul_unfl_ena_cont:
fmov.l &0x0,%fpsr # clear FPSR
- fmul.x FP_SCR0(%a6),%fp1 # execute multiply
+ fmul.x FP_SCR0(%a6),%fp1 # execute multiply
fmov.l &0x0,%fpcr # clear FPCR
@@ -11854,7 +11854,7 @@ fmul_may_unfl:
fmov.l L_SCR3(%a6),%fpcr # set FPCR
fmov.l &0x0,%fpsr # clear FPSR
- fmul.x FP_SCR0(%a6),%fp0 # execute multiply
+ fmul.x FP_SCR0(%a6),%fp0 # execute multiply
fmov.l %fpsr,%d1 # save status
fmov.l &0x0,%fpcr # clear FPCR
@@ -11878,11 +11878,11 @@ fmul_may_unfl:
mov.l L_SCR3(%a6),%d1
andi.b &0xc0,%d1 # keep rnd prec
ori.b &rz_mode*0x10,%d1 # insert RZ
-
+
fmov.l %d1,%fpcr # set FPCR
fmov.l &0x0,%fpsr # clear FPSR
- fmul.x FP_SCR0(%a6),%fp1 # execute multiply
+ fmul.x FP_SCR0(%a6),%fp1 # execute multiply
fmov.l &0x0,%fpcr # clear FPCR
fabs.x %fp1 # make absolute value
@@ -12024,22 +12024,22 @@ fmul_inf_src:
# norm() - normalize mantissa for EXOP on denorm #
# scale_to_zero_src() - scale src exponent to zero #
# ovf_res() - return default overflow result #
-# unf_res() - return default underflow result #
+# unf_res() - return default underflow result #
# res_qnan_1op() - return QNAN result #
# res_snan_1op() - return SNAN result #
# #
# INPUT *************************************************************** #
# a0 = pointer to extended precision source operand #
# d0 = round prec/mode #
-# #
+# #
# OUTPUT ************************************************************** #
# fp0 = result #
# fp1 = EXOP (if exception occurred) #
# #
# ALGORITHM *********************************************************** #
-# Handle NANs, infinities, and zeroes as special cases. Divide #
+# Handle NANs, infinities, and zeroes as special cases. Divide #
# norms into extended, single, and double precision. #
-# Norms can be emulated w/ a regular fmove instruction. For #
+# Norms can be emulated w/ a regular fmove instruction. For #
# sgl/dbl, must scale exponent and perform an "fmove". Check to see #
# if the result would have overflowed/underflowed. If so, use unf_res() #
# or ovf_res() to return the default result. Also return EXOP if #
@@ -12065,7 +12065,7 @@ fin:
mov.b STAG(%a6),%d1 # fetch src optype tag
bne.w fin_not_norm # optimize on non-norm input
-
+
#
# FP MOVE IN: NORMs and DENORMs ONLY!
#
@@ -12126,9 +12126,9 @@ fin_denorm_unfl_ena:
#
# operand is to be rounded to single or double precision
-#
+#
fin_not_ext:
- cmpi.b %d0,&s_mode*0x10 # separate sgl/dbl prec
+ cmpi.b %d0,&s_mode*0x10 # separate sgl/dbl prec
bne.b fin_dbl
#
@@ -12212,10 +12212,10 @@ fin_sd_unfl_dis:
bsr.l unf_res # calculate default result
or.b %d0,FPSR_CC(%a6) # unf_res may have set 'Z'
fmovm.x FP_SCR0(%a6),&0x80 # return default result in fp0
- rts
+ rts
#
-# operand will underflow AND underflow or inexact is enabled.
+# operand will underflow AND underflow or inexact is enabled.
# therefore, we must return the result rounded to extended precision.
#
fin_sd_unfl_ena:
@@ -12337,7 +12337,7 @@ fin_not_norm:
#########################################################################
# XDEF **************************************************************** #
-# fdiv(): emulates the fdiv instruction #
+# fdiv(): emulates the fdiv instruction #
# fsdiv(): emulates the fsdiv instruction #
# fddiv(): emulates the fddiv instruction #
# #
@@ -12346,8 +12346,8 @@ fin_not_norm:
# scale_to_zero_dst() - scale dst exponent to zero #
# unf_res() - return default underflow result #
# ovf_res() - return default overflow result #
-# res_qnan() - return QNAN result #
-# res_snan() - return SNAN result #
+# res_qnan() - return QNAN result #
+# res_snan() - return SNAN result #
# #
# INPUT *************************************************************** #
# a0 = pointer to extended precision source operand #
@@ -12365,7 +12365,7 @@ fin_not_norm:
# instruction won't cause an exception. Use the regular fdiv to #
# compute a result. Check if the regular operands would have taken #
# an exception. If so, return the default overflow/underflow result #
-# and return the EXOP if exceptions are enabled. Else, scale the #
+# and return the EXOP if exceptions are enabled. Else, scale the #
# result operand to the proper exponent. #
# #
#########################################################################
@@ -12402,7 +12402,7 @@ fdiv:
or.b STAG(%a6),%d1 # combine src tags
bne.w fdiv_not_norm # optimize on non-norm input
-
+
#
# DIVIDE: NORMs and DENORMs ONLY!
#
@@ -12468,7 +12468,7 @@ tbl_fdiv_ovfl2:
fdiv_no_ovfl:
mov.l (%sp)+,%d0 # restore scale factor
bra.b fdiv_normal_exit
-
+
fdiv_may_ovfl:
mov.l %d0,-(%sp) # save scale factor
@@ -12501,7 +12501,7 @@ fdiv_ovfl_tst:
bne.b fdiv_ovfl_ena # yes
fdiv_ovfl_dis:
- btst &neg_bit,FPSR_CC(%a6) # is result negative?
+ btst &neg_bit,FPSR_CC(%a6) # is result negative?
sne %d1 # set sign param accordingly
mov.l L_SCR3(%a6),%d0 # pass prec:rnd
bsr.l ovf_res # calculate default result
@@ -12573,7 +12573,7 @@ fdiv_unfl_dis:
rts
#
-# UNFL is enabled.
+# UNFL is enabled.
#
fdiv_unfl_ena:
fmovm.x FP_SCR1(%a6),&0x40 # load dst op
@@ -12637,8 +12637,8 @@ fdiv_may_unfl:
#
# we still don't know if underflow occurred. result is ~ equal to 1. but,
# we don't know if the result was an underflow that rounded up to a 1
-# or a normalized number that rounded down to a 1. so, redo the entire
-# operation using RZ as the rounding mode to see what the pre-rounded
+# or a normalized number that rounded down to a 1. so, redo the entire
+# operation using RZ as the rounding mode to see what the pre-rounded
# result is. this case should be relatively rare.
#
fmovm.x FP_SCR1(%a6),&0x40 # load dst op into fp1
@@ -12765,8 +12765,8 @@ fdiv_inf_load_p:
rts
#
-# The destination was an INF w/ an In Range or ZERO source, the result is
-# an INF w/ the proper sign.
+# The destination was an INF w/ an In Range or ZERO source, the result is
+# an INF w/ the proper sign.
# The 68881/882 returns the destination INF w/ the new sign(if the j-bit of the
# dst INF is set, then then j-bit of the result INF is also set).
#
@@ -12796,11 +12796,11 @@ fdiv_inf_dst_p:
# fdneg(): emulates the fdneg instruction #
# #
# XREF **************************************************************** #
-# norm() - normalize a denorm to provide EXOP #
+# norm() - normalize a denorm to provide EXOP #
# scale_to_zero_src() - scale sgl/dbl source exponent #
# ovf_res() - return default overflow result #
# unf_res() - return default underflow result #
-# res_qnan_1op() - return QNAN result #
+# res_qnan_1op() - return QNAN result #
# res_snan_1op() - return SNAN result #
# #
# INPUT *************************************************************** #
@@ -12838,7 +12838,7 @@ fneg:
mov.l %d0,L_SCR3(%a6) # store rnd info
mov.b STAG(%a6),%d1
bne.w fneg_not_norm # optimize on non-norm input
-
+
#
# NEGATE SIGN : norms and denorms ONLY!
#
@@ -12897,7 +12897,7 @@ fneg_ext_unfl_ena:
neg.w %d0 # new exponent = -(shft val)
addi.w &0x6000,%d0 # add new bias to exponent
mov.w FP_SCR0_EX(%a6),%d1 # fetch old sign,exp
- andi.w &0x8000,%d1 # keep old sign
+ andi.w &0x8000,%d1 # keep old sign
andi.w &0x7fff,%d0 # clear sign position
or.w %d1,%d0 # concat old sign, new exponent
mov.w %d0,FP_SCR0_EX(%a6) # insert new exponent
@@ -12976,7 +12976,7 @@ fneg_dbl:
fneg_sd_unfl:
bset &unfl_bit,FPSR_EXCEPT(%a6) # set unfl exc bit
- eori.b &0x80,FP_SCR0_EX(%a6) # negate sign
+ eori.b &0x80,FP_SCR0_EX(%a6) # negate sign
bpl.b fneg_sd_unfl_tst
bset &neg_bit,FPSR_CC(%a6) # set 'N' ccode bit
@@ -12992,10 +12992,10 @@ fneg_sd_unfl_dis:
bsr.l unf_res # calculate default result
or.b %d0,FPSR_CC(%a6) # unf_res may have set 'Z'
fmovm.x FP_SCR0(%a6),&0x80 # return default result in fp0
- rts
+ rts
#
-# operand will underflow AND underflow is enabled.
+# operand will underflow AND underflow is enabled.
# therefore, we must return the result rounded to extended precision.
#
fneg_sd_unfl_ena:
@@ -13117,19 +13117,19 @@ fneg_not_norm:
#########################################################################
# XDEF **************************************************************** #
-# ftst(): emulates the ftest instruction #
+# ftst(): emulates the ftest instruction #
# #
# XREF **************************************************************** #
-# res{s,q}nan_1op() - set NAN result for monadic instruction #
+# res{s,q}nan_1op() - set NAN result for monadic instruction #
# #
# INPUT *************************************************************** #
-# a0 = pointer to extended precision source operand #
+# a0 = pointer to extended precision source operand #
# #
# OUTPUT ************************************************************** #
# none #
# #
# ALGORITHM *********************************************************** #
-# Check the source operand tag (STAG) and set the FPCR according #
+# Check the source operand tag (STAG) and set the FPCR according #
# to the operand type and sign. #
# #
#########################################################################
@@ -13138,7 +13138,7 @@ fneg_not_norm:
ftst:
mov.b STAG(%a6),%d1
bne.b ftst_not_norm # optimize on non-norm input
-
+
#
# Norm:
#
@@ -13186,7 +13186,7 @@ ftst_inf_p:
ftst_inf_m:
mov.b &inf_bmask+neg_bmask,FPSR_CC(%a6) # set 'I','N' ccode bits
rts
-
+
#
# Zero:
#
@@ -13215,13 +13215,13 @@ ftst_zero_m:
# fp0 = result #
# #
# ALGORITHM *********************************************************** #
-# Separate according to operand type. Unnorms don't pass through #
-# here. For norms, load the rounding mode/prec, execute a "fint", then #
+# Separate according to operand type. Unnorms don't pass through #
+# here. For norms, load the rounding mode/prec, execute a "fint", then #
# store the resulting FPSR bits. #
-# For denorms, force the j-bit to a one and do the same as for #
-# norms. Denorms are so low that the answer will either be a zero or a #
+# For denorms, force the j-bit to a one and do the same as for #
+# norms. Denorms are so low that the answer will either be a zero or a #
# one. #
-# For zeroes/infs/NANs, return the same while setting the FPSR #
+# For zeroes/infs/NANs, return the same while setting the FPSR #
# as appropriate. #
# #
#########################################################################
@@ -13230,7 +13230,7 @@ ftst_zero_m:
fint:
mov.b STAG(%a6),%d1
bne.b fint_not_norm # optimize on non-norm input
-
+
#
# Norm:
#
@@ -13240,7 +13240,7 @@ fint_norm:
fmov.l %d0,%fpcr # set FPCR
fmov.l &0x0,%fpsr # clear FPSR
- fint.x SRC(%a0),%fp0 # execute fint
+ fint.x SRC(%a0),%fp0 # execute fint
fmov.l &0x0,%fpcr # clear FPCR
fmov.l %fpsr,%d0 # save FPSR
@@ -13318,16 +13318,16 @@ fint_inf_m:
# d0 = round precision/mode #
# #
# OUTPUT ************************************************************** #
-# fp0 = result #
+# fp0 = result #
# #
# ALGORITHM *********************************************************** #
# Separate according to operand type. Unnorms don't pass through #
-# here. For norms, load the rounding mode/prec, execute a "fintrz", #
+# here. For norms, load the rounding mode/prec, execute a "fintrz", #
# then store the resulting FPSR bits. #
-# For denorms, force the j-bit to a one and do the same as for #
+# For denorms, force the j-bit to a one and do the same as for #
# norms. Denorms are so low that the answer will either be a zero or a #
# one. #
-# For zeroes/infs/NANs, return the same while setting the FPSR #
+# For zeroes/infs/NANs, return the same while setting the FPSR #
# as appropriate. #
# #
#########################################################################
@@ -13336,7 +13336,7 @@ fint_inf_m:
fintrz:
mov.b STAG(%a6),%d1
bne.b fintrz_not_norm # optimize on non-norm input
-
+
#
# Norm:
#
@@ -13431,17 +13431,17 @@ fintrz_inf_m:
# #
# ALGORITHM *********************************************************** #
# Handle NANs, infinities, and zeroes as special cases. Divide #
-# norms into extended, single, and double precision. #
-# Simply clear sign for extended precision norm. Ext prec denorm #
+# norms into extended, single, and double precision. #
+# Simply clear sign for extended precision norm. Ext prec denorm #
# gets an EXOP created for it since it's an underflow. #
# Double and single precision can overflow and underflow. First, #
# scale the operand such that the exponent is zero. Perform an "fabs" #
-# using the correct rnd mode/prec. Check to see if the original #
+# using the correct rnd mode/prec. Check to see if the original #
# exponent would take an exception. If so, use unf_res() or ovf_res() #
# to calculate the default result. Also, create the EXOP for the #
-# exceptional case. If no exception should occur, insert the correct #
+# exceptional case. If no exception should occur, insert the correct #
# result exponent and return. #
-# Unnorms don't pass through here. #
+# Unnorms don't pass through here. #
# #
#########################################################################
@@ -13461,7 +13461,7 @@ fabs:
mov.l %d0,L_SCR3(%a6) # store rnd info
mov.b STAG(%a6),%d1
bne.w fabs_not_norm # optimize on non-norm input
-
+
#
# ABSOLUTE VALUE: norms and denorms ONLY!
#
@@ -13607,10 +13607,10 @@ fabs_sd_unfl_dis:
bsr.l unf_res # calculate default result
or.b %d0,FPSR_CC(%a6) # set possible 'Z' ccode
fmovm.x FP_SCR0(%a6),&0x80 # return default result in fp0
- rts
+ rts
#
-# operand will underflow AND underflow is enabled.
+# operand will underflow AND underflow is enabled.
# therefore, we must return the result rounded to extended precision.
#
fabs_sd_unfl_ena:
@@ -13732,10 +13732,10 @@ fabs_inf:
#########################################################################
# XDEF **************************************************************** #
-# fcmp(): fp compare op routine #
+# fcmp(): fp compare op routine #
# #
# XREF **************************************************************** #
-# res_qnan() - return QNAN result #
+# res_qnan() - return QNAN result #
# res_snan() - return SNAN result #
# #
# INPUT *************************************************************** #
@@ -13747,7 +13747,7 @@ fabs_inf:
# None #
# #
# ALGORITHM *********************************************************** #
-# Handle NANs and denorms as special cases. For everything else, #
+# Handle NANs and denorms as special cases. For everything else, #
# just use the actual fcmp instruction to produce the correct condition #
# codes. #
# #
@@ -13760,14 +13760,14 @@ fcmp:
lsl.b &0x3,%d1
or.b STAG(%a6),%d1
bne.b fcmp_not_norm # optimize on non-norm input
-
+
#
# COMPARE FP OPs : NORMs, ZEROs, INFs, and "corrected" DENORMs
#
fcmp_norm:
fmovm.x DST(%a1),&0x80 # load dst op
- fcmp.x %fp0,SRC(%a0) # do compare
+ fcmp.x %fp0,SRC(%a0) # do compare
fmov.l %fpsr,%d0 # save FPSR
rol.l &0x8,%d0 # extract ccode bits
@@ -13788,7 +13788,7 @@ tbl_fcmp_op:
short fcmp_norm - tbl_fcmp_op # NORM - ZERO
short fcmp_norm - tbl_fcmp_op # NORM - INF
short fcmp_res_qnan - tbl_fcmp_op # NORM - QNAN
- short fcmp_nrm_dnrm - tbl_fcmp_op # NORM - DENORM
+ short fcmp_nrm_dnrm - tbl_fcmp_op # NORM - DENORM
short fcmp_res_snan - tbl_fcmp_op # NORM - SNAN
short tbl_fcmp_op - tbl_fcmp_op #
short tbl_fcmp_op - tbl_fcmp_op #
@@ -13850,8 +13850,8 @@ fcmp_res_snan:
rts
#
-# DENORMs are a little more difficult.
-# If you have a 2 DENORMs, then you can just force the j-bit to a one
+# DENORMs are a little more difficult.
+# If you have a 2 DENORMs, then you can just force the j-bit to a one
# and use the fcmp_norm routine.
# If you have a DENORM and an INF or ZERO, just force the DENORM's j-bit to a one
# and use the fcmp_norm routine.
@@ -13892,7 +13892,7 @@ fcmp_dnrm_sd:
mov.l SRC_LO(%a0),FP_SCR0_LO(%a6)
lea FP_SCR1(%a6),%a1
lea FP_SCR0(%a6),%a0
- bra.w fcmp_norm
+ bra.w fcmp_norm
fcmp_nrm_dnrm:
mov.b SRC_EX(%a0),%d0 # determine if like signs
@@ -13924,15 +13924,15 @@ fcmp_dnrm_nrm_m:
#########################################################################
# XDEF **************************************************************** #
-# fsglmul(): emulates the fsglmul instruction #
+# fsglmul(): emulates the fsglmul instruction #
# #
# XREF **************************************************************** #
# scale_to_zero_src() - scale src exponent to zero #
# scale_to_zero_dst() - scale dst exponent to zero #
# unf_res4() - return default underflow result for sglop #
# ovf_res() - return default overflow result #
-# res_qnan() - return QNAN result #
-# res_snan() - return SNAN result #
+# res_qnan() - return QNAN result #
+# res_snan() - return SNAN result #
# #
# INPUT *************************************************************** #
# a0 = pointer to extended precision source operand #
@@ -13950,7 +13950,7 @@ fcmp_dnrm_nrm_m:
# instruction won't cause an exception. Use the regular fsglmul to #
# compute a result. Check if the regular operands would have taken #
# an exception. If so, return the default overflow/underflow result #
-# and return the EXOP if exceptions are enabled. Else, scale the #
+# and return the EXOP if exceptions are enabled. Else, scale the #
# result operand to the proper exponent. #
# #
#########################################################################
@@ -13982,11 +13982,11 @@ fsglmul_norm:
add.l (%sp)+,%d0 # SCALE_FACTOR = scale1 + scale2
- cmpi.l %d0,&0x3fff-0x7ffe # would result ovfl?
+ cmpi.l %d0,&0x3fff-0x7ffe # would result ovfl?
beq.w fsglmul_may_ovfl # result may rnd to overflow
blt.w fsglmul_ovfl # result will overflow
- cmpi.l %d0,&0x3fff+0x0001 # would result unfl?
+ cmpi.l %d0,&0x3fff+0x0001 # would result unfl?
beq.w fsglmul_may_unfl # result may rnd to no unfl
bgt.w fsglmul_unfl # result will underflow
@@ -14073,7 +14073,7 @@ fsglmul_may_ovfl:
fmov.l &0x0,%fpsr # clear FPSR
fsglmul.x FP_SCR0(%a6),%fp0 # execute sgl multiply
-
+
fmov.l %fpsr,%d1 # save status
fmov.l &0x0,%fpcr # clear FPCR
@@ -14082,7 +14082,7 @@ fsglmul_may_ovfl:
fabs.x %fp0,%fp1 # make a copy of result
fcmp.b %fp1,&0x2 # is |result| >= 2.b?
fbge.w fsglmul_ovfl_tst # yes; overflow has occurred
-
+
# no, it didn't overflow; we have correct result
bra.w fsglmul_normal_exit
@@ -14116,7 +14116,7 @@ fsglmul_unfl_dis:
rts
#
-# UNFL is enabled.
+# UNFL is enabled.
#
fsglmul_unfl_ena:
fmovm.x FP_SCR1(%a6),&0x40 # load dst op
@@ -14124,7 +14124,7 @@ fsglmul_unfl_ena:
fmov.l L_SCR3(%a6),%fpcr # set FPCR
fmov.l &0x0,%fpsr # clear FPSR
- fsglmul.x FP_SCR0(%a6),%fp1 # execute sgl multiply
+ fsglmul.x FP_SCR0(%a6),%fp1 # execute sgl multiply
fmov.l &0x0,%fpcr # clear FPCR
@@ -14149,7 +14149,7 @@ fsglmul_may_unfl:
fmov.l L_SCR3(%a6),%fpcr # set FPCR
fmov.l &0x0,%fpsr # clear FPSR
- fsglmul.x FP_SCR0(%a6),%fp0 # execute sgl multiply
+ fsglmul.x FP_SCR0(%a6),%fp0 # execute sgl multiply
fmov.l %fpsr,%d1 # save status
fmov.l &0x0,%fpcr # clear FPCR
@@ -14173,11 +14173,11 @@ fsglmul_may_unfl:
mov.l L_SCR3(%a6),%d1
andi.b &0xc0,%d1 # keep rnd prec
ori.b &rz_mode*0x10,%d1 # insert RZ
-
+
fmov.l %d1,%fpcr # set FPCR
fmov.l &0x0,%fpsr # clear FPSR
- fsglmul.x FP_SCR0(%a6),%fp1 # execute sgl multiply
+ fsglmul.x FP_SCR0(%a6),%fp1 # execute sgl multiply
fmov.l &0x0,%fpcr # clear FPCR
fabs.x %fp1 # make absolute value
@@ -14265,15 +14265,15 @@ fsglmul_inf_dst:
#########################################################################
# XDEF **************************************************************** #
-# fsgldiv(): emulates the fsgldiv instruction #
+# fsgldiv(): emulates the fsgldiv instruction #
# #
# XREF **************************************************************** #
# scale_to_zero_src() - scale src exponent to zero #
# scale_to_zero_dst() - scale dst exponent to zero #
# unf_res4() - return default underflow result for sglop #
# ovf_res() - return default overflow result #
-# res_qnan() - return QNAN result #
-# res_snan() - return SNAN result #
+# res_qnan() - return QNAN result #
+# res_snan() - return SNAN result #
# #
# INPUT *************************************************************** #
# a0 = pointer to extended precision source operand #
@@ -14291,7 +14291,7 @@ fsglmul_inf_dst:
# instruction won't cause an exception. Use the regular fsgldiv to #
# compute a result. Check if the regular operands would have taken #
# an exception. If so, return the default overflow/underflow result #
-# and return the EXOP if exceptions are enabled. Else, scale the #
+# and return the EXOP if exceptions are enabled. Else, scale the #
# result operand to the proper exponent. #
# #
#########################################################################
@@ -14306,7 +14306,7 @@ fsgldiv:
or.b STAG(%a6),%d1 # combine src tags
bne.w fsgldiv_not_norm # optimize on non-norm input
-
+
#
# DIVIDE: NORMs and DENORMs ONLY!
#
@@ -14333,7 +14333,7 @@ fsgldiv_norm:
cmpi.l %d0,&0x3fff-0x7ffe
ble.w fsgldiv_may_ovfl
- cmpi.l %d0,&0x3fff-0x0000 # will result underflow?
+ cmpi.l %d0,&0x3fff-0x0000 # will result underflow?
beq.w fsgldiv_may_unfl # maybe
bgt.w fsgldiv_unfl # yes; go handle underflow
@@ -14393,7 +14393,7 @@ fsgldiv_ovfl_tst:
bne.b fsgldiv_ovfl_ena # yes
fsgldiv_ovfl_dis:
- btst &neg_bit,FPSR_CC(%a6) # is result negative
+ btst &neg_bit,FPSR_CC(%a6) # is result negative
sne %d1 # set sign param accordingly
mov.l L_SCR3(%a6),%d0 # pass prec:rnd
andi.b &0x30,%d0 # kill precision
@@ -14449,7 +14449,7 @@ fsgldiv_unfl_dis:
rts
#
-# UNFL is enabled.
+# UNFL is enabled.
#
fsgldiv_unfl_ena:
fmovm.x FP_SCR1(%a6),&0x40 # load dst op
@@ -14500,8 +14500,8 @@ fsgldiv_may_unfl:
#
# we still don't know if underflow occurred. result is ~ equal to 1. but,
# we don't know if the result was an underflow that rounded up to a 1
-# or a normalized number that rounded down to a 1. so, redo the entire
-# operation using RZ as the rounding mode to see what the pre-rounded
+# or a normalized number that rounded down to a 1. so, redo the entire
+# operation using RZ as the rounding mode to see what the pre-rounded
# result is. this case should be relatively rare.
#
fmovm.x FP_SCR1(%a6),&0x40 # load dst op into %fp1
@@ -14605,25 +14605,25 @@ fsgldiv_inf_dst:
# fdadd(): emulates the fdadd instruction #
# #
# XREF **************************************************************** #
-# addsub_scaler2() - scale the operands so they won't take exc #
+# addsub_scaler2() - scale the operands so they won't take exc #
# ovf_res() - return default overflow result #
# unf_res() - return default underflow result #
# res_qnan() - set QNAN result #
-# res_snan() - set SNAN result #
+# res_snan() - set SNAN result #
# res_operr() - set OPERR result #
# scale_to_zero_src() - set src operand exponent equal to zero #
# scale_to_zero_dst() - set dst operand exponent equal to zero #
# #
# INPUT *************************************************************** #
# a0 = pointer to extended precision source operand #
-# a1 = pointer to extended precision destination operand #
+# a1 = pointer to extended precision destination operand #
# #
# OUTPUT ************************************************************** #
# fp0 = result #
# fp1 = EXOP (if exception occurred) #
# #
# ALGORITHM *********************************************************** #
-# Handle NANs, infinities, and zeroes as special cases. Divide #
+# Handle NANs, infinities, and zeroes as special cases. Divide #
# norms into extended, single, and double precision. #
# Do addition after scaling exponents such that exception won't #
# occur. Then, check result exponent to see if exception would have #
@@ -14837,7 +14837,7 @@ fadd_unfl_ena_sd:
#
# result is equal to the smallest normalized number in the selected precision
-# if the precision is extended, this result could not have come from an
+# if the precision is extended, this result could not have come from an
# underflow that rounded up.
#
fadd_may_unfl:
@@ -14859,7 +14859,7 @@ fadd_may_unfl:
# ok, so now the result has a exponent equal to the smallest normalized
# exponent for the selected precision. also, the mantissa is equal to
# 0x8000000000000000 and this mantissa is the result of rounding non-zero
-# g,r,s.
+# g,r,s.
# now, we must determine whether the pre-rounded result was an underflow
# rounded "up" or a normalized number rounded "down".
# so, we do this be re-executing the add using RZ as the rounding mode and
@@ -14970,7 +14970,7 @@ fadd_zero_2:
fmov.s &0x00000000,%fp0 # return +ZERO
mov.b &z_bmask,FPSR_CC(%a6) # set Z
rts
-
+
#
# the ZEROes have opposite signs:
# - therefore, we return +ZERO if the rounding modes are RN,RZ, or RP.
@@ -15024,7 +15024,7 @@ fadd_inf_2:
eor.b %d1,%d0
bmi.l res_operr # weed out (-INF)+(+INF)
-# ok, so it's not an OPERR. but, we do have to remember to return the
+# ok, so it's not an OPERR. but, we do have to remember to return the
# src INF since that's where the 881/882 gets the j-bit from...
#
@@ -15058,25 +15058,25 @@ fadd_inf_done:
# fdsub(): emulates the fdsub instruction #
# #
# XREF **************************************************************** #
-# addsub_scaler2() - scale the operands so they won't take exc #
+# addsub_scaler2() - scale the operands so they won't take exc #
# ovf_res() - return default overflow result #
# unf_res() - return default underflow result #
# res_qnan() - set QNAN result #
-# res_snan() - set SNAN result #
+# res_snan() - set SNAN result #
# res_operr() - set OPERR result #
# scale_to_zero_src() - set src operand exponent equal to zero #
# scale_to_zero_dst() - set dst operand exponent equal to zero #
# #
# INPUT *************************************************************** #
# a0 = pointer to extended precision source operand #
-# a1 = pointer to extended precision destination operand #
+# a1 = pointer to extended precision destination operand #
# #
# OUTPUT ************************************************************** #
# fp0 = result #
# fp1 = EXOP (if exception occurred) #
# #
# ALGORITHM *********************************************************** #
-# Handle NANs, infinities, and zeroes as special cases. Divide #
+# Handle NANs, infinities, and zeroes as special cases. Divide #
# norms into extended, single, and double precision. #
# Do subtraction after scaling exponents such that exception won't#
# occur. Then, check result exponent to see if exception would have #
@@ -15226,7 +15226,7 @@ fsub_unfl:
add.l &0xc,%sp
fmovm.x FP_SCR1(%a6),&0x80 # load dst op
-
+
fmov.l &rz_mode*0x10,%fpcr # set FPCR
fmov.l &0x0,%fpsr # clear FPSR
@@ -15290,7 +15290,7 @@ fsub_unfl_ena_sd:
#
# result is equal to the smallest normalized number in the selected precision
-# if the precision is extended, this result could not have come from an
+# if the precision is extended, this result could not have come from an
# underflow that rounded up.
#
fsub_may_unfl:
@@ -15312,7 +15312,7 @@ fsub_may_unfl:
# ok, so now the result has a exponent equal to the smallest normalized
# exponent for the selected precision. also, the mantissa is equal to
# 0x8000000000000000 and this mantissa is the result of rounding non-zero
-# g,r,s.
+# g,r,s.
# now, we must determine whether the pre-rounded result was an underflow
# rounded "up" or a normalized number rounded "down".
# so, we do this be re-executing the add using RZ as the rounding mode and
@@ -15468,7 +15468,7 @@ fsub_zero_src:
#
# both operands are INFs. an OPERR will result if the INFs have the
-# same signs. else,
+# same signs. else,
#
fsub_inf_2:
mov.b SRC_EX(%a0),%d0 # exclusive or the signs
@@ -15483,7 +15483,7 @@ fsub_inf_src:
fmovm.x SRC(%a0),&0x80 # return src INF
fneg.x %fp0 # invert sign
fbge.w fsub_inf_done # sign is now positive
- mov.b &neg_bmask+inf_bmask,FPSR_CC(%a6) # set INF/NEG
+ mov.b &neg_bmask+inf_bmask,FPSR_CC(%a6) # set INF/NEG
rts
fsub_inf_dst:
@@ -15499,7 +15499,7 @@ fsub_inf_done:
#########################################################################
# XDEF **************************************************************** #
-# fsqrt(): emulates the fsqrt instruction #
+# fsqrt(): emulates the fsqrt instruction #
# fssqrt(): emulates the fssqrt instruction #
# fdsqrt(): emulates the fdsqrt instruction #
# #
@@ -15507,8 +15507,8 @@ fsub_inf_done:
# scale_sqrt() - scale the source operand #
# unf_res() - return default underflow result #
# ovf_res() - return default overflow result #
-# res_qnan_1op() - return QNAN result #
-# res_snan_1op() - return SNAN result #
+# res_qnan_1op() - return QNAN result #
+# res_snan_1op() - return SNAN result #
# #
# INPUT *************************************************************** #
# a0 = pointer to extended precision source operand #
@@ -15525,7 +15525,7 @@ fsub_inf_done:
# instruction won't cause an exception. Use the regular fsqrt to #
# compute a result. Check if the regular operands would have taken #
# an exception. If so, return the default overflow/underflow result #
-# and return the EXOP if exceptions are enabled. Else, scale the #
+# and return the EXOP if exceptions are enabled. Else, scale the #
# result operand to the proper exponent. #
# #
#########################################################################
@@ -15547,7 +15547,7 @@ fsqrt:
clr.w %d1
mov.b STAG(%a6),%d1
bne.w fsqrt_not_norm # optimize on non-norm input
-
+
#
# SQUARE ROOT: norms and denorms ONLY!
#
@@ -15669,7 +15669,7 @@ fsqrt_sd_unfl:
fmov.l &rz_mode*0x10,%fpcr # set FPCR
fmov.l &0x0,%fpsr # clear FPSR
- fsqrt.x FP_SCR0(%a6),%fp0 # execute square root
+ fsqrt.x FP_SCR0(%a6),%fp0 # execute square root
fmov.l %fpsr,%d1 # save status
fmov.l &0x0,%fpcr # clear FPCR
@@ -15689,10 +15689,10 @@ fsqrt_sd_unfl_dis:
bsr.l unf_res # calculate default result
or.b %d0,FPSR_CC(%a6) # set possible 'Z' ccode
fmovm.x FP_SCR0(%a6),&0x80 # return default result in fp0
- rts
+ rts
#
-# operand will underflow AND underflow is enabled.
+# operand will underflow AND underflow is enabled.
# therefore, we must return the result rounded to extended precision.
#
fsqrt_sd_unfl_ena:
@@ -15808,15 +15808,15 @@ fsqrt_not_norm:
bra.l res_qnan_1op
#
-# fsqrt(+0) = +0
-# fsqrt(-0) = -0
+# fsqrt(+0) = +0
+# fsqrt(-0) = -0
# fsqrt(+INF) = +INF
-# fsqrt(-INF) = OPERR
+# fsqrt(-INF) = OPERR
#
fsqrt_zero:
tst.b SRC_EX(%a0) # is ZERO positive or negative?
bmi.b fsqrt_zero_m # negative
-fsqrt_zero_p:
+fsqrt_zero_p:
fmov.s &0x00000000,%fp0 # return +ZERO
mov.b &z_bmask,FPSR_CC(%a6) # set 'Z' ccode bit
rts
@@ -15846,14 +15846,14 @@ fsqrt_inf_p:
# INPUT *************************************************************** #
# FP_SRC(a6) = fp op1(src) #
# FP_DST(a6) = fp op2(dst) #
-# #
+# #
# OUTPUT ************************************************************** #
# FP_SRC(a6) = fp op1 scaled(src) #
# FP_DST(a6) = fp op2 scaled(dst) #
# d0 = scale amount #
# #
# ALGORITHM *********************************************************** #
-# If the DST exponent is > the SRC exponent, set the DST exponent #
+# If the DST exponent is > the SRC exponent, set the DST exponent #
# equal to 0x3fff and scale the SRC exponent by the value that the #
# DST exponent was scaled by. If the SRC exponent is greater or equal, #
# do the opposite. Return this scale factor in d0. #
@@ -15916,7 +15916,7 @@ quick_scale12:
andi.w &0x8000,FP_SCR0_EX(%a6) # zero src exponent
bset &0x0,1+FP_SCR0_EX(%a6) # set exp = 1
- mov.l (%sp)+,%d0 # return SCALE factor
+ mov.l (%sp)+,%d0 # return SCALE factor
rts
# src exp is >= dst exp; scale src to exp = 0x3fff
@@ -15952,7 +15952,7 @@ quick_scale22:
andi.w &0x8000,FP_SCR1_EX(%a6) # zero dst exponent
bset &0x0,1+FP_SCR1_EX(%a6) # set exp = 1
- mov.l (%sp)+,%d0 # return SCALE factor
+ mov.l (%sp)+,%d0 # return SCALE factor
rts
##########################################################################
@@ -15967,14 +15967,14 @@ quick_scale22:
# #
# INPUT *************************************************************** #
# FP_SCR0(a6) = extended precision operand to be scaled #
-# #
+# #
# OUTPUT ************************************************************** #
# FP_SCR0(a6) = scaled extended precision operand #
# d0 = scale value #
# #
# ALGORITHM *********************************************************** #
-# Set the exponent of the input operand to 0x3fff. Save the value #
-# of the difference between the original and new exponent. Then, #
+# Set the exponent of the input operand to 0x3fff. Save the value #
+# of the difference between the original and new exponent. Then, #
# normalize the operand if it was a DENORM. Add this normalization #
# value to the previous value. Return the result. #
# #
@@ -16020,17 +16020,17 @@ stzs_denorm:
# #
# INPUT *************************************************************** #
# FP_SCR0(a6) = extended precision operand to be scaled #
-# #
+# #
# OUTPUT ************************************************************** #
# FP_SCR0(a6) = scaled extended precision operand #
# d0 = scale value #
# #
# ALGORITHM *********************************************************** #
# If the input operand is a DENORM, normalize it. #
-# If the exponent of the input operand is even, set the exponent #
-# to 0x3ffe and return a scale factor of "(exp-0x3ffe)/2". If the #
+# If the exponent of the input operand is even, set the exponent #
+# to 0x3ffe and return a scale factor of "(exp-0x3ffe)/2". If the #
# exponent of the input operand is off, set the exponent to ox3fff and #
-# return a scale factor of "(exp-0x3fff)/2". #
+# return a scale factor of "(exp-0x3fff)/2". #
# #
#########################################################################
@@ -16094,14 +16094,14 @@ ss_denorm_even:
# #
# INPUT *************************************************************** #
# FP_SCR1(a6) = extended precision operand to be scaled #
-# #
+# #
# OUTPUT ************************************************************** #
# FP_SCR1(a6) = scaled extended precision operand #
# d0 = scale value #
# #
# ALGORITHM *********************************************************** #
-# Set the exponent of the input operand to 0x3fff. Save the value #
-# of the difference between the original and new exponent. Then, #
+# Set the exponent of the input operand to 0x3fff. Save the value #
+# of the difference between the original and new exponent. Then, #
# normalize the operand if it was a DENORM. Add this normalization #
# value to the previous value. Return the result. #
# #
@@ -16149,21 +16149,21 @@ stzd_denorm:
# INPUT *************************************************************** #
# FP_SRC(a6) = pointer to extended precision src operand #
# FP_DST(a6) = pointer to extended precision dst operand #
-# #
+# #
# OUTPUT ************************************************************** #
# fp0 = default result #
# #
# ALGORITHM *********************************************************** #
-# If either operand (but not both operands) of an operation is a #
+# If either operand (but not both operands) of an operation is a #
# nonsignalling NAN, then that NAN is returned as the result. If both #
-# operands are nonsignalling NANs, then the destination operand #
+# operands are nonsignalling NANs, then the destination operand #
# nonsignalling NAN is returned as the result. #
-# If either operand to an operation is a signalling NAN (SNAN), #
+# If either operand to an operation is a signalling NAN (SNAN), #
# then, the SNAN bit is set in the FPSR EXC byte. If the SNAN trap #
-# enable bit is set in the FPCR, then the trap is taken and the #
+# enable bit is set in the FPCR, then the trap is taken and the #
# destination is not modified. If the SNAN trap enable bit is not set, #
-# then the SNAN is converted to a nonsignalling NAN (by setting the #
-# SNAN bit in the operand to one), and the operation continues as #
+# then the SNAN is converted to a nonsignalling NAN (by setting the #
+# SNAN bit in the operand to one), and the operation continues as #
# described in the preceding paragraph, for nonsignalling NANs. #
# Make sure the appropriate FPSR bits are set before exiting. #
# #
@@ -16202,7 +16202,7 @@ dst_qnan2:
lea FP_DST(%a6), %a0
cmp.b STAG(%a6), &SNAN
bne nan_done
- or.l &aiop_mask+snan_mask, USER_FPSR(%a6)
+ or.l &aiop_mask+snan_mask, USER_FPSR(%a6)
nan_done:
or.l &nan_mask, USER_FPSR(%a6)
nan_comp:
@@ -16215,14 +16215,14 @@ nan_not_neg:
#########################################################################
# XDEF **************************************************************** #
-# res_operr(): return default result during operand error #
+# res_operr(): return default result during operand error #
# #
# XREF **************************************************************** #
# None #
# #
# INPUT *************************************************************** #
# None #
-# #
+# #
# OUTPUT ************************************************************** #
# fp0 = default operand error result #
# #
@@ -16230,8 +16230,8 @@ nan_not_neg:
# An nonsignalling NAN is returned as the default result when #
# an operand error occurs for the following cases: #
# #
-# Multiply: (Infinity x Zero) #
-# Divide : (Zero / Zero) || (Infinity / Infinity) #
+# Multiply: (Infinity x Zero) #
+# Divide : (Zero / Zero) || (Infinity / Infinity) #
# #
#########################################################################
@@ -16241,7 +16241,7 @@ res_operr:
fmovm.x nan_return(%pc), &0x80
rts
-nan_return:
+nan_return:
long 0x7fff0000, 0xffffffff, 0xffffffff
#########################################################################
@@ -16268,7 +16268,7 @@ nan_return:
# or false. #
# If a BSUN exception should be indicated, the BSUN and ABSUN #
# bits are set in the stacked FPSR. If the BSUN exception is enabled, #
-# the fbsun_flg is set in the SPCOND_FLG location on the stack. If an #
+# the fbsun_flg is set in the SPCOND_FLG location on the stack. If an #
# enabled BSUN should not be flagged and the predicate is true, then #
# Dn is fetched and decremented by one. If Dn is not equal to -1, add #
# the displacement value to the stacked PC so that when an "rte" is #
@@ -16286,7 +16286,7 @@ _fdbcc:
ror.l &0x8,%d1 # rotate to top byte
fmov.l %d1,%fpsr # insert into FPSR
- mov.w (tbl_fdbcc.b,%pc,%d0.w*2),%d1 # load table
+ mov.w (tbl_fdbcc.b,%pc,%d0.w*2),%d1 # load table
jmp (tbl_fdbcc.b,%pc,%d1.w) # jump to fdbcc routine
tbl_fdbcc:
@@ -16327,7 +16327,7 @@ tbl_fdbcc:
# #
# IEEE Nonaware tests #
# #
-# For the IEEE nonaware tests, only the false branch changes the #
+# For the IEEE nonaware tests, only the false branch changes the #
# counter. However, the true branch may set bsun so we check to see #
# if the NAN bit is set, in which case BSUN and AIOP will be set. #
# #
@@ -16376,7 +16376,7 @@ fdbcc_gt:
beq.w fdbcc_false # no;go handle counter
ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
- bne.w fdbcc_bsun # yes; we have an exception
+ bne.w fdbcc_bsun # yes; we have an exception
bra.w fdbcc_false # no; go handle counter
fdbcc_gt_yes:
rts # do nothing
@@ -16384,7 +16384,7 @@ fdbcc_gt_yes:
#
# not greater than:
#
-# NANvZvN
+# NANvZvN
#
fdbcc_ngt:
fbngt.w fdbcc_ngt_yes # not greater than?
@@ -16395,7 +16395,7 @@ fdbcc_ngt_yes:
beq.b fdbcc_ngt_done # no;go finish
ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
- bne.w fdbcc_bsun # yes; we have an exception
+ bne.w fdbcc_bsun # yes; we have an exception
fdbcc_ngt_done:
rts # no; do nothing
@@ -16411,14 +16411,14 @@ fdbcc_ge_no:
beq.w fdbcc_false # no;go handle counter
ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
- bne.w fdbcc_bsun # yes; we have an exception
+ bne.w fdbcc_bsun # yes; we have an exception
bra.w fdbcc_false # no; go handle counter
fdbcc_ge_yes:
btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
beq.b fdbcc_ge_yes_done # no;go do nothing
ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
- bne.w fdbcc_bsun # yes; we have an exception
+ bne.w fdbcc_bsun # yes; we have an exception
fdbcc_ge_yes_done:
rts # do nothing
@@ -16436,7 +16436,7 @@ fdbcc_nge_yes:
beq.b fdbcc_nge_done # no;go finish
ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
- bne.w fdbcc_bsun # yes; we have an exception
+ bne.w fdbcc_bsun # yes; we have an exception
fdbcc_nge_done:
rts # no; do nothing
@@ -16452,7 +16452,7 @@ fdbcc_lt_no:
beq.w fdbcc_false # no; go handle counter
ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
- bne.w fdbcc_bsun # yes; we have an exception
+ bne.w fdbcc_bsun # yes; we have an exception
bra.w fdbcc_false # no; go handle counter
fdbcc_lt_yes:
rts # do nothing
@@ -16471,7 +16471,7 @@ fdbcc_nlt_yes:
beq.b fdbcc_nlt_done # no;go finish
ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
- bne.w fdbcc_bsun # yes; we have an exception
+ bne.w fdbcc_bsun # yes; we have an exception
fdbcc_nlt_done:
rts # no; do nothing
@@ -16487,14 +16487,14 @@ fdbcc_le_no:
beq.w fdbcc_false # no; go handle counter
ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
- bne.w fdbcc_bsun # yes; we have an exception
+ bne.w fdbcc_bsun # yes; we have an exception
bra.w fdbcc_false # no; go handle counter
fdbcc_le_yes:
btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
beq.b fdbcc_le_yes_done # no; go do nothing
ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
- bne.w fdbcc_bsun # yes; we have an exception
+ bne.w fdbcc_bsun # yes; we have an exception
fdbcc_le_yes_done:
rts # do nothing
@@ -16611,7 +16611,7 @@ fdbcc_t: # no bsun possible
# False
#
fdbcc_sf:
- btst &nan_bit, FPSR_CC(%a6) # is NAN set?
+ btst &nan_bit, FPSR_CC(%a6) # is NAN set?
beq.w fdbcc_false # no;go handle counter
ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
@@ -16624,7 +16624,7 @@ fdbcc_sf:
# True
#
fdbcc_st:
- btst &nan_bit, FPSR_CC(%a6) # is NAN set?
+ btst &nan_bit, FPSR_CC(%a6) # is NAN set?
beq.b fdbcc_st_done # no;go finish
ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
@@ -16640,14 +16640,14 @@ fdbcc_st_done:
fdbcc_seq:
fbseq.w fdbcc_seq_yes # signalling equal?
fdbcc_seq_no:
- btst &nan_bit, FPSR_CC(%a6) # is NAN set?
+ btst &nan_bit, FPSR_CC(%a6) # is NAN set?
beq.w fdbcc_false # no;go handle counter
ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
bne.w fdbcc_bsun # yes; we have an exception
bra.w fdbcc_false # go handle counter
fdbcc_seq_yes:
- btst &nan_bit, FPSR_CC(%a6) # is NAN set?
+ btst &nan_bit, FPSR_CC(%a6) # is NAN set?
beq.b fdbcc_seq_yes_done # no;go do nothing
ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
@@ -16663,14 +16663,14 @@ fdbcc_seq_yes_done:
fdbcc_sneq:
fbsneq.w fdbcc_sneq_yes # signalling not equal?
fdbcc_sneq_no:
- btst &nan_bit, FPSR_CC(%a6) # is NAN set?
+ btst &nan_bit, FPSR_CC(%a6) # is NAN set?
beq.w fdbcc_false # no;go handle counter
ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
bne.w fdbcc_bsun # yes; we have an exception
bra.w fdbcc_false # go handle counter
fdbcc_sneq_yes:
- btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
+ btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
beq.w fdbcc_sneq_done # no;go finish
ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
btst &bsun_bit, FPCR_ENABLE(%a6) # is BSUN enabled?
@@ -16684,7 +16684,7 @@ fdbcc_sneq_done:
# #
# For the IEEE aware tests, action is only taken if the result is false.#
# Therefore, the opposite branch type is used to jump to the decrement #
-# routine. #
+# routine. #
# The BSUN exception will not be set for any of these tests. #
# #
#########################################################################
@@ -16845,7 +16845,7 @@ fdbcc_un_yes:
# pc += sign_ext(16-bit displacement)
#
fdbcc_false:
- mov.b 1+EXC_OPWORD(%a6), %d1 # fetch lo opword
+ mov.b 1+EXC_OPWORD(%a6), %d1 # fetch lo opword
andi.w &0x7, %d1 # extract count register
bsr.l fetch_dreg # fetch count value
@@ -16856,7 +16856,7 @@ fdbcc_false:
bsr.l store_dreg_l # store new count value
cmpi.w %d0, &-0x1 # is (Dn == -1)?
- bne.b fdbcc_false_cont # no;
+ bne.b fdbcc_false_cont # no;
rts
fdbcc_false_cont:
@@ -16897,7 +16897,7 @@ fdbcc_bsun:
# or false. #
# If a BSUN exception should be indicated, the BSUN and ABSUN #
# bits are set in the stacked FPSR. If the BSUN exception is enabled, #
-# the fbsun_flg is set in the SPCOND_FLG location on the stack. If an #
+# the fbsun_flg is set in the SPCOND_FLG location on the stack. If an #
# enabled BSUN should not be flagged and the predicate is true, then #
# the ftrapcc_flg is set in the SPCOND_FLG location. These special #
# flags indicate to the calling routine to emulate the exceptional #
@@ -16914,7 +16914,7 @@ _ftrapcc:
ror.l &0x8,%d1 # rotate to top byte
fmov.l %d1,%fpsr # insert into FPSR
- mov.w (tbl_ftrapcc.b,%pc,%d0.w*2), %d1 # load table
+ mov.w (tbl_ftrapcc.b,%pc,%d0.w*2), %d1 # load table
jmp (tbl_ftrapcc.b,%pc,%d1.w) # jump to ftrapcc routine
tbl_ftrapcc:
@@ -17006,7 +17006,7 @@ ftrapcc_gt_done:
#
# not greater than:
#
-# NANvZvN
+# NANvZvN
#
ftrapcc_ngt:
fbngt.w ftrapcc_ngt_yes # not greater than?
@@ -17226,7 +17226,7 @@ ftrapcc_t:
# False
#
ftrapcc_sf:
- btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
+ btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
beq.b ftrapcc_sf_done # no; go finish
ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
btst &bsun_bit, FPCR_ENABLE(%a6) # was BSUN set?
@@ -17240,7 +17240,7 @@ ftrapcc_sf_done:
# True
#
ftrapcc_st:
- btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
+ btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
beq.w ftrapcc_trap # no; go take trap
ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
btst &bsun_bit, FPCR_ENABLE(%a6) # was BSUN set?
@@ -17255,7 +17255,7 @@ ftrapcc_st:
ftrapcc_seq:
fbseq.w ftrapcc_seq_yes # signalling equal?
ftrapcc_seq_no:
- btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
+ btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
beq.w ftrapcc_seq_done # no; go finish
ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
btst &bsun_bit, FPCR_ENABLE(%a6) # was BSUN set?
@@ -17263,7 +17263,7 @@ ftrapcc_seq_no:
ftrapcc_seq_done:
rts # no; do nothing
ftrapcc_seq_yes:
- btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
+ btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
beq.w ftrapcc_trap # no; go take trap
ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
btst &bsun_bit, FPCR_ENABLE(%a6) # was BSUN set?
@@ -17278,7 +17278,7 @@ ftrapcc_seq_yes:
ftrapcc_sneq:
fbsneq.w ftrapcc_sneq_yes # signalling equal?
ftrapcc_sneq_no:
- btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
+ btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
beq.w ftrapcc_sneq_no_done # no; go finish
ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
btst &bsun_bit, FPCR_ENABLE(%a6) # was BSUN set?
@@ -17286,7 +17286,7 @@ ftrapcc_sneq_no:
ftrapcc_sneq_no_done:
rts # do nothing
ftrapcc_sneq_yes:
- btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
+ btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
beq.w ftrapcc_trap # no; go take trap
ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
btst &bsun_bit, FPCR_ENABLE(%a6) # was BSUN set?
@@ -17469,7 +17469,7 @@ ftrapcc_bsun:
# or false. #
# If a BSUN exception should be indicated, the BSUN and ABSUN #
# bits are set in the stacked FPSR. If the BSUN exception is enabled, #
-# the fbsun_flg is set in the SPCOND_FLG location on the stack. If an #
+# the fbsun_flg is set in the SPCOND_FLG location on the stack. If an #
# enabled BSUN should not be flagged and the predicate is true, then #
# the result is stored to the data register file or memory #
# #
@@ -17484,8 +17484,8 @@ _fscc:
ror.l &0x8,%d1 # rotate to top byte
fmov.l %d1,%fpsr # insert into FPSR
- mov.w (tbl_fscc.b,%pc,%d0.w*2),%d1 # load table
- jmp (tbl_fscc.b,%pc,%d1.w) # jump to fscc routine
+ mov.w (tbl_fscc.b,%pc,%d0.w*2),%d1 # load table
+ jmp (tbl_fscc.b,%pc,%d1.w) # jump to fscc routine
tbl_fscc:
short fscc_f - tbl_fscc # 00
@@ -17585,7 +17585,7 @@ fscc_gt_yes:
#
# not greater than:
#
-# NANvZvN
+# NANvZvN
#
fscc_ngt:
fbngt.w fscc_ngt_yes # not greater than?
@@ -17613,7 +17613,7 @@ fscc_ge_no:
ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
bra.w fscc_chk_bsun # go finish
fscc_ge_yes:
- st %d0 # set true
+ st %d0 # set true
btst &nan_bit, FPSR_CC(%a6) # is NAN set in cc?
beq.w fscc_done # no;go finish
ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
@@ -17806,7 +17806,7 @@ fscc_t:
#
fscc_sf:
clr.b %d0 # set false
- btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
+ btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
beq.w fscc_done # no;go finish
ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
bra.w fscc_chk_bsun # go finish
@@ -17818,7 +17818,7 @@ fscc_sf:
#
fscc_st:
st %d0 # set false
- btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
+ btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
beq.w fscc_done # no;go finish
ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
bra.w fscc_chk_bsun # go finish
@@ -17832,13 +17832,13 @@ fscc_seq:
fbseq.w fscc_seq_yes # signalling equal?
fscc_seq_no:
clr.b %d0 # set false
- btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
+ btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
beq.w fscc_done # no;go finish
ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
bra.w fscc_chk_bsun # go finish
fscc_seq_yes:
st %d0 # set true
- btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
+ btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
beq.w fscc_done # no;go finish
ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
bra.w fscc_chk_bsun # go finish
@@ -17852,13 +17852,13 @@ fscc_sneq:
fbsneq.w fscc_sneq_yes # signalling equal?
fscc_sneq_no:
clr.b %d0 # set false
- btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
+ btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
beq.w fscc_done # no;go finish
ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
bra.w fscc_chk_bsun # go finish
fscc_sneq_yes:
st %d0 # set true
- btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
+ btst &nan_bit, FPSR_CC(%a6) # set BSUN exc bit
beq.w fscc_done # no;go finish
ori.l &bsun_mask+aiop_mask, USER_FPSR(%a6) # set BSUN exc bit
bra.w fscc_chk_bsun # go finish
@@ -18044,7 +18044,7 @@ fscc_un_yes:
#######################################################################
#
-# the bsun exception bit was set. now, check to see is BSUN
+# the bsun exception bit was set. now, check to see is BSUN
# is enabled. if so, don't store result and correct stack frame
# for a bsun exception.
#
@@ -18061,7 +18061,7 @@ fscc_chk_bsun:
fscc_done:
mov.l %d0,%a0 # save result for a moment
- mov.b 1+EXC_OPWORD(%a6),%d1 # fetch lo opword
+ mov.b 1+EXC_OPWORD(%a6),%d1 # fetch lo opword
mov.l %d1,%d0 # make a copy
andi.b &0x38,%d1 # extract src mode
@@ -18075,7 +18075,7 @@ fscc_done:
#
# the stacked <ea> is correct with the exception of:
-# -> Dn : <ea> is garbage
+# -> Dn : <ea> is garbage
#
# if the addressing mode is post-increment or pre-decrement,
# then the address registers have not been updated.
@@ -18088,7 +18088,7 @@ fscc_mem_op:
mov.l %a0,%d0 # pass result in d0
mov.l EXC_EA(%a6),%a0 # fetch <ea>
- bsr.l _dmem_write_byte # write result byte
+ bsr.l _dmem_write_byte # write result byte
tst.l %d1 # did dstore fail?
bne.w fscc_err # yes
@@ -18159,7 +18159,7 @@ fscc_err:
# #
# INPUT *************************************************************** #
# None #
-# #
+# #
# OUTPUT ************************************************************** #
# If instr is "fmovm Dn,-(A7)" from supervisor mode, #
# d0 = size of dump #
@@ -18181,25 +18181,25 @@ fscc_err:
# The data register is determined and its value loaded to get the #
# string of FP registers affected. This value is used as an index into #
# a lookup table such that we can determine the number of bytes #
-# involved. #
+# involved. #
# If the instruction is "fmovm.x <ea>,Dn", a _mem_read() is used #
# to read in all FP values. Again, _mem_read() may fail and require a #
-# special exit. #
+# special exit. #
# If the instruction is "fmovm.x DN,<ea>", a _mem_write() is used #
# to write all FP values. _mem_write() may also fail. #
-# If the instruction is "fmovm.x DN,-(a7)" from supervisor mode, #
+# If the instruction is "fmovm.x DN,-(a7)" from supervisor mode, #
# then we return the size of the dump and the string to the caller #
# so that the move can occur outside of this routine. This special #
# case is required so that moves to the system stack are handled #
# correctly. #
# #
# DYNAMIC: #
-# fmovm.x dn, <ea> #
-# fmovm.x <ea>, dn #
+# fmovm.x dn, <ea> #
+# fmovm.x <ea>, dn #
# #
# <WORD 1> <WORD2> #
# 1111 0010 00 |<ea>| 11@& 1000 0$$$ 0000 #
-# #
+# #
# & = (0): predecrement addressing mode #
# (1): postincrement or control addressing mode #
# @ = (0): move listed regs from memory to the FPU #
@@ -18468,12 +18468,12 @@ tbl_fmovm_size:
byte 0x24,0x30,0x30,0x3c,0x30,0x3c,0x3c,0x48
byte 0x30,0x3c,0x3c,0x48,0x3c,0x48,0x48,0x54
byte 0x30,0x3c,0x3c,0x48,0x3c,0x48,0x48,0x54
- byte 0x3c,0x48,0x48,0x54,0x48,0x54,0x54,0x60
+ byte 0x3c,0x48,0x48,0x54,0x48,0x54,0x54,0x60
#
# table to convert a pre-decrement bit string into a post-increment
# or control bit string.
-# ex: 0x00 ==> 0x00
+# ex: 0x00 ==> 0x00
# 0x01 ==> 0x80
# 0x02 ==> 0x40
# .
@@ -18555,59 +18555,59 @@ tbl_fea_mode:
short tbl_fea_mode - tbl_fea_mode
short tbl_fea_mode - tbl_fea_mode
- short faddr_ind_a0 - tbl_fea_mode
- short faddr_ind_a1 - tbl_fea_mode
- short faddr_ind_a2 - tbl_fea_mode
- short faddr_ind_a3 - tbl_fea_mode
- short faddr_ind_a4 - tbl_fea_mode
- short faddr_ind_a5 - tbl_fea_mode
- short faddr_ind_a6 - tbl_fea_mode
- short faddr_ind_a7 - tbl_fea_mode
-
- short faddr_ind_p_a0 - tbl_fea_mode
- short faddr_ind_p_a1 - tbl_fea_mode
- short faddr_ind_p_a2 - tbl_fea_mode
- short faddr_ind_p_a3 - tbl_fea_mode
- short faddr_ind_p_a4 - tbl_fea_mode
- short faddr_ind_p_a5 - tbl_fea_mode
- short faddr_ind_p_a6 - tbl_fea_mode
- short faddr_ind_p_a7 - tbl_fea_mode
-
- short faddr_ind_m_a0 - tbl_fea_mode
- short faddr_ind_m_a1 - tbl_fea_mode
- short faddr_ind_m_a2 - tbl_fea_mode
- short faddr_ind_m_a3 - tbl_fea_mode
- short faddr_ind_m_a4 - tbl_fea_mode
- short faddr_ind_m_a5 - tbl_fea_mode
- short faddr_ind_m_a6 - tbl_fea_mode
- short faddr_ind_m_a7 - tbl_fea_mode
-
- short faddr_ind_disp_a0 - tbl_fea_mode
- short faddr_ind_disp_a1 - tbl_fea_mode
- short faddr_ind_disp_a2 - tbl_fea_mode
- short faddr_ind_disp_a3 - tbl_fea_mode
- short faddr_ind_disp_a4 - tbl_fea_mode
- short faddr_ind_disp_a5 - tbl_fea_mode
- short faddr_ind_disp_a6 - tbl_fea_mode
+ short faddr_ind_a0 - tbl_fea_mode
+ short faddr_ind_a1 - tbl_fea_mode
+ short faddr_ind_a2 - tbl_fea_mode
+ short faddr_ind_a3 - tbl_fea_mode
+ short faddr_ind_a4 - tbl_fea_mode
+ short faddr_ind_a5 - tbl_fea_mode
+ short faddr_ind_a6 - tbl_fea_mode
+ short faddr_ind_a7 - tbl_fea_mode
+
+ short faddr_ind_p_a0 - tbl_fea_mode
+ short faddr_ind_p_a1 - tbl_fea_mode
+ short faddr_ind_p_a2 - tbl_fea_mode
+ short faddr_ind_p_a3 - tbl_fea_mode
+ short faddr_ind_p_a4 - tbl_fea_mode
+ short faddr_ind_p_a5 - tbl_fea_mode
+ short faddr_ind_p_a6 - tbl_fea_mode
+ short faddr_ind_p_a7 - tbl_fea_mode
+
+ short faddr_ind_m_a0 - tbl_fea_mode
+ short faddr_ind_m_a1 - tbl_fea_mode
+ short faddr_ind_m_a2 - tbl_fea_mode
+ short faddr_ind_m_a3 - tbl_fea_mode
+ short faddr_ind_m_a4 - tbl_fea_mode
+ short faddr_ind_m_a5 - tbl_fea_mode
+ short faddr_ind_m_a6 - tbl_fea_mode
+ short faddr_ind_m_a7 - tbl_fea_mode
+
+ short faddr_ind_disp_a0 - tbl_fea_mode
+ short faddr_ind_disp_a1 - tbl_fea_mode
+ short faddr_ind_disp_a2 - tbl_fea_mode
+ short faddr_ind_disp_a3 - tbl_fea_mode
+ short faddr_ind_disp_a4 - tbl_fea_mode
+ short faddr_ind_disp_a5 - tbl_fea_mode
+ short faddr_ind_disp_a6 - tbl_fea_mode
short faddr_ind_disp_a7 - tbl_fea_mode
- short faddr_ind_ext - tbl_fea_mode
- short faddr_ind_ext - tbl_fea_mode
- short faddr_ind_ext - tbl_fea_mode
- short faddr_ind_ext - tbl_fea_mode
- short faddr_ind_ext - tbl_fea_mode
- short faddr_ind_ext - tbl_fea_mode
- short faddr_ind_ext - tbl_fea_mode
- short faddr_ind_ext - tbl_fea_mode
-
- short fabs_short - tbl_fea_mode
- short fabs_long - tbl_fea_mode
- short fpc_ind - tbl_fea_mode
- short fpc_ind_ext - tbl_fea_mode
- short tbl_fea_mode - tbl_fea_mode
- short tbl_fea_mode - tbl_fea_mode
- short tbl_fea_mode - tbl_fea_mode
- short tbl_fea_mode - tbl_fea_mode
+ short faddr_ind_ext - tbl_fea_mode
+ short faddr_ind_ext - tbl_fea_mode
+ short faddr_ind_ext - tbl_fea_mode
+ short faddr_ind_ext - tbl_fea_mode
+ short faddr_ind_ext - tbl_fea_mode
+ short faddr_ind_ext - tbl_fea_mode
+ short faddr_ind_ext - tbl_fea_mode
+ short faddr_ind_ext - tbl_fea_mode
+
+ short fabs_short - tbl_fea_mode
+ short fabs_long - tbl_fea_mode
+ short fpc_ind - tbl_fea_mode
+ short fpc_ind_ext - tbl_fea_mode
+ short tbl_fea_mode - tbl_fea_mode
+ short tbl_fea_mode - tbl_fea_mode
+ short tbl_fea_mode - tbl_fea_mode
+ short tbl_fea_mode - tbl_fea_mode
###################################
# Address register indirect: (An) #
@@ -18903,7 +18903,7 @@ faddr_ind_ext:
btst &0x8,%d0
bne.w fcalc_mem_ind
-
+
mov.l %d0,L_SCR1(%a6) # hold opword
mov.l %d0,%d1
@@ -18999,7 +18999,7 @@ fpc_ind_ext:
btst &0x8,%d0 # is disp only 8 bits?
bne.w fcalc_mem_ind # calc memory indirect
-
+
mov.l %d0,L_SCR1(%a6) # store opword
mov.l %d0,%d1 # make extword copy
@@ -19076,7 +19076,7 @@ fno_base_sup:
bfextu %d5{&26:&2},%d0 # get bd size
# beq.l fmovm_error # if (size == 0) it's reserved
- cmpi.b %d0,&0x2
+ cmpi.b %d0,&0x2
blt.b fno_bd
beq.b fget_word_bd
@@ -19098,7 +19098,7 @@ fget_word_bd:
bne.l fcea_iacc # yes
ext.l %d0 # sign extend bd
-
+
fchk_ind:
add.l %d0,%d3 # base += bd
@@ -19107,10 +19107,10 @@ fno_bd:
bfextu %d5{&30:&2},%d0 # is od suppressed?
beq.w faii_bd
- cmpi.b %d0,&0x2
+ cmpi.b %d0,&0x2
blt.b fnull_od
beq.b fword_od
-
+
mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
bsr.l _imem_read_long
@@ -19118,7 +19118,7 @@ fno_bd:
tst.l %d1 # did ifetch fail?
bne.l fcea_iacc # yes
- bra.b fadd_them
+ bra.b fadd_them
fword_od:
mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
@@ -19171,7 +19171,7 @@ fdone_ea:
rts
#########################################################
-fcea_err:
+fcea_err:
mov.l %d3,%a0
movm.l (%sp)+,&0x003c # restore d2-d5
@@ -19181,7 +19181,7 @@ fcea_err:
fcea_iacc:
movm.l (%sp)+,&0x003c # restore d2-d5
bra.l iea_iacc
-
+
fmovm_out_err:
bsr.l restore
mov.w &0x00e1,%d0
@@ -19197,7 +19197,7 @@ fmovm_err:
#########################################################################
# XDEF **************************************************************** #
-# fmovm_ctrl(): emulate fmovm.l of control registers instr #
+# fmovm_ctrl(): emulate fmovm.l of control registers instr #
# #
# XREF **************************************************************** #
# _imem_read_long() - read longword from memory #
@@ -19205,7 +19205,7 @@ fmovm_err:
# #
# INPUT *************************************************************** #
# None #
-# #
+# #
# OUTPUT ************************************************************** #
# If _imem_read_long() doesn't fail: #
# USER_FPCR(a6) = new FPCR value #
@@ -19213,14 +19213,14 @@ fmovm_err:
# USER_FPIAR(a6) = new FPIAR value #
# #
# ALGORITHM *********************************************************** #
-# Decode the instruction type by looking at the extension word #
+# Decode the instruction type by looking at the extension word #
# in order to see how many control registers to fetch from memory. #
# Fetch them using _imem_read_long(). If this fetch fails, exit through #
# the special access error exit handler iea_iacc(). #
# #
# Instruction word decoding: #
# #
-# fmovem.l #<data>, {FPIAR&|FPCR&|FPSR} #
+# fmovem.l #<data>, {FPIAR&|FPCR&|FPSR} #
# #
# WORD1 WORD2 #
# 1111 0010 00 111100 100$ $$00 0000 0000 #
@@ -19241,7 +19241,7 @@ fmovm_ctrl:
beq.w fctrl_in_6 # yes
cmpi.b %d0,&0x94 # fpcr & fpiar ?
beq.b fctrl_in_5 # yes
-
+
# fmovem.l #<data>, fpsr/fpiar
fctrl_in_3:
mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
@@ -19340,21 +19340,21 @@ fctrl_in_7:
# #
# INPUT *************************************************************** #
# d0 = number of bytes to adjust <ea> by #
-# #
+# #
# OUTPUT ************************************************************** #
# None #
# #
# ALGORITHM *********************************************************** #
# "Dummy" CALCulate Effective Address: #
-# The stacked <ea> for FP unimplemented instructions and opclass #
+# The stacked <ea> for FP unimplemented instructions and opclass #
# two packed instructions is correct with the exception of... #
# #
# 1) -(An) : The register is not updated regardless of size. #
-# Also, for extended precision and packed, the #
+# Also, for extended precision and packed, the #
# stacked <ea> value is 8 bytes too big #
# 2) (An)+ : The register is not updated. #
-# 3) #<data> : The upper longword of the immediate operand is #
-# stacked b,w,l and s sizes are completely stacked. #
+# 3) #<data> : The upper longword of the immediate operand is #
+# stacked b,w,l and s sizes are completely stacked. #
# d,x, and p are not. #
# #
#########################################################################
@@ -19390,8 +19390,8 @@ dcea_imm:
lea ([USER_FPIAR,%a6],0x4),%a0 # no; return <ea>
rts
-# here, the <ea> is stacked correctly. however, we must update the
-# address register...
+# here, the <ea> is stacked correctly. however, we must update the
+# address register...
dcea_pi:
mov.l %a0,%d0 # pass amt to inc by
bsr.l inc_areg # inc addr register
@@ -19399,7 +19399,7 @@ dcea_pi:
mov.l EXC_EA(%a6),%a0 # stacked <ea> is correct
rts
-# the <ea> is stacked correctly for all but extended and packed which
+# the <ea> is stacked correctly for all but extended and packed which
# the <ea>s are 8 bytes too large.
# it would make no sense to have a pre-decrement to a7 in supervisor
# mode so we don't even worry about this tricky case here : )
@@ -19419,7 +19419,7 @@ dcea_pd2:
#########################################################################
# XDEF **************************************************************** #
-# _calc_ea_fout(): calculate correct stacked <ea> for extended #
+# _calc_ea_fout(): calculate correct stacked <ea> for extended #
# and packed data opclass 3 operations. #
# #
# XREF **************************************************************** #
@@ -19427,22 +19427,22 @@ dcea_pd2:
# #
# INPUT *************************************************************** #
# None #
-# #
+# #
# OUTPUT ************************************************************** #
# a0 = return correct effective address #
# #
# ALGORITHM *********************************************************** #
# For opclass 3 extended and packed data operations, the <ea> #
# stacked for the exception is incorrect for -(an) and (an)+ addressing #
-# modes. Also, while we're at it, the index register itself must get #
+# modes. Also, while we're at it, the index register itself must get #
# updated. #
-# So, for -(an), we must subtract 8 off of the stacked <ea> value #
+# So, for -(an), we must subtract 8 off of the stacked <ea> value #
# and return that value as the correct <ea> and store that value in An. #
# For (an)+, the stacked <ea> is correct but we must adjust An by +12. #
# #
#########################################################################
-# This calc_ea is currently used to retrieve the correct <ea>
+# This calc_ea is currently used to retrieve the correct <ea>
# for fmove outs of type extended and packed.
global _calc_ea_fout
_calc_ea_fout:
@@ -19463,7 +19463,7 @@ _calc_ea_fout:
# (An)+ : extended and packed fmove out
# : stacked <ea> is correct
-# : "An" not updated
+# : "An" not updated
ceaf_pi:
mov.w (tbl_ceaf_pi.b,%pc,%d1.w*2),%d1
mov.l EXC_EA(%a6),%a0
@@ -19574,31 +19574,31 @@ ceaf_pd7:
# #
# INPUT *************************************************************** #
# None #
-# #
+# #
# OUTPUT ************************************************************** #
# If memory access doesn't fail: #
# FP_SRC(a6) = source operand in extended precision #
-# FP_DST(a6) = destination operand in extended precision #
+# FP_DST(a6) = destination operand in extended precision #
# #
# ALGORITHM *********************************************************** #
-# This is called from the Unimplemented FP exception handler in #
+# This is called from the Unimplemented FP exception handler in #
# order to load the source and maybe destination operand into #
# FP_SRC(a6) and FP_DST(a6). If the instruction was opclass zero, load #
# the source and destination from the FP register file. Set the optype #
# tags for both if dyadic, one for monadic. If a number is an UNNORM, #
# convert it to a DENORM or a ZERO. #
-# If the instruction is opclass two (memory->reg), then fetch #
-# the destination from the register file and the source operand from #
+# If the instruction is opclass two (memory->reg), then fetch #
+# the destination from the register file and the source operand from #
# memory. Tag and fix both as above w/ opclass zero instructions. #
-# If the source operand is byte,word,long, or single, it may be #
+# If the source operand is byte,word,long, or single, it may be #
# in the data register file. If it's actually out in memory, use one of #
# the mem_read() routines to fetch it. If the mem_read() access returns #
# a failing value, exit through the special facc_in() routine which #
# will create an access error exception frame from the current exception #
# frame. #
-# Immediate data and regular data accesses are separated because #
+# Immediate data and regular data accesses are separated because #
# if an immediate data access fails, the resulting fault status #
-# longword stacked for the access error exception must have the #
+# longword stacked for the access error exception must have the #
# instruction bit set. #
# #
#########################################################################
@@ -19644,7 +19644,7 @@ op000_dst:
cmpi.b %d0, &UNNORM # is dst fpreg an UNNORM?
beq.b op000_dst_unnorm # yes
op000_dst_cont:
- mov.b %d0, DTAG(%a6) # store the dst optype tag
+ mov.b %d0, DTAG(%a6) # store the dst optype tag
op000_src:
bfextu EXC_CMDREG(%a6){&3:&3}, %d0 # extract src field
@@ -19709,7 +19709,7 @@ op010_dst_unnorm:
swbeg &0x8
tbl_op010_dreg:
short opd_long - tbl_op010_dreg
- short opd_sgl - tbl_op010_dreg
+ short opd_sgl - tbl_op010_dreg
short tbl_op010_dreg - tbl_op010_dreg
short tbl_op010_dreg - tbl_op010_dreg
short opd_word - tbl_op010_dreg
@@ -19722,7 +19722,7 @@ tbl_op010_dreg:
#
opd_long:
bsr.l fetch_dreg # fetch long in d0
- fmov.l %d0, %fp0 # load a long
+ fmov.l %d0, %fp0 # load a long
fmovm.x &0x80, FP_SRC(%a6) # return src op in FP_SRC
fbeq.w opd_long_zero # long is a ZERO
rts
@@ -19735,7 +19735,7 @@ opd_long_zero:
#
opd_word:
bsr.l fetch_dreg # fetch word in d0
- fmov.w %d0, %fp0 # load a word
+ fmov.w %d0, %fp0 # load a word
fmovm.x &0x80, FP_SRC(%a6) # return src op in FP_SRC
fbeq.w opd_word_zero # WORD is a ZERO
rts
@@ -19748,7 +19748,7 @@ opd_word_zero:
#
opd_byte:
bsr.l fetch_dreg # fetch word in d0
- fmov.b %d0, %fp0 # load a byte
+ fmov.b %d0, %fp0 # load a byte
fmovm.x &0x80, FP_SRC(%a6) # return src op in FP_SRC
fbeq.w opd_byte_zero # byte is a ZERO
rts
@@ -19766,7 +19766,7 @@ opd_sgl:
bsr.l fetch_dreg # fetch sgl in d0
mov.l %d0,L_SCR1(%a6)
- lea L_SCR1(%a6), %a0 # pass: ptr to the sgl
+ lea L_SCR1(%a6), %a0 # pass: ptr to the sgl
bsr.l set_tag_s # determine sgl type
mov.b %d0, STAG(%a6) # save the src tag
@@ -19813,7 +19813,7 @@ tbl_fp_type:
#########################################
# load a LONG into %fp0: #
-# -number can't fault #
+# -number can't fault #
# (1) calc ea #
# (2) read 4 bytes into L_SCR1 #
# (3) fmov.l into %fp0 #
@@ -19849,7 +19849,7 @@ load_long_immed:
#########################################
# load a WORD into %fp0: #
-# -number can't fault #
+# -number can't fault #
# (1) calc ea #
# (2) read 2 bytes into L_SCR1 #
# (3) fmov.w into %fp0 #
@@ -19885,7 +19885,7 @@ load_word_immed:
#########################################
# load a BYTE into %fp0: #
-# -number can't fault #
+# -number can't fault #
# (1) calc ea #
# (2) read 1 byte into L_SCR1 #
# (3) fmov.b into %fp0 #
@@ -19921,7 +19921,7 @@ load_byte_immed:
#########################################
# load a SGL into %fp0: #
-# -number can't fault #
+# -number can't fault #
# (1) calc ea #
# (2) read 4 bytes into L_SCR1 #
# (3) fmov.s into %fp0 #
@@ -19961,7 +19961,7 @@ load_sgl_immed:
bne.l funimp_iacc # yes
bra.b load_sgl_cont
-# must convert sgl denorm format to an Xprec denorm fmt suitable for
+# must convert sgl denorm format to an Xprec denorm fmt suitable for
# normalization...
# %a0 : points to sgl denorm
get_sgl_denorm:
@@ -20003,7 +20003,7 @@ no_sgl_snan_sgn:
#########################################
# load a DBL into %fp0: #
-# -number can't fault #
+# -number can't fault #
# (1) calc ea #
# (2) read 8 bytes into L_SCR(1,2)#
# (3) fmov.d into %fp0 #
@@ -20046,7 +20046,7 @@ load_dbl_immed:
bne.l funimp_iacc # yes
bra.b load_dbl_cont
-# must convert dbl denorm format to an Xprec denorm fmt suitable for
+# must convert dbl denorm format to an Xprec denorm fmt suitable for
# normalization...
# %a0 : loc. of dbl denorm
get_dbl_denorm:
@@ -20092,7 +20092,7 @@ no_dbl_snan_sgn:
#################################################
# load a Xprec into %fp0: #
-# -number can't fault #
+# -number can't fault #
# (1) calc ea #
# (2) read 12 bytes into L_SCR(1,2) #
# (3) fmov.x into %fp0 #
@@ -20124,7 +20124,7 @@ load_ext_unnorm:
#################################################
# load a packed into %fp0: #
-# -number can't fault #
+# -number can't fault #
# (1) calc ea #
# (2) read 12 bytes into L_SCR(1,2,3) #
# (3) fmov.x into %fp0 #
@@ -20143,11 +20143,11 @@ load_packed:
load_packed_unnorm:
bsr.l unnorm_fix # fix the UNNORM ZERO
mov.b %d0,STAG(%a6) # store the src optype tag
- rts
+ rts
#########################################################################
# XDEF **************************************************************** #
-# fout(): move from fp register to memory or data register #
+# fout(): move from fp register to memory or data register #
# #
# XREF **************************************************************** #
# _round() - needed to create EXOP for sgl/dbl precision #
@@ -20167,7 +20167,7 @@ load_packed_unnorm:
# INPUT *************************************************************** #
# a0 = pointer to extended precision source operand #
# d0 = round prec,mode #
-# #
+# #
# OUTPUT ************************************************************** #
# fp0 : intermediate underflow or overflow result if #
# OVFL/UNFL occurred for a sgl or dbl operand #
@@ -20186,9 +20186,9 @@ load_packed_unnorm:
# w/ the address index register as appropriate w/ _calc_ea_fout(). If #
# the source is a denorm and if underflow is enabled, an EXOP must be #
# created. #
-# For packed, the k-factor must be fetched from the instruction #
-# word or a data register. The <ea> must be fixed as w/ extended #
-# precision. Then, bindec() is called to create the appropriate #
+# For packed, the k-factor must be fetched from the instruction #
+# word or a data register. The <ea> must be fixed as w/ extended #
+# precision. Then, bindec() is called to create the appropriate #
# packed result. #
# If at any time an access error is flagged by one of the move- #
# to-memory routines, then a special exit must be made so that the #
@@ -20304,7 +20304,7 @@ fout_word_denorm:
ori.l &0x00800000,%d1 # make smallest sgl
fmov.s %d1,%fp0
bra.b fout_word_norm
-
+
#################################################################
# fmove.l out ###################################################
#################################################################
@@ -20378,7 +20378,7 @@ fout_ext:
mov.l &0xc,%d0 # pass: opsize is 12 bytes
# we must not yet write the extended precision data to the stack
-# in the pre-decrement case from supervisor mode or else we'll corrupt
+# in the pre-decrement case from supervisor mode or else we'll corrupt
# the stack frame. so, leave it in FP_SRC for now and deal with it later...
cmpi.b SPCOND_FLG(%a6),&mda7_flg
beq.b fout_ext_a7
@@ -20465,7 +20465,7 @@ fout_sgl_exg:
fmov.l &0x0,%fpcr # clear FPCR
fmov.l %fpsr,%d1 # save FPSR
- or.w %d1,2+USER_FPSR(%a6) # set possible inex2/ainex
+ or.w %d1,2+USER_FPSR(%a6) # set possible inex2/ainex
fout_sgl_exg_write:
mov.b 1+EXC_OPWORD(%a6),%d1 # extract dst mode
@@ -20506,7 +20506,7 @@ fout_sgl_unfl:
lea FP_SCR0(%a6),%a0
bsr.l norm # normalize the DENORM
-
+
fout_sgl_unfl_cont:
lea FP_SCR0(%a6),%a0 # pass: ptr to operand
mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode
@@ -20557,7 +20557,7 @@ fout_sgl_ovfl_cont:
# call ovf_res() w/ sgl prec and the correct rnd mode to create the default
# overflow result. DON'T save the returned ccodes from ovf_res() since
-# fmove out doesn't alter them.
+# fmove out doesn't alter them.
tst.b SRC_EX(%a0) # is operand negative?
smi %d1 # set if so
mov.l L_SCR3(%a6),%d0 # pass: sgl prec,rnd mode
@@ -20612,7 +20612,7 @@ fout_sgl_may_ovfl:
fabs.x %fp0 # need absolute value
fcmp.b %fp0,&0x2 # did exponent increase?
- fblt.w fout_sgl_exg # no; go finish NORM
+ fblt.w fout_sgl_exg # no; go finish NORM
bra.w fout_sgl_ovfl # yes; go handle overflow
################
@@ -20703,7 +20703,7 @@ fout_dbl_exg:
fmov.l &0x0,%fpcr # clear FPCR
fmov.l %fpsr,%d0 # save FPSR
- or.w %d0,2+USER_FPSR(%a6) # set possible inex2/ainex
+ or.w %d0,2+USER_FPSR(%a6) # set possible inex2/ainex
mov.l EXC_EA(%a6),%a1 # pass: dst addr
lea L_SCR1(%a6),%a0 # pass: src addr
@@ -20713,7 +20713,7 @@ fout_dbl_exg:
tst.l %d1 # did dstore fail?
bne.l facc_out_d # yes
- rts # no; so we're finished
+ rts # no; so we're finished
#
# here, we know that the operand would UNFL if moved out to double prec,
@@ -20735,7 +20735,7 @@ fout_dbl_unfl:
lea FP_SCR0(%a6),%a0
bsr.l norm # normalize the DENORM
-
+
fout_dbl_unfl_cont:
lea FP_SCR0(%a6),%a0 # pass: ptr to operand
mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode
@@ -20778,7 +20778,7 @@ fout_dbl_ovfl_cont:
# call ovf_res() w/ dbl prec and the correct rnd mode to create the default
# overflow result. DON'T save the returned ccodes from ovf_res() since
-# fmove out doesn't alter them.
+# fmove out doesn't alter them.
tst.b SRC_EX(%a0) # is operand negative?
smi %d1 # set if so
mov.l L_SCR3(%a6),%d0 # pass: dbl prec,rnd mode
@@ -20823,19 +20823,19 @@ fout_dbl_may_ovfl:
fabs.x %fp0 # need absolute value
fcmp.b %fp0,&0x2 # did exponent increase?
- fblt.w fout_dbl_exg # no; go finish NORM
+ fblt.w fout_dbl_exg # no; go finish NORM
bra.w fout_dbl_ovfl # yes; go handle overflow
#########################################################################
# XDEF **************************************************************** #
-# dst_dbl(): create double precision value from extended prec. #
+# dst_dbl(): create double precision value from extended prec. #
# #
# XREF **************************************************************** #
# None #
# #
# INPUT *************************************************************** #
# a0 = pointer to source operand in extended precision #
-# #
+# #
# OUTPUT ************************************************************** #
# d0 = hi(double precision result) #
# d1 = lo(double precision result) #
@@ -20849,18 +20849,18 @@ fout_dbl_may_ovfl:
# get rid of ext integer bit #
# dbl_mant = ext_mant{62:12} #
# #
-# --------------- --------------- --------------- #
+# --------------- --------------- --------------- #
# extended -> |s| exp | |1| ms mant | | ls mant | #
-# --------------- --------------- --------------- #
-# 95 64 63 62 32 31 11 0 #
+# --------------- --------------- --------------- #
+# 95 64 63 62 32 31 11 0 #
# | | #
# | | #
# | | #
-# v v #
-# --------------- --------------- #
-# double -> |s|exp| mant | | mant | #
-# --------------- --------------- #
-# 63 51 32 31 0 #
+# v v #
+# --------------- --------------- #
+# double -> |s|exp| mant | | mant | #
+# --------------- --------------- #
+# 63 51 32 31 0 #
# #
#########################################################################
@@ -20896,13 +20896,13 @@ dst_get_dman:
#########################################################################
# XDEF **************************************************************** #
-# dst_sgl(): create single precision value from extended prec #
+# dst_sgl(): create single precision value from extended prec #
# #
# XREF **************************************************************** #
# #
# INPUT *************************************************************** #
# a0 = pointer to source operand in extended precision #
-# #
+# #
# OUTPUT ************************************************************** #
# d0 = single precision result #
# #
@@ -20914,18 +20914,18 @@ dst_get_dman:
# get rid of ext integer bit #
# sgl_mant = ext_mant{62:12} #
# #
-# --------------- --------------- --------------- #
+# --------------- --------------- --------------- #
# extended -> |s| exp | |1| ms mant | | ls mant | #
-# --------------- --------------- --------------- #
-# 95 64 63 62 40 32 31 12 0 #
+# --------------- --------------- --------------- #
+# 95 64 63 62 40 32 31 12 0 #
# | | #
# | | #
# | | #
-# v v #
-# --------------- #
-# single -> |s|exp| mant | #
-# --------------- #
-# 31 22 0 #
+# v v #
+# --------------- #
+# single -> |s|exp| mant | #
+# --------------- #
+# 31 22 0 #
# #
#########################################################################
@@ -20998,7 +20998,7 @@ fout_pack_type:
# add the extra condition that only if the k-factor was zero, too, should
# we zero the exponent
tst.l %d0
- bne.b fout_pack_set
+ bne.b fout_pack_set
# "mantissa" is all zero which means that the answer is zero. but, the '040
# algorithm allows the exponent to be non-zero. the 881/2 do not. therefore,
# if the mantissa is zero, I will zero the exponent, too.
@@ -21057,13 +21057,13 @@ fout_pack_snan:
# #
# INPUT *************************************************************** #
# d1 = index of register to fetch from #
-# #
+# #
# OUTPUT ************************************************************** #
# d0 = value of register fetched #
# #
# ALGORITHM *********************************************************** #
-# According to the index value in d1 which can range from zero #
-# to fifteen, load the corresponding register file value (where #
+# According to the index value in d1 which can range from zero #
+# to fifteen, load the corresponding register file value (where #
# address register indexes start at 8). D0/D1/A0/A1/A6/A7 are on the #
# stack. The rest should still be in their original places. #
# #
@@ -21152,7 +21152,7 @@ fdregf:
# INPUT *************************************************************** #
# d0 = longowrd value to store #
# d1 = index of register to fetch from #
-# #
+# #
# OUTPUT ************************************************************** #
# (data register is updated) #
# #
@@ -21213,7 +21213,7 @@ sdregl7:
# INPUT *************************************************************** #
# d0 = word value to store #
# d1 = index of register to fetch from #
-# #
+# #
# OUTPUT ************************************************************** #
# (data register is updated) #
# #
@@ -21274,7 +21274,7 @@ sdregw7:
# INPUT *************************************************************** #
# d0 = byte value to store #
# d1 = index of register to fetch from #
-# #
+# #
# OUTPUT ************************************************************** #
# (data register is updated) #
# #
@@ -21335,16 +21335,16 @@ sdregb7:
# INPUT *************************************************************** #
# d0 = amount to increment by #
# d1 = index of address register to increment #
-# #
+# #
# OUTPUT ************************************************************** #
# (address register is updated) #
# #
# ALGORITHM *********************************************************** #
-# Typically used for an instruction w/ a post-increment <ea>, #
+# Typically used for an instruction w/ a post-increment <ea>, #
# this routine adds the increment value in d0 to the address register #
# specified by d1. A0/A1/A6/A7 reside on the stack. The rest reside #
# in their original places. #
-# For a7, if the increment amount is one, then we have to #
+# For a7, if the increment amount is one, then we have to #
# increment by two. For any a7 update, set the mia7_flag so that if #
# an access error exception occurs later in emulation, this address #
# register update can be undone. #
@@ -21399,16 +21399,16 @@ iareg7b:
# INPUT *************************************************************** #
# d0 = amount to decrement by #
# d1 = index of address register to decrement #
-# #
+# #
# OUTPUT ************************************************************** #
# (address register is updated) #
# #
# ALGORITHM *********************************************************** #
-# Typically used for an instruction w/ a pre-decrement <ea>, #
+# Typically used for an instruction w/ a pre-decrement <ea>, #
# this routine adds the decrement value in d0 to the address register #
# specified by d1. A0/A1/A6/A7 reside on the stack. The rest reside #
# in their original places. #
-# For a7, if the decrement amount is one, then we have to #
+# For a7, if the decrement amount is one, then we have to #
# decrement by two. For any a7 update, set the mda7_flag so that if #
# an access error exception occurs later in emulation, this address #
# register update can be undone. #
@@ -21464,17 +21464,17 @@ dareg7b:
# #
# INPUT *************************************************************** #
# d0 = index of FP register to load #
-# #
+# #
# OUTPUT ************************************************************** #
# FP_SRC(a6) = value loaded from FP register file #
# #
# ALGORITHM *********************************************************** #
-# Using the index in d0, load FP_SRC(a6) with a number from the #
+# Using the index in d0, load FP_SRC(a6) with a number from the #
# FP register file. #
# #
#########################################################################
- global load_fpn1
+ global load_fpn1
load_fpn1:
mov.w (tbl_load_fpn1.b,%pc,%d0.w*2), %d0
jmp (tbl_load_fpn1.b,%pc,%d0.w*1)
@@ -21537,12 +21537,12 @@ load_fpn1_7:
# #
# INPUT *************************************************************** #
# d0 = index of FP register to load #
-# #
+# #
# OUTPUT ************************************************************** #
# FP_DST(a6) = value loaded from FP register file #
# #
# ALGORITHM *********************************************************** #
-# Using the index in d0, load FP_DST(a6) with a number from the #
+# Using the index in d0, load FP_DST(a6) with a number from the #
# FP register file. #
# #
#########################################################################
@@ -21603,7 +21603,7 @@ load_fpn2_7:
#########################################################################
# XDEF **************************************************************** #
-# store_fpreg(): store an fp value to the fpreg designated d0. #
+# store_fpreg(): store an fp value to the fpreg designated d0. #
# #
# XREF **************************************************************** #
# None #
@@ -21611,7 +21611,7 @@ load_fpn2_7:
# INPUT *************************************************************** #
# fp0 = extended precision value to store #
# d0 = index of floating-point register #
-# #
+# #
# OUTPUT ************************************************************** #
# None #
# #
@@ -21644,33 +21644,33 @@ store_fpreg_1:
fmovm.x &0x80, EXC_FP1(%a6)
rts
store_fpreg_2:
- fmovm.x &0x01, -(%sp)
+ fmovm.x &0x01, -(%sp)
fmovm.x (%sp)+, &0x20
rts
store_fpreg_3:
- fmovm.x &0x01, -(%sp)
+ fmovm.x &0x01, -(%sp)
fmovm.x (%sp)+, &0x10
rts
store_fpreg_4:
- fmovm.x &0x01, -(%sp)
+ fmovm.x &0x01, -(%sp)
fmovm.x (%sp)+, &0x08
rts
store_fpreg_5:
- fmovm.x &0x01, -(%sp)
+ fmovm.x &0x01, -(%sp)
fmovm.x (%sp)+, &0x04
rts
store_fpreg_6:
- fmovm.x &0x01, -(%sp)
+ fmovm.x &0x01, -(%sp)
fmovm.x (%sp)+, &0x02
rts
store_fpreg_7:
- fmovm.x &0x01, -(%sp)
+ fmovm.x &0x01, -(%sp)
fmovm.x (%sp)+, &0x01
rts
#########################################################################
# XDEF **************************************************************** #
-# _denorm(): denormalize an intermediate result #
+# _denorm(): denormalize an intermediate result #
# #
# XREF **************************************************************** #
# None #
@@ -21678,7 +21678,7 @@ store_fpreg_7:
# INPUT *************************************************************** #
# a0 = points to the operand to be denormalized #
# (in the internal extended format) #
-# #
+# #
# d0 = rounding precision #
# #
# OUTPUT ************************************************************** #
@@ -21688,10 +21688,10 @@ store_fpreg_7:
# d0 = guard,round,sticky #
# #
# ALGORITHM *********************************************************** #
-# According to the exponent underflow threshold for the given #
+# According to the exponent underflow threshold for the given #
# precision, shift the mantissa bits to the right in order raise the #
-# exponent of the operand to the threshold value. While shifting the #
-# mantissa bits right, maintain the value of the guard, round, and #
+# exponent of the operand to the threshold value. While shifting the #
+# mantissa bits right, maintain the value of the guard, round, and #
# sticky bits. #
# other notes: #
# (1) _denorm() is called by the underflow routines #
@@ -21711,7 +21711,7 @@ tbl_thresh:
_denorm:
#
# Load the exponent threshold for the precision selected and check
-# to see if (threshold - exponent) is > 65 in which case we can
+# to see if (threshold - exponent) is > 65 in which case we can
# simply calculate the sticky bit and zero the mantissa. otherwise
# we have to call the denormalization routine.
#
@@ -21750,7 +21750,7 @@ denorm_set_stky:
# %d0{31:29} : initial guard,round,sticky #
# %d1{15:0} : denormalization threshold #
# OUTPUT: #
-# %a0 : points to the denormalized operand #
+# %a0 : points to the denormalized operand #
# %d0{31:29} : final guard,round,sticky #
# #
@@ -21770,7 +21770,7 @@ dnrm_lp:
#
# check to see how much less than the underflow threshold the operand
-# exponent is.
+# exponent is.
#
mov.l %d1, %d0 # copy the denorm threshold
sub.w FTEMP_EX(%a0), %d1 # d1 = threshold - uns exponent
@@ -21785,7 +21785,7 @@ dnrm_lp:
# No normalization necessary
#
dnrm_no_lp:
- mov.l GRS(%a6), %d0 # restore original g,r,s
+ mov.l GRS(%a6), %d0 # restore original g,r,s
rts
#
@@ -21795,7 +21795,7 @@ dnrm_no_lp:
# %d1 = "n" = amt to shift
#
# ---------------------------------------------------------
-# | FTEMP_HI | FTEMP_LO |grs000.........000|
+# | FTEMP_HI | FTEMP_LO |grs000.........000|
# ---------------------------------------------------------
# <-(32 - n)-><-(n)-><-(32 - n)-><-(n)-><-(32 - n)-><-(n)->
# \ \ \ \
@@ -21806,7 +21806,7 @@ dnrm_no_lp:
# \ \ \ \
# \ \ \ \
# \ \ \ \
-# <-(n)-><-(32 - n)-><------(32)-------><------(32)------->
+# <-(n)-><-(32 - n)-><------(32)-------><------(32)------->
# ---------------------------------------------------------
# |0.....0| NEW_HI | NEW_FTEMP_LO |grs |
# ---------------------------------------------------------
@@ -21847,17 +21847,17 @@ case1_sticky_clear:
# %d1 = "n" = amt to shift
#
# ---------------------------------------------------------
-# | FTEMP_HI | FTEMP_LO |grs000.........000|
+# | FTEMP_HI | FTEMP_LO |grs000.........000|
# ---------------------------------------------------------
# <-(32 - n)-><-(n)-><-(32 - n)-><-(n)-><-(32 - n)-><-(n)->
# \ \ \
# \ \ \
# \ \ -------------------
# \ -------------------- \
-# ------------------- \ \
-# \ \ \
-# \ \ \
-# \ \ \
+# ------------------- \ \
+# \ \ \
+# \ \ \
+# \ \ \
# <-------(32)------><-(n)-><-(32 - n)-><------(32)------->
# ---------------------------------------------------------
# |0...............0|0....0| NEW_LO |grs |
@@ -21928,17 +21928,17 @@ case_3:
# case (d1 == 64)
#
# ---------------------------------------------------------
-# | FTEMP_HI | FTEMP_LO |grs000.........000|
+# | FTEMP_HI | FTEMP_LO |grs000.........000|
# ---------------------------------------------------------
# <-------(32)------>
-# \ \
-# \ \
-# \ \
-# \ ------------------------------
+# \ \
+# \ \
+# \ \
+# \ ------------------------------
# ------------------------------- \
-# \ \
-# \ \
-# \ \
+# \ \
+# \ \
+# \ \
# <-------(32)------>
# ---------------------------------------------------------
# |0...............0|0................0|grs |
@@ -21956,17 +21956,17 @@ case3_64:
# case (d1 == 65)
#
# ---------------------------------------------------------
-# | FTEMP_HI | FTEMP_LO |grs000.........000|
+# | FTEMP_HI | FTEMP_LO |grs000.........000|
# ---------------------------------------------------------
# <-------(32)------>
-# \ \
-# \ \
-# \ \
-# \ ------------------------------
+# \ \
+# \ \
+# \ \
+# \ ------------------------------
# -------------------------------- \
-# \ \
-# \ \
-# \ \
+# \ \
+# \ \
+# \ \
# <-------(31)----->
# ---------------------------------------------------------
# |0...............0|0................0|0rs |
@@ -22014,7 +22014,7 @@ case3_set_sticky:
# None #
# #
# INPUT *************************************************************** #
-# a0 = ptr to input operand in internal extended format #
+# a0 = ptr to input operand in internal extended format #
# d1(hi) = contains rounding precision: #
# ext = $0000xxxx #
# sgl = $0004xxxx #
@@ -22045,7 +22045,7 @@ _round:
#
# ext_grs() looks at the rounding precision and sets the appropriate
# G,R,S bits.
-# If (G,R,S == 0) then result is exact and round is done, else set
+# If (G,R,S == 0) then result is exact and round is done, else set
# the inex flag in status reg and continue.
#
bsr.l ext_grs # extract G,R,S
@@ -22091,7 +22091,7 @@ rnd_plus:
# If sign of fp number = 1 (negative), then add 1 to l. #
#################################################################
rnd_mnus:
- tst.b FTEMP_SGN(%a0) # check for sign
+ tst.b FTEMP_SGN(%a0) # check for sign
bpl.w truncate # if negative then truncate
mov.l &0xffffffff, %d0 # force g,r,s to be all f's
@@ -22202,7 +22202,7 @@ truncate:
#
# INPUT
# d0 = extended precision g,r,s (in d0{31:29})
-# d1 = {PREC,ROUND}
+# d1 = {PREC,ROUND}
# OUTPUT
# d0{31:29} = guard, round, sticky
#
@@ -22253,7 +22253,7 @@ ext_grs_sgl:
mov.l &30, %d2 # of the sgl prec. limits
lsl.l %d2, %d3 # shift g-r bits to MSB of d3
mov.l FTEMP_HI(%a0), %d2 # get word 2 for s-bit test
- and.l &0x0000003f, %d2 # s bit is the or of all other
+ and.l &0x0000003f, %d2 # s bit is the or of all other
bne.b ext_grs_st_stky # bits to the right of g-r
tst.l FTEMP_LO(%a0) # test lower mantissa
bne.b ext_grs_st_stky # if any are set, set sticky
@@ -22263,9 +22263,9 @@ ext_grs_sgl:
#
# dbl:
-# 96 64 32 11 0
+# 96 64 32 11 0
# -----------------------------------------------------
-# | EXP |XXXXXXX| | |xx |grs|
+# | EXP |XXXXXXX| | |xx |grs|
# -----------------------------------------------------
# nn\ /
# ee -------
@@ -22278,7 +22278,7 @@ ext_grs_dbl:
mov.l &30, %d2 # of the dbl prec. limits
lsl.l %d2, %d3 # shift g-r bits to the MSB of d3
mov.l FTEMP_LO(%a0), %d2 # get lower mantissa for s-bit test
- and.l &0x000001ff, %d2 # s bit is the or-ing of all
+ and.l &0x000001ff, %d2 # s bit is the or-ing of all
bne.b ext_grs_st_stky # other bits to the right of g-r
tst.l %d0 # test word original g,r,s
bne.b ext_grs_st_stky # if any are set, set sticky
@@ -22308,7 +22308,7 @@ ext_grs_end_sd:
# a0 = pointer fp extended precision operand to normalize #
# #
# OUTPUT ************************************************************** #
-# d0 = number of bit positions the mantissa was shifted #
+# d0 = number of bit positions the mantissa was shifted #
# a0 = the input operand's mantissa is normalized; the exponent #
# is unchanged. #
# #
@@ -22335,7 +22335,7 @@ norm_hi:
mov.l %d1, FTEMP_LO(%a0) # store new lo(man)
mov.l %d2, %d0 # return shift amount
-
+
mov.l (%sp)+, %d3 # restore temp regs
mov.l (%sp)+, %d2
@@ -22350,7 +22350,7 @@ norm_lo:
clr.l FTEMP_LO(%a0) # lo(man) is now zero
mov.l %d2, %d0 # return shift amount
-
+
mov.l (%sp)+, %d3 # restore temp regs
mov.l (%sp)+, %d2
@@ -22455,27 +22455,27 @@ unnorm_nrm_zero_lrg:
# whole mantissa is zero so this UNNORM is actually a zero
#
unnorm_zero:
- and.w &0x8000, FTEMP_EX(%a0) # force exponent to zero
+ and.w &0x8000, FTEMP_EX(%a0) # force exponent to zero
mov.b &ZERO, %d0 # fix optype tag
rts
#########################################################################
# XDEF **************************************************************** #
-# set_tag_x(): return the optype of the input ext fp number #
+# set_tag_x(): return the optype of the input ext fp number #
# #
# XREF **************************************************************** #
# None #
# #
# INPUT *************************************************************** #
# a0 = pointer to extended precision operand #
-# #
+# #
# OUTPUT ************************************************************** #
# d0 = value of type tag #
-# one of: NORM, INF, QNAN, SNAN, DENORM, UNNORM, ZERO #
+# one of: NORM, INF, QNAN, SNAN, DENORM, UNNORM, ZERO #
# #
# ALGORITHM *********************************************************** #
-# Simply test the exponent, j-bit, and mantissa values to #
+# Simply test the exponent, j-bit, and mantissa values to #
# determine the type of operand. #
# If it's an unnormalized zero, alter the operand and force it #
# to be a normal zero. #
@@ -22542,20 +22542,20 @@ is_snan_x:
#########################################################################
# XDEF **************************************************************** #
-# set_tag_d(): return the optype of the input dbl fp number #
+# set_tag_d(): return the optype of the input dbl fp number #
# #
# XREF **************************************************************** #
# None #
# #
# INPUT *************************************************************** #
# a0 = points to double precision operand #
-# #
+# #
# OUTPUT ************************************************************** #
# d0 = value of type tag #
-# one of: NORM, INF, QNAN, SNAN, DENORM, ZERO #
+# one of: NORM, INF, QNAN, SNAN, DENORM, ZERO #
# #
# ALGORITHM *********************************************************** #
-# Simply test the exponent, j-bit, and mantissa values to #
+# Simply test the exponent, j-bit, and mantissa values to #
# determine the type of operand. #
# #
#########################################################################
@@ -22605,20 +22605,20 @@ is_qnan_d:
#########################################################################
# XDEF **************************************************************** #
-# set_tag_s(): return the optype of the input sgl fp number #
+# set_tag_s(): return the optype of the input sgl fp number #
# #
# XREF **************************************************************** #
# None #
# #
# INPUT *************************************************************** #
# a0 = pointer to single precision operand #
-# #
+# #
# OUTPUT ************************************************************** #
# d0 = value of type tag #
-# one of: NORM, INF, QNAN, SNAN, DENORM, ZERO #
+# one of: NORM, INF, QNAN, SNAN, DENORM, ZERO #
# #
# ALGORITHM *********************************************************** #
-# Simply test the exponent, j-bit, and mantissa values to #
+# Simply test the exponent, j-bit, and mantissa values to #
# determine the type of operand. #
# #
#########################################################################
@@ -22664,15 +22664,15 @@ is_qnan_s:
#########################################################################
# XDEF **************************************************************** #
-# unf_res(): routine to produce default underflow result of a #
-# scaled extended precision number; this is used by #
+# unf_res(): routine to produce default underflow result of a #
+# scaled extended precision number; this is used by #
# fadd/fdiv/fmul/etc. emulation routines. #
-# unf_res4(): same as above but for fsglmul/fsgldiv which use #
+# unf_res4(): same as above but for fsglmul/fsgldiv which use #
# single round prec and extended prec mode. #
# #
# XREF **************************************************************** #
# _denorm() - denormalize according to scale factor #
-# _round() - round denormalized number according to rnd prec #
+# _round() - round denormalized number according to rnd prec #
# #
# INPUT *************************************************************** #
# a0 = pointer to extended precison operand #
@@ -22684,15 +22684,15 @@ is_qnan_s:
# d0.b = result FPSR_cc which caller may or may not want to save #
# #
# ALGORITHM *********************************************************** #
-# Convert the input operand to "internal format" which means the #
+# Convert the input operand to "internal format" which means the #
# exponent is extended to 16 bits and the sign is stored in the unused #
# portion of the extended precison operand. Denormalize the number #
-# according to the scale factor passed in d0. Then, round the #
+# according to the scale factor passed in d0. Then, round the #
# denormalized result. #
-# Set the FPSR_exc bits as appropriate but return the cc bits in #
+# Set the FPSR_exc bits as appropriate but return the cc bits in #
# d0 in case the caller doesn't want to save them (as is the case for #
# fmove out). #
-# unf_res4() for fsglmul/fsgldiv forces the denorm to extended #
+# unf_res4() for fsglmul/fsgldiv forces the denorm to extended #
# precision and the rounding mode to single. #
# #
#########################################################################
@@ -22830,23 +22830,23 @@ unf_res4_end:
# none #
# #
# INPUT *************************************************************** #
-# d1.b = '-1' => (-); '0' => (+) #
+# d1.b = '-1' => (-); '0' => (+) #
# ovf_res(): #
-# d0 = rnd mode/prec #
+# d0 = rnd mode/prec #
# ovf_res2(): #
-# hi(d0) = rnd prec #
+# hi(d0) = rnd prec #
# lo(d0) = rnd mode #
# #
# OUTPUT ************************************************************** #
-# a0 = points to extended precision result #
-# d0.b = condition code bits #
+# a0 = points to extended precision result #
+# d0.b = condition code bits #
# #
# ALGORITHM *********************************************************** #
# The default overflow result can be determined by the sign of #
# the result and the rounding mode/prec in effect. These bits are #
-# concatenated together to create an index into the default result #
+# concatenated together to create an index into the default result #
# table. A pointer to the correct result is returned in a0. The #
-# resulting condition codes are returned in d0 in case the caller #
+# resulting condition codes are returned in d0 in case the caller #
# doesn't want FPSR_cc altered (as is the case for fmove out). #
# #
#########################################################################
@@ -22876,7 +22876,7 @@ ovf_res2:
ovf_res_load:
mov.b (tbl_ovfl_cc.b,%pc,%d0.w*1), %d0 # fetch result ccodes
lea (tbl_ovfl_result.b,%pc,%d1.w*8), %a0 # return result ptr
-
+
rts
tbl_ovfl_cc:
@@ -22937,18 +22937,18 @@ tbl_ovfl_result:
# #
# INPUT *************************************************************** #
# None #
-# #
+# #
# OUTPUT ************************************************************** #
# If no failure on _mem_read(): #
-# FP_SRC(a6) = packed operand now as a binary FP number #
+# FP_SRC(a6) = packed operand now as a binary FP number #
# #
# ALGORITHM *********************************************************** #
-# Get the correct <ea> whihc is the value on the exception stack #
+# Get the correct <ea> whihc is the value on the exception stack #
# frame w/ maybe a correction factor if the <ea> is -(an) or (an)+. #
# Then, fetch the operand from memory. If the fetch fails, exit #
# through facc_in_x(). #
# If the packed operand is a ZERO,NAN, or INF, convert it to #
-# its binary representation here. Else, call decbin() which will #
+# its binary representation here. Else, call decbin() which will #
# convert the packed value to an extended precision binary value. #
# #
#########################################################################
@@ -23005,7 +23005,7 @@ gp_not_spec:
# and NaN operands are dispatched without entering this routine) #
# value in 68881/882 format at location (a0). #
# #
-# A1. Convert the bcd exponent to binary by successive adds and #
+# A1. Convert the bcd exponent to binary by successive adds and #
# muls. Set the sign according to SE. Subtract 16 to compensate #
# for the mantissa which is to be interpreted as 17 integer #
# digits, rather than 1 integer and 16 fraction digits. #
@@ -23069,7 +23069,7 @@ RTABLE:
global decbin
decbin:
- mov.l 0x0(%a0),FP_SCR0_EX(%a6) # make a copy of input
+ mov.l 0x0(%a0),FP_SCR0_EX(%a6) # make a copy of input
mov.l 0x4(%a0),FP_SCR0_HI(%a6) # so we don't alter it
mov.l 0x8(%a0),FP_SCR0_LO(%a6)
@@ -23358,7 +23358,7 @@ ap_n_en:
#
# Pwrten calculates the exponent factor in the selected rounding mode
# according to the following table:
-#
+#
# Sign of Mant Sign of Exp Rounding Mode PWRTEN Rounding Mode
#
# ANY ANY RN RN
@@ -23446,7 +23446,7 @@ mul:
# it will be inex2, but will be reported as inex1 by get_op.
#
end_dec:
- fmov.l %fpsr,%d0 # get status register
+ fmov.l %fpsr,%d0 # get status register
bclr &inex2_bit+8,%d0 # test for inex2 and clear it
beq.b no_exc # skip this if no exc
ori.w &inx1a_mask,2+USER_FPSR(%a6) # set INEX1/AINEX
@@ -23463,16 +23463,16 @@ no_exc:
# #
# INPUT *************************************************************** #
# a0 = pointer to the input extended precision value in memory. #
-# the input may be either normalized, unnormalized, or #
+# the input may be either normalized, unnormalized, or #
# denormalized. #
-# d0 = contains the k-factor sign-extended to 32-bits. #
+# d0 = contains the k-factor sign-extended to 32-bits. #
# #
# OUTPUT ************************************************************** #
# FP_SCR0(a6) = bcd format result on the stack. #
# #
# ALGORITHM *********************************************************** #
# #
-# A1. Set RM and size ext; Set SIGMA = sign of input. #
+# A1. Set RM and size ext; Set SIGMA = sign of input. #
# The k-factor is saved for use in d7. Clear the #
# BINDEC_FLG for separating normalized/denormalized #
# input. If input is unnormalized or denormalized, #
@@ -23482,15 +23482,15 @@ no_exc:
# #
# A3. Compute ILOG. #
# ILOG is the log base 10 of the input value. It is #
-# approximated by adding e + 0.f when the original #
-# value is viewed as 2^^e * 1.f in extended precision. #
+# approximated by adding e + 0.f when the original #
+# value is viewed as 2^^e * 1.f in extended precision. #
# This value is stored in d6. #
# #
# A4. Clr INEX bit. #
-# The operation in A3 above may have set INEX2. #
+# The operation in A3 above may have set INEX2. #
# #
# A5. Set ICTR = 0; #
-# ICTR is a flag used in A13. It must be set before the #
+# ICTR is a flag used in A13. It must be set before the #
# loop entry A6. #
# #
# A6. Calculate LEN. #
@@ -23512,7 +23512,7 @@ no_exc:
# of ISCALE and X. A table is given in the code. #
# #
# A8. Clr INEX; Force RZ. #
-# The operation in A3 above may have set INEX2. #
+# The operation in A3 above may have set INEX2. #
# RZ mode is forced for the scaling operation to insure #
# only one rounding error. The grs bits are collected in #
# the INEX flag for use in A10. #
@@ -23543,11 +23543,11 @@ no_exc:
# the mantissa by 10. #
# #
# A14. Convert the mantissa to bcd. #
-# The binstr routine is used to convert the LEN digit #
+# The binstr routine is used to convert the LEN digit #
# mantissa to bcd in memory. The input to binstr is #
# to be a fraction; i.e. (mantissa)/10^LEN and adjusted #
# such that the decimal point is to the left of bit 63. #
-# The bcd digits are stored in the correct position in #
+# The bcd digits are stored in the correct position in #
# the final string area in memory. #
# #
# A15. Convert the exponent to bcd. #
@@ -23593,7 +23593,7 @@ RBDTBL:
# d2: upper 32-bits of mantissa for binstr
# d3: scratch;lower 32-bits of mantissa for binstr
# d4: LEN
-# d5: LAMBDA/ICTR
+# d5: LAMBDA/ICTR
# d6: ILOG
# d7: k-factor
# a0: ptr for original operand/final result
@@ -23617,7 +23617,7 @@ bindec:
# separating normalized/denormalized input. If the input
# is a denormalized number, set the BINDEC_FLG memory word
# to signal denorm. If the input is unnormalized, normalize
-# the input and test for denormalized result.
+# the input and test for denormalized result.
#
fmov.l &rm_mode*0x10,%fpcr # set RM and ext
mov.l (%a0),L_SCR2(%a6) # save exponent for sign check
@@ -23698,7 +23698,7 @@ A3_cont:
sub.w &0x3fff,%d0 # strip off bias
fadd.w %d0,%fp0 # add in exp
fsub.s FONE(%pc),%fp0 # subtract off 1.0
- fbge.w pos_res # if pos, branch
+ fbge.w pos_res # if pos, branch
fmul.x PLOG2UP1(%pc),%fp0 # if neg, mul by LOG2UP1
fmov.l %fp0,%d6 # put ILOG in d6 as a lword
bra.b A4_str # go move out ILOG
@@ -23708,14 +23708,14 @@ pos_res:
# A4. Clr INEX bit.
-# The operation in A3 above may have set INEX2.
+# The operation in A3 above may have set INEX2.
A4_str:
fmov.l &0,%fpsr # zero all of fpsr - nothing needed
# A5. Set ICTR = 0;
-# ICTR is a flag used in A13. It must be set before the
+# ICTR is a flag used in A13. It must be set before the
# loop entry A6. The lower word of d5 is used for ICTR.
clr.w %d5 # clear ICTR
@@ -23881,21 +23881,21 @@ e_next2:
bne.b e_loop2 # if not, loop
# A8. Clr INEX; Force RZ.
-# The operation in A3 above may have set INEX2.
+# The operation in A3 above may have set INEX2.
# RZ mode is forced for the scaling operation to insure
-# only one rounding error. The grs bits are collected in
+# only one rounding error. The grs bits are collected in
# the INEX flag for use in A10.
#
# Register usage:
# Input/Output
- fmov.l &0,%fpsr # clr INEX
+ fmov.l &0,%fpsr # clr INEX
fmov.l &rz_mode*0x10,%fpcr # set RZ rounding mode
# A9. Scale X -> Y.
# The mantissa is scaled to the desired number of significant
# digits. The excess digits are collected in INEX2. If mul,
-# Check d2 for excess 10 exponential value. If not zero,
+# Check d2 for excess 10 exponential value. If not zero,
# the iscale value would have caused the pwrten calculation
# to overflow. Only a negative iscale can cause this, so
# multiply by 10^(d2), which is now only allowed to be 24,
@@ -24026,7 +24026,7 @@ A10_st:
A11_st:
mov.l USER_FPCR(%a6),L_SCR1(%a6) # save it for later
- and.l &0x00000030,USER_FPCR(%a6) # set size to ext,
+ and.l &0x00000030,USER_FPCR(%a6) # set size to ext,
# ;block exceptions
@@ -24062,7 +24062,7 @@ A12_st:
lea.l FP_SCR1(%a6),%a0 # a0 is ptr to FP_SCR1(a6)
fmov.x %fp0,(%a0) # move Y to memory at FP_SCR1(a6)
tst.l L_SCR2(%a6) # test sign of original operand
- bge.b do_fint12 # if pos, use Y
+ bge.b do_fint12 # if pos, use Y
or.l &0x80000000,(%a0) # if neg, use -Y
do_fint12:
mov.l USER_FPSR(%a6),-(%sp)
@@ -24158,7 +24158,7 @@ A13_con:
subq.l &1,%d6 # subtract 1 from ILOG
mov.w &1,%d5 # set ICTR
fmov.l &rm_mode*0x10,%fpcr # set rmode to RM
- fmul.s FTEN(%pc),%fp2 # compute 10^LEN
+ fmul.s FTEN(%pc),%fp2 # compute 10^LEN
bra.w A6_str # return to A6 and recompute YINT
test_2:
fmul.s FTEN(%pc),%fp2 # compute 10^LEN
@@ -24174,7 +24174,7 @@ fix_ex:
fmov.l &rm_mode*0x10,%fpcr # set rmode to RM
bra.w A6_str # return to A6 and recompute YINT
#
-# Since ICTR <> 0, we have already been through one adjustment,
+# Since ICTR <> 0, we have already been through one adjustment,
# and shouldn't have another; this is to check if abs(YINT) = 10^LEN
# 10^LEN is again computed using whatever table is in a1 since the
# value calculated cannot be inexact.
@@ -24200,11 +24200,11 @@ z_next:
fmul.s FTEN(%pc),%fp2 # if LEN++, the get 10^^LEN
# A14. Convert the mantissa to bcd.
-# The binstr routine is used to convert the LEN digit
+# The binstr routine is used to convert the LEN digit
# mantissa to bcd in memory. The input to binstr is
# to be a fraction; i.e. (mantissa)/10^LEN and adjusted
# such that the decimal point is to the left of bit 63.
-# The bcd digits are stored in the correct position in
+# The bcd digits are stored in the correct position in
# the final string area in memory.
#
#
@@ -24247,7 +24247,7 @@ A14_st:
bgt.b no_sft # if so, don't shift
neg.l %d0 # make exp positive
m_loop:
- lsr.l &1,%d2 # shift d2:d3 right, add 0s
+ lsr.l &1,%d2 # shift d2:d3 right, add 0s
roxr.l &1,%d3 # the number of places
dbf.w %d0,m_loop # given in d0
no_sft:
@@ -24272,9 +24272,9 @@ zer_m:
#
# Digits are stored in L_SCR1(a6) on return from BINDEC as:
#
-# 32 16 15 0
+# 32 16 15 0
# -----------------------------------------
-# | 0 | e3 | e2 | e1 | e4 | X | X | X |
+# | 0 | e3 | e2 | e1 | e4 | X | X | X |
# -----------------------------------------
#
# And are moved into their proper places in FP_SCR0. If digit e4
@@ -24337,7 +24337,7 @@ convrt:
sub.w &0x3ffd,%d0 # subtract off bias
neg.w %d0 # make exp positive
x_loop:
- lsr.l &1,%d2 # shift d2:d3 right
+ lsr.l &1,%d2 # shift d2:d3 right
roxr.l &1,%d3 # the number of places
dbf.w %d0,x_loop # given in d0
x_loop_fin:
@@ -24348,12 +24348,12 @@ x_loop_fin:
mov.l &4,%d0 # put 4 in d0 for binstr call
lea.l L_SCR1(%a6),%a0 # a0 is ptr to L_SCR1 for exp digits
bsr binstr # call binstr to convert exp
- mov.l L_SCR1(%a6),%d0 # load L_SCR1 lword to d0
+ mov.l L_SCR1(%a6),%d0 # load L_SCR1 lword to d0
mov.l &12,%d1 # use d1 for shift count
lsr.l %d1,%d0 # shift d0 right by 12
bfins %d0,FP_SCR0(%a6){&4:&12} # put e3:e2:e1 in FP_SCR0
lsr.l %d1,%d0 # shift d0 right by 12
- bfins %d0,FP_SCR0(%a6){&16:&4} # put e4 in FP_SCR0
+ bfins %d0,FP_SCR0(%a6){&16:&4} # put e4 in FP_SCR0
tst.b %d0 # check if e4 is zero
beq.b A16_st # if zero, skip rest
or.l &opaop_mask,USER_FPSR(%a6) # set OPERR & AIOP in USER_FPSR
@@ -24384,14 +24384,14 @@ x_loop_fin:
A16_st:
clr.l %d0 # clr d0 for collection of signs
- and.b &0x0f,FP_SCR0(%a6) # clear first nibble of FP_SCR0
+ and.b &0x0f,FP_SCR0(%a6) # clear first nibble of FP_SCR0
tst.l L_SCR2(%a6) # check sign of original mantissa
bge.b mant_p # if pos, don't set SM
mov.l &2,%d0 # move 2 in to d0 for SM
mant_p:
tst.l %d6 # check sign of ILOG
bge.b wr_sgn # if pos, don't set SE
- addq.l &1,%d0 # set bit 0 in d0 for SE
+ addq.l &1,%d0 # set bit 0 in d0 for SE
wr_sgn:
bfins %d0,FP_SCR0(%a6){&0:&2} # insert SM and SE into FP_SCR0
@@ -24457,8 +24457,8 @@ PTENRM:
# d2:d3 = 64-bit binary integer #
# d0 = desired length (LEN) #
# a0 = pointer to start in memory for bcd characters #
-# (This pointer must point to byte 4 of the first #
-# lword of the packed decimal memory string.) #
+# (This pointer must point to byte 4 of the first #
+# lword of the packed decimal memory string.) #
# #
# OUTPUT ************************************************************** #
# a0 = pointer to LEN bcd digits representing the 64-bit integer. #
@@ -24598,14 +24598,14 @@ end_bstr:
# #
# INPUT *************************************************************** #
# None #
-# #
+# #
# OUTPUT ************************************************************** #
# None #
# #
# ALGORITHM *********************************************************** #
-# Flow jumps here when an FP data fetch call gets an error #
+# Flow jumps here when an FP data fetch call gets an error #
# result. This means the operating system wants an access error frame #
-# made out of the current exception stack frame. #
+# made out of the current exception stack frame. #
# So, we first call restore() which makes sure that any updated #
# -(an)+ register gets returned to its pre-exception value and then #
# we change the stack to an access error stack frame. #
@@ -24775,7 +24775,7 @@ ri_a7:
bne.b ri_a7_done # supervisor
movc %usp,%a0 # restore USP
sub.l %d0,%a0
- movc %a0,%usp
+ movc %a0,%usp
ri_a7_done:
rts
diff -puN arch/m68k/ifpsp060/src/ftest.S~m68k-superfluous-whitespace arch/m68k/ifpsp060/src/ftest.S
--- 25/arch/m68k/ifpsp060/src/ftest.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/ifpsp060/src/ftest.S Thu Apr 22 13:43:13 2004
@@ -5,10 +5,10 @@ M68060 Software Package
Production Release P1.00 -- October 10, 1994
M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved.
-
+
THE SOFTWARE is provided on an "AS IS" basis and without warranty.
To the maximum extent permitted by applicable law,
-MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
+MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
and any warranty against infringement with regard to the SOFTWARE
(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
@@ -86,7 +86,7 @@ test_fail:
#############################################
_060TESTS_:
link %a6,&-384
-
+
movm.l &0x3f3c,-(%sp)
fmovm.x &0xff,-(%sp)
@@ -138,7 +138,7 @@ _060TESTS_:
_060TESTS_unimp:
link %a6,&-384
-
+
movm.l &0x3f3c,-(%sp)
fmovm.x &0xff,-(%sp)
@@ -164,7 +164,7 @@ _060TESTS_unimp:
_060TESTS_enable:
link %a6,&-384
-
+
movm.l &0x3f3c,-(%sp)
fmovm.x &0xff,-(%sp)
@@ -687,7 +687,7 @@ fmovmx_0:
fmovm.l %fpcr,%fpsr,%fpiar,IFPCREGS(%a6)
fmovm.x &0xff,IFPREGS(%a6)
-
+
mov.w &0x0000,%cc
fmovm.x %d0,-(%sp)
@@ -753,7 +753,7 @@ fmovmx_1:
movm.l &0xffff,IREGS(%a6)
fmovm.l %fpcr,%fpsr,%fpiar,IFPCREGS(%a6)
-
+
mov.w &0x0000,%cc
fmovm.x (%sp)+,%d0
@@ -797,7 +797,7 @@ fmovmx_2:
fmovm.l %fpcr,%fpsr,%fpiar,IFPCREGS(%a6)
fmovm.x &0xff,IFPREGS(%a6)
-
+
mov.w &0x0000,%cc
fmovm.x %d0,-(%sp)
diff -puN arch/m68k/ifpsp060/src/ilsp.S~m68k-superfluous-whitespace arch/m68k/ifpsp060/src/ilsp.S
--- 25/arch/m68k/ifpsp060/src/ilsp.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/ifpsp060/src/ilsp.S Thu Apr 22 13:43:13 2004
@@ -5,10 +5,10 @@ M68060 Software Package
Production Release P1.00 -- October 10, 1994
M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved.
-
+
THE SOFTWARE is provided on an "AS IS" basis and without warranty.
To the maximum extent permitted by applicable law,
-MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
+MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
and any warranty against infringement with regard to the SOFTWARE
(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
@@ -27,7 +27,7 @@ No licenses are granted by implication,
or trademarks of Motorola, Inc.
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
# litop.s:
-# This file is appended to the top of the 060FPLSP package
+# This file is appended to the top of the 060FPLSP package
# and contains the entry points into the package. The user, in
# effect, branches to one of the branch table entries located here.
#
@@ -64,7 +64,7 @@ or trademarks of Motorola, Inc.
# _060LSP__idivs64_(): Emulate 64-bit signed div instruction. #
# #
# This is the library version which is accessed as a subroutine #
-# and therefore does not work exactly like the 680X0 div{s,u}.l #
+# and therefore does not work exactly like the 680X0 div{s,u}.l #
# 64-bit divide instruction. #
# #
# XREF **************************************************************** #
@@ -75,17 +75,17 @@ or trademarks of Motorola, Inc.
# 0x8(sp) = hi(dividend) #
# 0xc(sp) = lo(dividend) #
# 0x10(sp) = pointer to location to place quotient/remainder #
-# #
+# #
# OUTPUT ************************************************************** #
# 0x10(sp) = points to location of remainder/quotient. #
# remainder is in first longword, quotient is in 2nd. #
# #
# ALGORITHM *********************************************************** #
-# If the operands are signed, make them unsigned and save the #
+# If the operands are signed, make them unsigned and save the #
# sign info for later. Separate out special cases like divide-by-zero #
# or 32-bit divides if possible. Else, use a special math algorithm #
# to calculate the result. #
-# Restore sign info if signed instruction. Set the condition #
+# Restore sign info if signed instruction. Set the condition #
# codes before performing the final "rts". If the divisor was equal to #
# zero, then perform a divide-by-zero using a 16-bit implemented #
# divide instruction. This way, the operating system can record that #
@@ -135,8 +135,8 @@ ldiv64_cont:
beq.w ldiv64eq0 # divisor is = 0!!!
- mov.l 0xc(%a6), %d5 # get dividend hi
- mov.l 0x10(%a6), %d6 # get dividend lo
+ mov.l 0xc(%a6), %d5 # get dividend hi
+ mov.l 0x10(%a6), %d6 # get dividend lo
# separate signed and unsigned divide
tst.b POSNEG(%a6) # signed or unsigned?
@@ -161,7 +161,7 @@ ldsgndividend:
negx.l %d5
# extract some special cases:
-# - is (dividend == 0) ?
+# - is (dividend == 0) ?
# - is (hi(dividend) == 0 && (divisor <= lo(dividend))) ? (32-bit div)
ldspecialcases:
tst.l %d5 # is (hi(dividend) == 0)
@@ -170,7 +170,7 @@ ldspecialcases:
tst.l %d6 # is (lo(dividend) == 0), too
beq.w lddone # yes, so (dividend == 0)
- cmp.l %d7,%d6 # is (divisor <= lo(dividend))
+ cmp.l %d7,%d6 # is (divisor <= lo(dividend))
bls.b ld32bitdivide # yes, so use 32 bit divide
exg %d5,%d6 # q = 0, r = dividend
@@ -183,7 +183,7 @@ ld32bitdivide:
ldnormaldivide:
# last special case:
-# - is hi(dividend) >= divisor ? if yes, then overflow
+# - is hi(dividend) >= divisor ? if yes, then overflow
cmp.l %d7,%d5
bls.b lddovf # answer won't fit in 32 bits
@@ -196,7 +196,7 @@ ldivfinish:
beq.b lddone # divu has no processing!!!
# it was a divs.l, so ccode setting is a little more complicated...
- tst.b NDIVIDEND(%a6) # remainder has same sign
+ tst.b NDIVIDEND(%a6) # remainder has same sign
beq.b ldcc # as dividend.
neg.l %d5 # sgn(rem) = sgn(dividend)
ldcc:
@@ -240,8 +240,8 @@ ldexit:
# the result should be the unchanged dividend
lddovf:
- mov.l 0xc(%a6), %d5 # get dividend hi
- mov.l 0x10(%a6), %d6 # get dividend lo
+ mov.l 0xc(%a6), %d5 # get dividend hi
+ mov.l 0x10(%a6), %d6 # get dividend lo
andi.w &0x1c,DIV64_CC(%a6)
ori.w &0x02,DIV64_CC(%a6) # set 'V' ccode bit
@@ -271,8 +271,8 @@ ldiv64eq0:
# For this implementation b=2**16, and the target is U1U2U3U4/V1V2, #
# where U,V are words of the quadword dividend and longword divisor, #
# and U1, V1 are the most significant words. #
-# #
-# The most sig. longword of the 64 bit dividend must be in %d5, least #
+# #
+# The most sig. longword of the 64 bit dividend must be in %d5, least #
# in %d6. The divisor must be in the variable ddivisor, and the #
# signed/unsigned flag ddusign must be set (0=unsigned,1=signed). #
# The quotient is returned in %d6, remainder in %d5, unless the #
@@ -292,7 +292,7 @@ ldclassical:
# dividing the divisor word into each dividend word. In this case,
# the first two quotient words must be zero, or overflow would occur.
# Since we already checked this case above, we can treat the most significant
-# longword of the dividend as (0) remainder (see Knuth) and merely complete
+# longword of the dividend as (0) remainder (see Knuth) and merely complete
# the last two divisions to get a quotient longword and word remainder:
clr.l %d1
@@ -328,12 +328,12 @@ lddknuth:
clr.b DDSECOND(%a6) # clear flag for quotient digits
clr.l %d1 # %d1 will hold trial quotient
lddnchk:
- btst &31, %d7 # must we normalize? first word of
+ btst &31, %d7 # must we normalize? first word of
bne.b lddnormalized # divisor (V1) must be >= 65536/2
addq.l &0x1, DDNORMAL(%a6) # count normalization shifts
lsl.l &0x1, %d7 # shift the divisor
lsl.l &0x1, %d6 # shift u4,u3 with overflow to u2
- roxl.l &0x1, %d5 # shift u1,u2
+ roxl.l &0x1, %d5 # shift u1,u2
bra.w lddnchk
lddnormalized:
@@ -343,12 +343,12 @@ lddnormalized:
mov.l %d5, %d2 # dividend mslw
swap %d2
swap %d3
- cmp.w %d2, %d3 # V1 = U1 ?
+ cmp.w %d2, %d3 # V1 = U1 ?
bne.b lddqcalc1
mov.w &0xffff, %d1 # use max trial quotient word
bra.b lddadj0
lddqcalc1:
- mov.l %d5, %d1
+ mov.l %d5, %d1
divu.w %d3, %d1 # use quotient of mslw/msw
@@ -379,7 +379,7 @@ lddadj1: mov.l %d7, %d3
# add.l %d6, %d4 # (U1U2 - V1q) + U3
- cmp.l %d2, %d4
+ cmp.l %d2, %d4
bls.b lddadjd1 # is V2q > (U1U2-V1q) + U3 ?
subq.l &0x1, %d1 # yes, decrement and recheck
bra.b lddadj1
@@ -416,7 +416,7 @@ ldd2nd:
tst.b DDSECOND(%a6) # both q words done?
bne.b lddremain
# first quotient digit now correct. store digit and shift the
-# (subtracted) dividend
+# (subtracted) dividend
mov.w %d1, DDQUOTIENT(%a6)
clr.l %d1
swap %d5
@@ -427,7 +427,7 @@ ldd2nd:
bra.w lddnormalized
lddremain:
# add 2nd word to quotient, get the remainder.
- mov.w %d1, DDQUOTIENT+2(%a6)
+ mov.w %d1, DDQUOTIENT+2(%a6)
# shift down one word/digit to renormalize remainder.
mov.w %d5, %d6
swap %d6
@@ -441,7 +441,7 @@ lddnlp:
dbf %d7, lddnlp
lddrn:
mov.l %d6, %d5 # remainder
- mov.l DDQUOTIENT(%a6), %d6 # quotient
+ mov.l DDQUOTIENT(%a6), %d6 # quotient
rts
ldmm2:
@@ -471,7 +471,7 @@ ldmm2:
clr.w %d2 # lsw of two mixed products used,
swap %d5 # now use msws of longwords
swap %d2
- add.l %d2, %d5
+ add.l %d2, %d5
add.l %d3, %d5 # %d5 now ms 32 bits of final product
rts
@@ -491,7 +491,7 @@ ldmm2:
# 0x4(sp) = multiplier #
# 0x8(sp) = multiplicand #
# 0xc(sp) = pointer to location to place 64-bit result #
-# #
+# #
# OUTPUT ************************************************************** #
# 0xc(sp) = points to location of 64-bit result #
# #
@@ -524,9 +524,9 @@ _060LSP__imulu64_:
#########################################################################
# 63 32 0 #
-# ---------------------------- #
-# | hi(mplier) * hi(mplicand)| #
-# ---------------------------- #
+# ---------------------------- #
+# | hi(mplier) * hi(mplicand)| #
+# ---------------------------- #
# ----------------------------- #
# | hi(mplier) * lo(mplicand) | #
# ----------------------------- #
@@ -589,7 +589,7 @@ mulu64_ddone:
# the values at the location pointed to by a0.
# use movm here to not disturb the condition codes.
mulu64_end:
- exg %d1,%d0
+ exg %d1,%d0
movm.l &0x0003,([0x10,%a6]) # save result
# EPILOGUE BEGIN ########################################################
@@ -643,16 +643,16 @@ _060LSP__imuls64_:
# the result sign is the exclusive or of the operand sign bits.
muls64_chk_md_sgn:
tst.l %d1 # is multiplicand negative?
- bge.b muls64_alg # no
+ bge.b muls64_alg # no
neg.l %d1 # make multiplicand positive
eori.b &0x1,%d5 # calculate correct sign
#########################################################################
# 63 32 0 #
-# ---------------------------- #
-# | hi(mplier) * hi(mplicand)| #
-# ---------------------------- #
+# ---------------------------- #
+# | hi(mplier) * hi(mplicand)| #
+# ---------------------------- #
# ----------------------------- #
# | hi(mplier) * lo(mplicand) | #
# ----------------------------- #
@@ -726,7 +726,7 @@ muls64_ddone:
# the values at the location pointed to by a0.
# use movm here to not disturb the condition codes.
muls64_end:
- exg %d1,%d0
+ exg %d1,%d0
movm.l &0x0003,([0x10,%a6]) # save result at (a0)
# EPILOGUE BEGIN ########################################################
@@ -769,12 +769,12 @@ muls64_zero:
# INPUT *************************************************************** #
# 0x4(sp) = Rn #
# 0x8(sp) = pointer to boundary pair #
-# #
+# #
# OUTPUT ************************************************************** #
# cc = condition codes are set correctly #
# #
# ALGORITHM *********************************************************** #
-# In the interest of simplicity, all operands are converted to #
+# In the interest of simplicity, all operands are converted to #
# longword size whether the operation is byte, word, or long. The #
# bounds are sign extended accordingly. If Rn is a data regsiter, Rn is #
# also sign extended. If Rn is an address register, it need not be sign #
@@ -785,7 +785,7 @@ muls64_zero:
set CMP2_CC, -4
- global _060LSP__cmp2_Ab_
+ global _060LSP__cmp2_Ab_
_060LSP__cmp2_Ab_:
# PROLOGUE BEGIN ########################################################
@@ -795,7 +795,7 @@ _060LSP__cmp2_Ab_:
# PROLOGUE END ##########################################################
mov.w %cc,CMP2_CC(%a6)
- mov.l 0x8(%a6), %d2 # get regval
+ mov.l 0x8(%a6), %d2 # get regval
mov.b ([0xc,%a6],0x0),%d0
mov.b ([0xc,%a6],0x1),%d1
@@ -804,7 +804,7 @@ _060LSP__cmp2_Ab_:
extb.l %d1 # sign extend hi bnd
bra.w l_cmp2_cmp # go do the compare emulation
- global _060LSP__cmp2_Aw_
+ global _060LSP__cmp2_Aw_
_060LSP__cmp2_Aw_:
# PROLOGUE BEGIN ########################################################
@@ -814,7 +814,7 @@ _060LSP__cmp2_Aw_:
# PROLOGUE END ##########################################################
mov.w %cc,CMP2_CC(%a6)
- mov.l 0x8(%a6), %d2 # get regval
+ mov.l 0x8(%a6), %d2 # get regval
mov.w ([0xc,%a6],0x0),%d0
mov.w ([0xc,%a6],0x2),%d1
@@ -823,7 +823,7 @@ _060LSP__cmp2_Aw_:
ext.l %d1 # sign extend hi bnd
bra.w l_cmp2_cmp # go do the compare emulation
- global _060LSP__cmp2_Al_
+ global _060LSP__cmp2_Al_
_060LSP__cmp2_Al_:
# PROLOGUE BEGIN ########################################################
@@ -833,13 +833,13 @@ _060LSP__cmp2_Al_:
# PROLOGUE END ##########################################################
mov.w %cc,CMP2_CC(%a6)
- mov.l 0x8(%a6), %d2 # get regval
+ mov.l 0x8(%a6), %d2 # get regval
mov.l ([0xc,%a6],0x0),%d0
mov.l ([0xc,%a6],0x4),%d1
bra.w l_cmp2_cmp # go do the compare emulation
- global _060LSP__cmp2_Db_
+ global _060LSP__cmp2_Db_
_060LSP__cmp2_Db_:
# PROLOGUE BEGIN ########################################################
@@ -849,7 +849,7 @@ _060LSP__cmp2_Db_:
# PROLOGUE END ##########################################################
mov.w %cc,CMP2_CC(%a6)
- mov.l 0x8(%a6), %d2 # get regval
+ mov.l 0x8(%a6), %d2 # get regval
mov.b ([0xc,%a6],0x0),%d0
mov.b ([0xc,%a6],0x1),%d1
@@ -862,7 +862,7 @@ _060LSP__cmp2_Db_:
extb.l %d2 # sign extend data byte
bra.w l_cmp2_cmp # go do the compare emulation
- global _060LSP__cmp2_Dw_
+ global _060LSP__cmp2_Dw_
_060LSP__cmp2_Dw_:
# PROLOGUE BEGIN ########################################################
@@ -872,7 +872,7 @@ _060LSP__cmp2_Dw_:
# PROLOGUE END ##########################################################
mov.w %cc,CMP2_CC(%a6)
- mov.l 0x8(%a6), %d2 # get regval
+ mov.l 0x8(%a6), %d2 # get regval
mov.w ([0xc,%a6],0x0),%d0
mov.w ([0xc,%a6],0x2),%d1
@@ -885,7 +885,7 @@ _060LSP__cmp2_Dw_:
ext.l %d2 # sign extend data word
bra.w l_cmp2_cmp # go emulate compare
- global _060LSP__cmp2_Dl_
+ global _060LSP__cmp2_Dl_
_060LSP__cmp2_Dl_:
# PROLOGUE BEGIN ########################################################
@@ -895,14 +895,14 @@ _060LSP__cmp2_Dl_:
# PROLOGUE END ##########################################################
mov.w %cc,CMP2_CC(%a6)
- mov.l 0x8(%a6), %d2 # get regval
+ mov.l 0x8(%a6), %d2 # get regval
mov.l ([0xc,%a6],0x0),%d0
mov.l ([0xc,%a6],0x4),%d1
#
# To set the ccodes correctly:
-# (1) save 'Z' bit from (Rn - lo)
+# (1) save 'Z' bit from (Rn - lo)
# (2) save 'Z' and 'N' bits from ((hi - lo) - (Rn - hi))
# (3) keep 'X', 'N', and 'V' from before instruction
# (4) combine ccodes
@@ -912,7 +912,7 @@ l_cmp2_cmp:
mov.w %cc, %d3 # fetch resulting ccodes
andi.b &0x4, %d3 # keep 'Z' bit
sub.l %d0, %d1 # (hi - lo)
- cmp.l %d1,%d2 # ((hi - lo) - (Rn - hi))
+ cmp.l %d1,%d2 # ((hi - lo) - (Rn - hi))
mov.w %cc, %d4 # fetch resulting ccodes
or.b %d4, %d3 # combine w/ earlier ccodes
diff -puN arch/m68k/ifpsp060/src/isp.S~m68k-superfluous-whitespace arch/m68k/ifpsp060/src/isp.S
--- 25/arch/m68k/ifpsp060/src/isp.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/ifpsp060/src/isp.S Thu Apr 22 13:43:13 2004
@@ -5,10 +5,10 @@ M68060 Software Package
Production Release P1.00 -- October 10, 1994
M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved.
-
+
THE SOFTWARE is provided on an "AS IS" basis and without warranty.
To the maximum extent permitted by applicable law,
-MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
+MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
and any warranty against infringement with regard to the SOFTWARE
(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
@@ -322,21 +322,21 @@ set immed_bit, 0x7 # immediate data b
# Misc. #
#########
set BYTE, 1 # len(byte) == 1 byte
-set WORD, 2 # len(word) == 2 bytes
-set LONG, 4 # len(longword) == 4 bytes
+set WORD, 2 # len(word) == 2 bytes
+set LONG, 4 # len(longword) == 4 bytes
#########################################################################
# XDEF **************************************************************** #
# _isp_unimp(): 060ISP entry point for Unimplemented Instruction #
# #
-# This handler should be the first code executed upon taking the #
-# "Unimplemented Integer Instruction" exception in an operating #
+# This handler should be the first code executed upon taking the #
+# "Unimplemented Integer Instruction" exception in an operating #
# system. #
# #
# XREF **************************************************************** #
# _imem_read_{word,long}() - read instruction word/longword #
# _mul64() - emulate 64-bit multiply #
-# _div64() - emulate 64-bit divide #
+# _div64() - emulate 64-bit divide #
# _moveperipheral() - emulate "movep" #
# _compandset() - emulate misaligned "cas" #
# _compandset2() - emulate "cas2" #
@@ -349,7 +349,7 @@ set LONG, 4 # len(longword) == 4 byt
# #
# INPUT *************************************************************** #
# - The system stack contains the Unimp Int Instr stack frame #
-# #
+# #
# OUTPUT ************************************************************** #
# If Trace exception: #
# - The system stack changed to contain Trace exc stack frame #
@@ -366,8 +366,8 @@ set LONG, 4 # len(longword) == 4 byt
# This handler fetches the first instruction longword from #
# memory and decodes it to determine which of the unimplemented #
# integer instructions caused this exception. This handler then calls #
-# one of _mul64(), _div64(), _moveperipheral(), _compandset(), #
-# _compandset2(), or _chk2_cmp2() as appropriate. #
+# one of _mul64(), _div64(), _moveperipheral(), _compandset(), #
+# _compandset2(), or _chk2_cmp2() as appropriate. #
# Some of these instructions, by their nature, may produce other #
# types of exceptions. "div" can produce a divide-by-zero exception, #
# and "chk2" can cause a "Chk" exception. In both cases, the current #
@@ -375,7 +375,7 @@ set LONG, 4 # len(longword) == 4 byt
# of the correct exception type and an exit must be made through #
# _real_divbyzero() or _real_chk() as appropriate. In addition, all #
# instructions may be executing while Trace is enabled. If so, then #
-# a Trace exception stack frame must be created and an exit made #
+# a Trace exception stack frame must be created and an exit made #
# through _real_trace(). #
# Meanwhile, if any read or write to memory using the #
# _mem_{read,write}() "callout"s returns a failing value, then an #
@@ -384,19 +384,19 @@ set LONG, 4 # len(longword) == 4 byt
# If none of these occur, then a normal exit is made through #
# _isp_done(). #
# #
-# This handler, upon entry, saves almost all user-visible #
+# This handler, upon entry, saves almost all user-visible #
# address and data registers to the stack. Although this may seem to #
# cause excess memory traffic, it was found that due to having to #
# access these register files for things like data retrieval and <ea> #
# calculations, it was more efficient to have them on the stack where #
-# they could be accessed by indexing rather than to make subroutine #
-# calls to retrieve a register of a particular index. #
+# they could be accessed by indexing rather than to make subroutine #
+# calls to retrieve a register of a particular index. #
# #
#########################################################################
global _isp_unimp
_isp_unimp:
- link.w %a6,&-LOCAL_SIZE # create room for stack frame
+ link.w %a6,&-LOCAL_SIZE # create room for stack frame
movm.l &0x3fff,EXC_DREGS(%a6) # store d0-d7/a0-a5
mov.l (%a6),EXC_A6(%a6) # store a6
@@ -428,9 +428,9 @@ uieh_cont:
bsr.l _imem_read_long # fetch opword & extword
mov.l %d0,EXC_OPWORD(%a6) # store extword on stack
-
+
#########################################################################
-# muls.l 0100 1100 00 |<ea>| 0*** 1100 0000 0*** #
+# muls.l 0100 1100 00 |<ea>| 0*** 1100 0000 0*** #
# mulu.l 0100 1100 00 |<ea>| 0*** 0100 0000 0*** #
# #
# divs.l 0100 1100 01 |<ea>| 0*** 1100 0000 0*** #
@@ -514,7 +514,7 @@ uieh_div64_a7:
tst.b EXC_ISR(%a6) # no; is trace enabled?
bmi.w uieh_trace_a7 # yes
bra.w uieh_a7 # no
-
+
#
# now, w/ group2, make movep's decode the fastest since it will
# most likely be used the most.
@@ -532,7 +532,7 @@ uieh_not_movep:
beq.b uieh_chk2cmp2 # go handle chk2,cmp2
swap %d0 # put opword in lo word
- cmpi.b %d0,&0xfc # test for cas2
+ cmpi.b %d0,&0xfc # test for cas2
beq.b uieh_cas2 # go handle cas2
uieh_cas:
@@ -585,7 +585,7 @@ uieh_done:
mov.l %a0,%usp # restore it
uieh_finish:
- movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5
+ movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5
btst &0x7,EXC_ISR(%a6) # is trace mode on?
bne.b uieh_trace # yes;go handle trace mode
@@ -596,7 +596,7 @@ uieh_finish:
bra.l _isp_done
#
-# The instruction that was just emulated was also being traced. The trace
+# The instruction that was just emulated was also being traced. The trace
# trap for this instruction will be lost unless we jump to the trace handler.
# So, here we create a Trace Exception format number two exception stack
# frame from the Unimplemented Integer Intruction Exception stack frame
@@ -607,11 +607,11 @@ uieh_finish:
# * 0x0 * 0x0f4 * * Current *
# ***************** * PC *
# * Current * *****************
-# * PC * * 0x2 * 0x024 *
+# * PC * * 0x2 * 0x024 *
# ***************** *****************
# * SR * * Next *
# ***************** * PC *
-# ->* Old * *****************
+# ->* Old * *****************
# from link -->* A6 * * SR *
# ***************** *****************
# /* A7 * * New * <-- for final unlink
@@ -651,7 +651,7 @@ uieh_trace:
#
uieh_chk_trap:
mov.b EXC_CC+1(%a6),EXC_ISR+1(%a6) # insert new ccodes
- movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5
+ movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5
mov.w EXC_ISR(%a6),(%a6) # put new SR on stack
mov.l EXC_IPC(%a6),0x8(%a6) # put "Current PC" on stack
@@ -678,14 +678,14 @@ uieh_chk_trap:
# *****************
# (6 words)
#
-# the divide instruction should take an integer divide by zero trap. so, here
-# we must create a divbyzero stack frame from an unimplemented integer
-# instruction exception frame and jump to the user supplied entry point
+# the divide instruction should take an integer divide by zero trap. so, here
+# we must create a divbyzero stack frame from an unimplemented integer
+# instruction exception frame and jump to the user supplied entry point
# "_real_divbyzero()".
#
uieh_divbyzero:
mov.b EXC_CC+1(%a6),EXC_ISR+1(%a6) # insert new ccodes
- movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5
+ movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5
mov.w EXC_ISR(%a6),(%a6) # put new SR on stack
mov.l EXC_IPC(%a6),0x8(%a6) # put "Current PC" on stack
@@ -712,9 +712,9 @@ uieh_divbyzero:
# ***************** *****************
# (4 words) (6 words)
#
-# the divide instruction should take an integer divide by zero trap. so, here
-# we must create a divbyzero stack frame from an unimplemented integer
-# instruction exception frame and jump to the user supplied entry point
+# the divide instruction should take an integer divide by zero trap. so, here
+# we must create a divbyzero stack frame from an unimplemented integer
+# instruction exception frame and jump to the user supplied entry point
# "_real_divbyzero()".
#
# However, we must also deal with the fact that (a7)+ was used from supervisor
@@ -722,7 +722,7 @@ uieh_divbyzero:
#
uieh_divbyzero_a7:
mov.b EXC_CC+1(%a6),EXC_ISR+1(%a6) # insert new ccodes
- movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5
+ movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5
mov.l EXC_IPC(%a6),0xc(%a6) # put "Current PC" on stack
mov.w &0x2014,0xa(%a6) # put Vector Offset on stack
@@ -748,8 +748,8 @@ uieh_divbyzero_a7:
# ***************** *****************
# (4 words) (6 words)
#
-#
-# The instruction that was just emulated was also being traced. The trace
+#
+# The instruction that was just emulated was also being traced. The trace
# trap for this instruction will be lost unless we jump to the trace handler.
# So, here we create a Trace Exception format number two exception stack
# frame from the Unimplemented Integer Intruction Exception stack frame
@@ -760,7 +760,7 @@ uieh_divbyzero_a7:
#
uieh_trace_a7:
mov.b EXC_CC+1(%a6),EXC_ISR+1(%a6) # insert new ccodes
- movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5
+ movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5
mov.l EXC_IPC(%a6),0xc(%a6) # put "Current PC" on stack
mov.w &0x2024,0xa(%a6) # put Vector Offset on stack
@@ -772,12 +772,12 @@ uieh_trace_a7:
bra.l _real_trace
#
-# UIEH FRAME
+# UIEH FRAME
# *****************
# * 0x0 * 0x0f4 *
# UIEH FRAME *****************
# ***************** * Next *
-# * 0x0 * 0x0f4 * * PC *
+# * 0x0 * 0x0f4 * * PC *
# ***************** *****************
# * Current * * SR *
# * PC * *****************
@@ -787,7 +787,7 @@ uieh_trace_a7:
# (4 words)
uieh_a7:
mov.b EXC_CC+1(%a6),EXC_ISR+1(%a6) # insert new ccodes
- movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5
+ movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5
mov.w &0x00f4,0xe(%a6) # put Vector Offset on stack
mov.l EXC_EXTWPTR(%a6),0xa(%a6) # put "Next PC" on stack
@@ -803,11 +803,11 @@ uieh_a7:
# a0 = failing address
# d0 = fslw
isp_dacc:
- mov.l %a0,(%a6) # save address
+ mov.l %a0,(%a6) # save address
mov.l %d0,-0x4(%a6) # save partial fslw
lea -64(%a6),%sp
- movm.l (%sp)+,&0x7fff # restore d0-d7/a0-a6
+ movm.l (%sp)+,&0x7fff # restore d0-d7/a0-a6
mov.l 0xc(%sp),-(%sp) # move voff,hi(pc)
mov.l 0x4(%sp),0x10(%sp) # store fslw
@@ -822,11 +822,11 @@ isp_dacc:
# FSLW:
# misaligned = true
# read = true
-# size = word
-# instruction = true
-# software emulation error = true
+# size = word
+# instruction = true
+# software emulation error = true
isp_iacc:
- movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5
+ movm.l EXC_DREGS(%a6),&0x3fff # restore d0-d7/a0-a5
unlk %a6 # unlink frame
sub.w &0x8,%sp # make room for acc frame
mov.l 0x8(%sp),(%sp) # store sr,lo(pc)
@@ -840,7 +840,7 @@ isp_acc_exit:
beq.b isp_acc_exit2 # user
bset &0x2,0xd(%sp) # set supervisor TM bit
isp_acc_exit2:
- bra.l _real_access
+ bra.l _real_access
# if the addressing mode was (an)+ or -(an), the address register must
# be restored to its pre-exception value before entering _real_access.
@@ -858,14 +858,14 @@ isp_restore_done:
# _calc_ea(): routine to calculate effective address #
# #
# XREF **************************************************************** #
-# _imem_read_word() - read instruction word #
-# _imem_read_long() - read instruction longword #
-# _dmem_read_long() - read data longword (for memory indirect) #
-# isp_iacc() - handle instruction access error exception #
+# _imem_read_word() - read instruction word #
+# _imem_read_long() - read instruction longword #
+# _dmem_read_long() - read data longword (for memory indirect) #
+# isp_iacc() - handle instruction access error exception #
# isp_dacc() - handle data access error exception #
# #
# INPUT *************************************************************** #
-# d0 = number of bytes related to effective address (w,l) #
+# d0 = number of bytes related to effective address (w,l) #
# #
# OUTPUT ************************************************************** #
# If exiting through isp_dacc... #
@@ -877,22 +877,22 @@ isp_restore_done:
# a0 = effective address #
# #
# ALGORITHM *********************************************************** #
-# The effective address type is decoded from the opword residing #
-# on the stack. A jump table is used to vector to a routine for the #
+# The effective address type is decoded from the opword residing #
+# on the stack. A jump table is used to vector to a routine for the #
# appropriate mode. Since none of the emulated integer instructions #
# uses byte-sized operands, only handle word and long operations. #
# #
-# Dn,An - shouldn't enter here #
+# Dn,An - shouldn't enter here #
# (An) - fetch An value from stack #
-# -(An) - fetch An value from stack; return decr value; #
+# -(An) - fetch An value from stack; return decr value; #
# place decr value on stack; store old value in case of #
-# future access error; if -(a7), set mda7_flg in #
+# future access error; if -(a7), set mda7_flg in #
# SPCOND_FLG #
# (An)+ - fetch An value from stack; return value; #
# place incr value on stack; store old value in case of #
# future access error; if (a7)+, set mia7_flg in #
# SPCOND_FLG #
-# (d16,An) - fetch An value from stack; read d16 using #
+# (d16,An) - fetch An value from stack; read d16 using #
# _imem_read_word(); fetch may fail -> branch to #
# isp_iacc() #
# (xxx).w,(xxx).l - use _imem_read_{word,long}() to fetch #
@@ -904,7 +904,7 @@ isp_restore_done:
# isp_iacc() #
# everything else - read needed displacements as appropriate w/ #
# _imem_read_{word,long}(); read may fail; if memory #
-# indirect, read indirect address using #
+# indirect, read indirect address using #
# _dmem_read_long() which may also fail #
# #
#########################################################################
@@ -944,59 +944,59 @@ tbl_ea_mode:
short tbl_ea_mode - tbl_ea_mode
short tbl_ea_mode - tbl_ea_mode
- short addr_ind_a0 - tbl_ea_mode
- short addr_ind_a1 - tbl_ea_mode
- short addr_ind_a2 - tbl_ea_mode
- short addr_ind_a3 - tbl_ea_mode
- short addr_ind_a4 - tbl_ea_mode
- short addr_ind_a5 - tbl_ea_mode
- short addr_ind_a6 - tbl_ea_mode
- short addr_ind_a7 - tbl_ea_mode
-
- short addr_ind_p_a0 - tbl_ea_mode
- short addr_ind_p_a1 - tbl_ea_mode
- short addr_ind_p_a2 - tbl_ea_mode
- short addr_ind_p_a3 - tbl_ea_mode
- short addr_ind_p_a4 - tbl_ea_mode
- short addr_ind_p_a5 - tbl_ea_mode
- short addr_ind_p_a6 - tbl_ea_mode
- short addr_ind_p_a7 - tbl_ea_mode
-
- short addr_ind_m_a0 - tbl_ea_mode
- short addr_ind_m_a1 - tbl_ea_mode
- short addr_ind_m_a2 - tbl_ea_mode
- short addr_ind_m_a3 - tbl_ea_mode
- short addr_ind_m_a4 - tbl_ea_mode
- short addr_ind_m_a5 - tbl_ea_mode
- short addr_ind_m_a6 - tbl_ea_mode
- short addr_ind_m_a7 - tbl_ea_mode
-
- short addr_ind_disp_a0 - tbl_ea_mode
- short addr_ind_disp_a1 - tbl_ea_mode
- short addr_ind_disp_a2 - tbl_ea_mode
- short addr_ind_disp_a3 - tbl_ea_mode
- short addr_ind_disp_a4 - tbl_ea_mode
- short addr_ind_disp_a5 - tbl_ea_mode
- short addr_ind_disp_a6 - tbl_ea_mode
+ short addr_ind_a0 - tbl_ea_mode
+ short addr_ind_a1 - tbl_ea_mode
+ short addr_ind_a2 - tbl_ea_mode
+ short addr_ind_a3 - tbl_ea_mode
+ short addr_ind_a4 - tbl_ea_mode
+ short addr_ind_a5 - tbl_ea_mode
+ short addr_ind_a6 - tbl_ea_mode
+ short addr_ind_a7 - tbl_ea_mode
+
+ short addr_ind_p_a0 - tbl_ea_mode
+ short addr_ind_p_a1 - tbl_ea_mode
+ short addr_ind_p_a2 - tbl_ea_mode
+ short addr_ind_p_a3 - tbl_ea_mode
+ short addr_ind_p_a4 - tbl_ea_mode
+ short addr_ind_p_a5 - tbl_ea_mode
+ short addr_ind_p_a6 - tbl_ea_mode
+ short addr_ind_p_a7 - tbl_ea_mode
+
+ short addr_ind_m_a0 - tbl_ea_mode
+ short addr_ind_m_a1 - tbl_ea_mode
+ short addr_ind_m_a2 - tbl_ea_mode
+ short addr_ind_m_a3 - tbl_ea_mode
+ short addr_ind_m_a4 - tbl_ea_mode
+ short addr_ind_m_a5 - tbl_ea_mode
+ short addr_ind_m_a6 - tbl_ea_mode
+ short addr_ind_m_a7 - tbl_ea_mode
+
+ short addr_ind_disp_a0 - tbl_ea_mode
+ short addr_ind_disp_a1 - tbl_ea_mode
+ short addr_ind_disp_a2 - tbl_ea_mode
+ short addr_ind_disp_a3 - tbl_ea_mode
+ short addr_ind_disp_a4 - tbl_ea_mode
+ short addr_ind_disp_a5 - tbl_ea_mode
+ short addr_ind_disp_a6 - tbl_ea_mode
short addr_ind_disp_a7 - tbl_ea_mode
- short _addr_ind_ext - tbl_ea_mode
- short _addr_ind_ext - tbl_ea_mode
- short _addr_ind_ext - tbl_ea_mode
- short _addr_ind_ext - tbl_ea_mode
- short _addr_ind_ext - tbl_ea_mode
- short _addr_ind_ext - tbl_ea_mode
- short _addr_ind_ext - tbl_ea_mode
- short _addr_ind_ext - tbl_ea_mode
-
- short abs_short - tbl_ea_mode
- short abs_long - tbl_ea_mode
- short pc_ind - tbl_ea_mode
- short pc_ind_ext - tbl_ea_mode
- short immediate - tbl_ea_mode
- short tbl_ea_mode - tbl_ea_mode
- short tbl_ea_mode - tbl_ea_mode
- short tbl_ea_mode - tbl_ea_mode
+ short _addr_ind_ext - tbl_ea_mode
+ short _addr_ind_ext - tbl_ea_mode
+ short _addr_ind_ext - tbl_ea_mode
+ short _addr_ind_ext - tbl_ea_mode
+ short _addr_ind_ext - tbl_ea_mode
+ short _addr_ind_ext - tbl_ea_mode
+ short _addr_ind_ext - tbl_ea_mode
+ short _addr_ind_ext - tbl_ea_mode
+
+ short abs_short - tbl_ea_mode
+ short abs_long - tbl_ea_mode
+ short pc_ind - tbl_ea_mode
+ short pc_ind_ext - tbl_ea_mode
+ short immediate - tbl_ea_mode
+ short tbl_ea_mode - tbl_ea_mode
+ short tbl_ea_mode - tbl_ea_mode
+ short tbl_ea_mode - tbl_ea_mode
###################################
# Address register indirect: (An) #
@@ -1041,7 +1041,7 @@ addr_ind_p_a0:
mov.l EXC_A0(%a6),%a0 # load current value
add.l %a0,%d0 # increment
mov.l %d0,EXC_A0(%a6) # save incremented value
-
+
mov.l %a0,EXC_SAVVAL(%a6) # save in case of access error
mov.b &0x0,EXC_SAVREG(%a6) # save regno, too
mov.b &restore_flg,SPCOND_FLG(%a6) # set flag
@@ -1339,7 +1339,7 @@ _addr_ind_ext:
mov.l %a0,%d3 # put base in d3
bra.l calc_mem_ind # calc memory indirect
-
+
addr_ind_index_8bit:
mov.l %d2,-(%sp) # save old d2
@@ -1370,8 +1370,8 @@ aii8_long:
# Immediate: #<data> #
#########################################################################
# word, long: <ea> of the data is the current extension word #
-# pointer value. new extension word pointer is simply the old #
-# plus the number of bytes in the data type(2 or 4). #
+# pointer value. new extension word pointer is simply the old #
+# plus the number of bytes in the data type(2 or 4). #
#########################################################################
immediate:
mov.b &immed_flg,SPCOND_FLG(%a6) # set immediate flag
@@ -1455,9 +1455,9 @@ pc_ind_ext:
mov.l %a0,%d3 # put base in d3
bra.l calc_mem_ind # calc memory indirect
-
+
pc_ind_index_8bit:
- mov.l %d2,-(%sp) # create a temp register
+ mov.l %d2,-(%sp) # create a temp register
mov.l %d0,%d1 # make extword copy
rol.w &0x4,%d1 # rotate reg num into place
@@ -1512,14 +1512,14 @@ base_supp_ck:
no_base_sup:
bfextu %d5{&26:&2},%d0 # get bd size
# beq.l _error # if (size == 0) it's reserved
- cmpi.b %d0,&2
+ cmpi.b %d0,&2
blt.b no_bd
beq.b get_word_bd
mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
bsr.l _imem_read_long
-
+
tst.l %d1 # ifetch error?
bne.l isp_iacc # yes
@@ -1533,16 +1533,16 @@ get_word_bd:
bne.l isp_iacc # yes
ext.l %d0 # sign extend bd
-
+
chk_ind:
add.l %d0,%d3 # base += bd
no_bd:
bfextu %d5{&30:&2},%d0 # is od suppressed?
beq.w aii_bd
- cmpi.b %d0,&0x2
+ cmpi.b %d0,&0x2
blt.b null_od
beq.b word_od
-
+
mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
bsr.l _imem_read_long
@@ -1550,7 +1550,7 @@ no_bd:
tst.l %d1 # ifetch error?
bne.l isp_iacc # yes
- bra.b add_them
+ bra.b add_them
word_od:
mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
@@ -1604,10 +1604,10 @@ done_ea:
# must create an access error frame. here, we pass a skeleton fslw
# and the failing address to the routine that creates the new frame.
# FSLW:
-# read = true
-# size = longword
+# read = true
+# size = longword
# TM = data
-# software emulation error = true
+# software emulation error = true
calc_ea_err:
mov.l %d3,%a0 # pass failing address
mov.l &0x01010001,%d0 # pass fslw
@@ -1615,7 +1615,7 @@ calc_ea_err:
#########################################################################
# XDEF **************************************************************** #
-# _moveperipheral(): routine to emulate movep instruction #
+# _moveperipheral(): routine to emulate movep instruction #
# #
# XREF **************************************************************** #
# _dmem_read_byte() - read byte from memory #
@@ -1647,7 +1647,7 @@ calc_ea_err:
# movep.(w,l) Dx,(d,Ay) #
# movep.(w,l) (d,Ay),Dx #
###########################
- global _moveperipheral
+ global _moveperipheral
_moveperipheral:
mov.w EXC_OPWORD(%a6),%d1 # fetch the opcode word
@@ -1793,11 +1793,11 @@ m2rltrans:
mov.b EXC_OPWORD(%a6),%d1
lsr.b &0x1,%d1
and.w &0x7,%d1 # extract Dx from opcode word
-
+
mov.l %d2,(EXC_DREGS,%a6,%d1.w*4) # store dx
rts
-
+
# a0 = dst addr
m2rwtrans:
mov.l %a0,%a2 # store addr
@@ -1823,7 +1823,7 @@ m2rwtrans:
mov.b EXC_OPWORD(%a6),%d1
lsr.b &0x1,%d1
and.w &0x7,%d1 # extract Dx from opcode word
-
+
mov.w %d2,(EXC_DREGS+2,%a6,%d1.w*4) # store dx
rts
@@ -1832,7 +1832,7 @@ m2rwtrans:
# must create an access error frame. here, we pass a skeleton fslw
# and the failing address to the routine that creates the new frame.
# FSLW:
-# write = true
+# write = true
# size = byte
# TM = data
# software emulation error = true
@@ -1842,7 +1842,7 @@ movp_write_err:
bra.l isp_dacc
# FSLW:
-# read = true
+# read = true
# size = byte
# TM = data
# software emulation error = true
@@ -1853,12 +1853,12 @@ movp_read_err:
#########################################################################
# XDEF **************************************************************** #
-# _chk2_cmp2(): routine to emulate chk2/cmp2 instructions #
+# _chk2_cmp2(): routine to emulate chk2/cmp2 instructions #
# #
# XREF **************************************************************** #
# _calc_ea(): calculate effective address #
# _dmem_read_long(): read operands #
-# _dmem_read_word(): read operands #
+# _dmem_read_word(): read operands #
# isp_dacc(): handle data access error exception #
# #
# INPUT *************************************************************** #
@@ -1869,25 +1869,25 @@ movp_read_err:
# a0 = failing address #
# d0 = FSLW #
# else #
-# none #
+# none #
# #
# ALGORITHM *********************************************************** #
# First, calculate the effective address, then fetch the byte, #
-# word, or longword sized operands. Then, in the interest of #
-# simplicity, all operands are converted to longword size whether the #
-# operation is byte, word, or long. The bounds are sign extended #
-# accordingly. If Rn is a data regsiter, Rn is also sign extended. If #
-# Rn is an address register, it need not be sign extended since the #
+# word, or longword sized operands. Then, in the interest of #
+# simplicity, all operands are converted to longword size whether the #
+# operation is byte, word, or long. The bounds are sign extended #
+# accordingly. If Rn is a data regsiter, Rn is also sign extended. If #
+# Rn is an address register, it need not be sign extended since the #
# full register is always used. #
# The comparisons are made and the condition codes calculated. #
# If the instruction is chk2 and the Rn value is out-of-bounds, set #
# the ichk_flg in SPCOND_FLG. #
-# If the memory fetch returns a failing value, pass the failing #
+# If the memory fetch returns a failing value, pass the failing #
# address and FSLW to the isp_dacc() routine. #
# #
#########################################################################
- global _chk2_cmp2
+ global _chk2_cmp2
_chk2_cmp2:
# passing size parameter doesn't matter since chk2 & cmp2 can't do
@@ -1974,7 +1974,7 @@ chk2_cmp2_byte:
#
# To set the ccodes correctly:
-# (1) save 'Z' bit from (Rn - lo)
+# (1) save 'Z' bit from (Rn - lo)
# (2) save 'Z' and 'N' bits from ((hi - lo) - (Rn - hi))
# (3) keep 'X', 'N', and 'V' from before instruction
# (4) combine ccodes
@@ -1984,7 +1984,7 @@ chk2_cmp2_compare:
mov.w %cc, %d3 # fetch resulting ccodes
andi.b &0x4, %d3 # keep 'Z' bit
sub.l %d0, %d1 # (hi - lo)
- cmp.l %d1,%d2 # ((hi - lo) - (Rn - hi))
+ cmp.l %d1,%d2 # ((hi - lo) - (Rn - hi))
mov.w %cc, %d4 # fetch resulting ccodes
or.b %d4, %d3 # combine w/ earlier ccodes
@@ -2003,7 +2003,7 @@ chk2_cmp2_compare:
# this code handles the only difference between chk2 and cmp2. chk2 would
# have trapped out if the value was out of bounds. we check this by seeing
# if the 'N' bit was set by the operation.
-chk2_finish:
+chk2_finish:
btst &0x0, %d4 # is 'N' bit set?
bne.b chk2_trap # yes;chk2 should trap
rts
@@ -2018,7 +2018,7 @@ chk2_trap:
# read = true
# size = longword
# TM = data
-# software emulation error = true
+# software emulation error = true
chk2_cmp2_err_l:
mov.l %a2,%a0 # pass failing address
mov.l &0x01010001,%d0 # pass fslw
@@ -2028,7 +2028,7 @@ chk2_cmp2_err_l:
# read = true
# size = word
# TM = data
-# software emulation error = true
+# software emulation error = true
chk2_cmp2_err_w:
mov.l %a2,%a0 # pass failing address
mov.l &0x01410001,%d0 # pass fslw
@@ -2036,12 +2036,12 @@ chk2_cmp2_err_w:
#########################################################################
# XDEF **************************************************************** #
-# _div64(): routine to emulate div{u,s}.l <ea>,Dr:Dq #
+# _div64(): routine to emulate div{u,s}.l <ea>,Dr:Dq #
# 64/32->32r:32q #
# #
# XREF **************************************************************** #
# _calc_ea() - calculate effective address #
-# isp_iacc() - handle instruction access error exception #
+# isp_iacc() - handle instruction access error exception #
# isp_dacc() - handle data access error exception #
# isp_restore() - restore An on access error w/ -() or ()+ #
# #
@@ -2049,24 +2049,24 @@ chk2_cmp2_err_w:
# none #
# #
# OUTPUT ************************************************************** #
-# If exiting through isp_dacc... #
+# If exiting through isp_dacc... #
# a0 = failing address #
-# d0 = FSLW #
+# d0 = FSLW #
# else #
# none #
# #
# ALGORITHM *********************************************************** #
-# First, decode the operand location. If it's in Dn, fetch from #
-# the stack. If it's in memory, use _calc_ea() to calculate the #
+# First, decode the operand location. If it's in Dn, fetch from #
+# the stack. If it's in memory, use _calc_ea() to calculate the #
# effective address. Use _dmem_read_long() to fetch at that address. #
# Unless the operand is immediate data. Then use _imem_read_long(). #
# Send failures to isp_dacc() or isp_iacc() as appropriate. #
-# If the operands are signed, make them unsigned and save the #
+# If the operands are signed, make them unsigned and save the #
# sign info for later. Separate out special cases like divide-by-zero #
# or 32-bit divides if possible. Else, use a special math algorithm #
-# to calculate the result. #
-# Restore sign info if signed instruction. Set the condition #
-# codes. Set idbyz_flg in SPCOND_FLG if divisor was zero. Store the #
+# to calculate the result. #
+# Restore sign info if signed instruction. Set the condition #
+# codes. Set idbyz_flg in SPCOND_FLG if divisor was zero. Store the #
# quotient and remainder in the appropriate data registers on the stack.#
# #
#########################################################################
@@ -2131,7 +2131,7 @@ dsgndividend:
negx.l %d5
# extract some special cases:
-# - is (dividend == 0) ?
+# - is (dividend == 0) ?
# - is (hi(dividend) == 0 && (divisor <= lo(dividend))) ? (32-bit div)
dspecialcases:
tst.l %d5 # is (hi(dividend) == 0)
@@ -2140,7 +2140,7 @@ dspecialcases:
tst.l %d6 # is (lo(dividend) == 0), too
beq.w ddone # yes, so (dividend == 0)
- cmp.l %d7,%d6 # is (divisor <= lo(dividend))
+ cmp.l %d7,%d6 # is (divisor <= lo(dividend))
bls.b d32bitdivide # yes, so use 32 bit divide
exg %d5,%d6 # q = 0, r = dividend
@@ -2153,7 +2153,7 @@ d32bitdivide:
dnormaldivide:
# last special case:
-# - is hi(dividend) >= divisor ? if yes, then overflow
+# - is hi(dividend) >= divisor ? if yes, then overflow
cmp.l %d7,%d5
bls.b ddovf # answer won't fit in 32 bits
@@ -2166,7 +2166,7 @@ divfinish:
beq.b ddone # divu has no processing!!!
# it was a divs.l, so ccode setting is a little more complicated...
- tst.b NDIVIDEND(%a6) # remainder has same sign
+ tst.b NDIVIDEND(%a6) # remainder has same sign
beq.b dcc # as dividend.
neg.l %d5 # sgn(rem) = sgn(dividend)
dcc:
@@ -2194,7 +2194,7 @@ ddone:
mov.w %cc, EXC_CC(%a6)
mov.w NDRSAVE(%a6), %d0 # get Dr off stack
- mov.w NDQSAVE(%a6), %d1 # get Dq off stack
+ mov.w NDQSAVE(%a6), %d1 # get Dq off stack
# if the register numbers are the same, only the quotient gets saved.
# so, if we always save the quotient second, we save ourselves a cmp&beq
@@ -2221,8 +2221,8 @@ div64eq0:
# For this implementation b=2**16, and the target is U1U2U3U4/V1V2, #
# where U,V are words of the quadword dividend and longword divisor, #
# and U1, V1 are the most significant words. #
-# #
-# The most sig. longword of the 64 bit dividend must be in %d5, least #
+# #
+# The most sig. longword of the 64 bit dividend must be in %d5, least #
# in %d6. The divisor must be in the variable ddivisor, and the #
# signed/unsigned flag ddusign must be set (0=unsigned,1=signed). #
# The quotient is returned in %d6, remainder in %d5, unless the #
@@ -2242,7 +2242,7 @@ dclassical:
# dividing the divisor word into each dividend word. In this case,
# the first two quotient words must be zero, or overflow would occur.
# Since we already checked this case above, we can treat the most significant
-# longword of the dividend as (0) remainder (see Knuth) and merely complete
+# longword of the dividend as (0) remainder (see Knuth) and merely complete
# the last two divisions to get a quotient longword and word remainder:
clr.l %d1
@@ -2278,12 +2278,12 @@ ddknuth:
clr.b DDSECOND(%a6) # clear flag for quotient digits
clr.l %d1 # %d1 will hold trial quotient
ddnchk:
- btst &31, %d7 # must we normalize? first word of
+ btst &31, %d7 # must we normalize? first word of
bne.b ddnormalized # divisor (V1) must be >= 65536/2
addq.l &0x1, DDNORMAL(%a6) # count normalization shifts
lsl.l &0x1, %d7 # shift the divisor
lsl.l &0x1, %d6 # shift u4,u3 with overflow to u2
- roxl.l &0x1, %d5 # shift u1,u2
+ roxl.l &0x1, %d5 # shift u1,u2
bra.w ddnchk
ddnormalized:
@@ -2293,12 +2293,12 @@ ddnormalized:
mov.l %d5, %d2 # dividend mslw
swap %d2
swap %d3
- cmp.w %d2, %d3 # V1 = U1 ?
+ cmp.w %d2, %d3 # V1 = U1 ?
bne.b ddqcalc1
mov.w &0xffff, %d1 # use max trial quotient word
bra.b ddadj0
ddqcalc1:
- mov.l %d5, %d1
+ mov.l %d5, %d1
divu.w %d3, %d1 # use quotient of mslw/msw
@@ -2329,7 +2329,7 @@ ddadj1: mov.l %d7, %d3
# add.l %d6, %d4 # (U1U2 - V1q) + U3
- cmp.l %d2, %d4
+ cmp.l %d2, %d4
bls.b ddadjd1 # is V2q > (U1U2-V1q) + U3 ?
subq.l &0x1, %d1 # yes, decrement and recheck
bra.b ddadj1
@@ -2366,7 +2366,7 @@ dd2nd:
tst.b DDSECOND(%a6) # both q words done?
bne.b ddremain
# first quotient digit now correct. store digit and shift the
-# (subtracted) dividend
+# (subtracted) dividend
mov.w %d1, DDQUOTIENT(%a6)
clr.l %d1
swap %d5
@@ -2377,7 +2377,7 @@ dd2nd:
bra.w ddnormalized
ddremain:
# add 2nd word to quotient, get the remainder.
- mov.w %d1, DDQUOTIENT+2(%a6)
+ mov.w %d1, DDQUOTIENT+2(%a6)
# shift down one word/digit to renormalize remainder.
mov.w %d5, %d6
swap %d6
@@ -2391,7 +2391,7 @@ ddnlp:
dbf %d7, ddnlp
ddrn:
mov.l %d6, %d5 # remainder
- mov.l DDQUOTIENT(%a6), %d6 # quotient
+ mov.l DDQUOTIENT(%a6), %d6 # quotient
rts
dmm2:
@@ -2421,7 +2421,7 @@ dmm2:
clr.w %d2 # lsw of two mixed products used,
swap %d5 # now use msws of longwords
swap %d2
- add.l %d2, %d5
+ add.l %d2, %d5
add.l %d3, %d5 # %d5 now ms 32 bits of final product
rts
@@ -2463,10 +2463,10 @@ dimmed:
# also, we call isp_restore in case the effective addressing mode was
# (an)+ or -(an) in which case the previous "an" value must be restored.
# FSLW:
-# read = true
-# size = longword
+# read = true
+# size = longword
# TM = data
-# software emulation error = true
+# software emulation error = true
div64_err:
bsr.l isp_restore # restore addr reg
mov.l %a2,%a0 # pass failing address
@@ -2480,17 +2480,17 @@ div64_err:
# XREF **************************************************************** #
# _calc_ea() - calculate effective address #
# isp_iacc() - handle instruction access error exception #
-# isp_dacc() - handle data access error exception #
+# isp_dacc() - handle data access error exception #
# isp_restore() - restore An on access error w/ -() or ()+ #
# #
# INPUT *************************************************************** #
# none #
# #
# OUTPUT ************************************************************** #
-# If exiting through isp_dacc... #
+# If exiting through isp_dacc... #
# a0 = failing address #
# d0 = FSLW #
-# else #
+# else #
# none #
# #
# ALGORITHM *********************************************************** #
@@ -2499,9 +2499,9 @@ div64_err:
# effective address. Use _dmem_read_long() to fetch at that address. #
# Unless the operand is immediate data. Then use _imem_read_long(). #
# Send failures to isp_dacc() or isp_iacc() as appropriate. #
-# If the operands are signed, make them unsigned and save the #
+# If the operands are signed, make them unsigned and save the #
# sign info for later. Perform the multiplication using 16x16->32 #
-# unsigned multiplies and "add" instructions. Store the high and low #
+# unsigned multiplies and "add" instructions. Store the high and low #
# portions of the result in the appropriate data registers on the #
# stack. Calculate the condition codes, also. #
# #
@@ -2554,15 +2554,15 @@ mul64_multiplicand:
# the result sign is the exclusive or of the operand sign bits.
mul64_chk_md_sgn:
tst.l %d4 # is multiplicand negative?
- bge.b mul64_alg # no
+ bge.b mul64_alg # no
neg.l %d4 # make multiplicand positive
eori.b &0x1, EXC_TEMP(%a6) # calculate correct sign
#########################################################################
# 63 32 0 #
-# ---------------------------- #
-# | hi(mplier) * hi(mplicand)| #
-# ---------------------------- #
+# ---------------------------- #
+# | hi(mplier) * hi(mplicand)| #
+# ---------------------------- #
# ----------------------------- #
# | hi(mplier) * lo(mplicand) | #
# ----------------------------- #
@@ -2639,7 +2639,7 @@ mul64_done:
andi.b &0x8, %d7 # extract 'N' bit
mul64_ccode_set:
- mov.b EXC_CC+1(%a6), %d6 # fetch previous %ccr
+ mov.b EXC_CC+1(%a6), %d6 # fetch previous %ccr
andi.b &0x10, %d6 # all but 'X' bit changes
or.b %d7, %d6 # group 'X' and 'N'
@@ -2698,10 +2698,10 @@ mul64_immed:
# also, we call isp_restore in case the effective addressing mode was
# (an)+ or -(an) in which case the previous "an" value must be restored.
# FSLW:
-# read = true
-# size = longword
+# read = true
+# size = longword
# TM = data
-# software emulation error = true
+# software emulation error = true
mul64_err:
bsr.l isp_restore # restore addr reg
mov.l %a2,%a0 # pass failing address
@@ -2728,7 +2728,7 @@ mul64_err:
# #
# _isp_cas2_finish(): #
# see cas2 core emulation code #
-# #
+# #
# OUTPUT ************************************************************** #
# _compandset2(): #
# see cas2 core emulation code #
@@ -2744,7 +2744,7 @@ mul64_err:
# pages from being paged out. If either _real_lock_page() fails, exit #
# through _cas_terminate2(). Don't forget to unlock the 1st locked page #
# using _real_unlock_paged() if the 2nd lock-page fails. #
-# Finally, branch to the core cas2 emulation code by calling the #
+# Finally, branch to the core cas2 emulation code by calling the #
# "callout" _real_cas2(). #
# #
# _isp_cas2_finish(): #
@@ -2793,7 +2793,7 @@ _compandset2:
lsr.w &0x6,%d1
andi.w &0x7,%d1 # extract Du1
mov.l (EXC_DREGS,%a6,%d1.w*4),%d4 # fetch Update1 Op
-
+
andi.w &0x7,%d0 # extract Dc1
mov.l (EXC_DREGS,%a6,%d0.w*4),%d2 # fetch Compare1 Op
mov.w %d0,DC1(%a6)
@@ -2827,7 +2827,7 @@ _compandset2:
bra.l _real_cas2
-# if the 2nd lock attempt fails, then we must still unlock the
+# if the 2nd lock attempt fails, then we must still unlock the
# first page(s).
cas_preterm:
mov.l %d0,-(%sp) # save FSLW
@@ -2869,7 +2869,7 @@ cas2_finish_w_done:
sf %d1 # pass size
mov.l ADDR1(%a6),%a0 # pass ADDR1
bsr.l _real_unlock_page # unlock page
-
+
mov.l %d2,%d0 # pass mode
sf %d1 # pass size
mov.l ADDR2(%a6),%a0 # pass ADDR2
@@ -2900,7 +2900,7 @@ cas2_finish_l_done:
st %d1 # pass size
mov.l ADDR1(%a6),%a0 # pass ADDR1
bsr.l _real_unlock_page # unlock page
-
+
mov.l %d2,%d0 # pass mode
st %d1 # pass size
mov.l ADDR2(%a6),%a0 # pass ADDR2
@@ -2928,11 +2928,11 @@ cr_cas2:
# (external to package) #
# #
# XREF **************************************************************** #
-# _calc_ea(): calculate effective address #
+# _calc_ea(): calculate effective address #
# #
# INPUT *************************************************************** #
# compandset(): #
-# none #
+# none #
# _isp_cas_restart(): #
# d6 = previous sfc/dfc #
# _isp_cas_finish(): #
@@ -2959,10 +2959,10 @@ cr_cas2:
# ALGORITHM *********************************************************** #
# #
# compandset(): #
-# First, calculate the effective address. Then, decode the #
+# First, calculate the effective address. Then, decode the #
# instruction word and fetch the "compare" (DC) and "update" (Du) #
# operands. #
-# Next, call the external routine _real_lock_page() so that the #
+# Next, call the external routine _real_lock_page() so that the #
# operating system can keep this page from being paged out while we're #
# in this routine. If this call fails, jump to _cas_terminate2(). #
# The routine then branches to _real_cas(). This external routine #
@@ -2971,7 +2971,7 @@ cr_cas2:
# this purpose. #
# #
# _isp_cas_finish(): #
-# Either way, after emulation, the package is re-entered at #
+# Either way, after emulation, the package is re-entered at #
# _isp_cas_finish(). This routine re-compares the operands in order to #
# set the condition codes. Finally, these routines will call #
# _real_unlock_page() in order to unlock the pages that were previously #
@@ -2984,13 +2984,13 @@ cr_cas2:
# _isp_cas_terminate(): #
# This routine can be entered from an access error handler where #
# an emulation operand access failed and the operating system would #
-# like an access error stack frame created instead of the current #
+# like an access error stack frame created instead of the current #
# unimplemented integer instruction frame. #
-# Also, the package enters here if a call to _real_lock_page() #
+# Also, the package enters here if a call to _real_lock_page() #
# fails. #
# #
# _isp_cas_inrange(): #
-# Checks to see whether the instruction address passed to it in #
+# Checks to see whether the instruction address passed to it in #
# a0 is within the software package cas/cas2 emulation routines. This #
# can be helpful for an operating system to determine whether an access #
# error during emulation was due to a cas/cas2 emulation access. #
@@ -3003,18 +3003,18 @@ set ADDR, EXC_TEMP+0x4
global _compandset
_compandset:
btst &0x1,EXC_OPWORD(%a6) # word or long operation?
- bne.b compandsetl # long
+ bne.b compandsetl # long
compandsetw:
movq.l &0x2,%d0 # size = 2 bytes
- bsr.l _calc_ea # a0 = calculated <ea>
+ bsr.l _calc_ea # a0 = calculated <ea>
mov.l %a0,ADDR(%a6) # save <ea> for possible restart
sf %d7 # clear d7 for word size
bra.b compandsetfetch
compandsetl:
movq.l &0x4,%d0 # size = 4 bytes
- bsr.l _calc_ea # a0 = calculated <ea>
+ bsr.l _calc_ea # a0 = calculated <ea>
mov.l %a0,ADDR(%a6) # save <ea> for possible restart
st %d7 # set d7 for longword size
@@ -3040,7 +3040,7 @@ compandsetfetch:
tst.l %d0 # did error occur?
bne.w _cas_terminate2 # yes, clean up the mess
mov.l %a2,%a0 # pass addr in a0
-
+
bra.l _real_cas
########
@@ -3053,7 +3053,7 @@ _isp_cas_finish:
# from the locked routine...
cas_finish_w:
mov.w EXC_CC(%a6),%cc # restore cc
- cmp.w %d0,%d4 # do word compare
+ cmp.w %d0,%d4 # do word compare
mov.w %cc,EXC_CC(%a6) # save cc
tst.b %d1 # update compare reg?
@@ -3074,7 +3074,7 @@ cas_finish_w_done:
# from the locked routine...
cas_finish_l:
mov.w EXC_CC(%a6),%cc # restore cc
- cmp.l %d0,%d4 # do longword compare
+ cmp.l %d0,%d4 # do longword compare
mov.w %cc,EXC_CC(%a6) # save cc
tst.b %d1 # update compare reg?
@@ -3092,7 +3092,7 @@ cas_finish_l_done:
rts
########
-
+
global _isp_cas_restart
_isp_cas_restart:
mov.l %d6,%sfc # restore previous sfc
@@ -3104,7 +3104,7 @@ cr_cas:
mov.l ADDR(%a6),%a0 # load <ea>
btst &0x1,EXC_OPWORD(%a6) # word or long operation?
sne %d7 # set d7 accordingly
- bra.w compandsetfetch
+ bra.w compandsetfetch
########
@@ -3151,7 +3151,7 @@ _isp_cas_inrange:
cmp.l %a0,%a1 # is PC in range?
blt.b cin_no # no
rts # yes; return d0 = 0
-cin_no:
+cin_no:
mov.l &-0x1,%d0 # out of range; return d0 = -1
rts
@@ -3179,28 +3179,28 @@ cin_no:
# #
# XREF **************************************************************** #
# _isp_cas2_finish() - only exit point for this emulation code; #
-# do clean-up; calculate ccodes; store #
+# do clean-up; calculate ccodes; store #
# Compare Ops if appropriate. #
# #
# INPUT *************************************************************** #
# *see chart below* #
-# #
+# #
# OUTPUT ************************************************************** #
# *see chart below* #
# #
# ALGORITHM *********************************************************** #
# (1) Make several copies of the effective address. #
# (2) Save current SR; Then mask off all maskable interrupts. #
-# (3) Save current SFC/DFC (ASSUMED TO BE EQUAL!!!); Then set #
-# according to whether exception occurred in user or #
+# (3) Save current SFC/DFC (ASSUMED TO BE EQUAL!!!); Then set #
+# according to whether exception occurred in user or #
# supervisor mode. #
# (4) Use "plpaw" instruction to pre-load ATC with effective #
# address pages(s). THIS SHOULD NOT FAULT!!! The relevant #
# page(s) should have already been made resident prior to #
-# entering this routine. #
-# (5) Push the operand lines from the cache w/ "cpushl". #
+# entering this routine. #
+# (5) Push the operand lines from the cache w/ "cpushl". #
# In the 68040, this was done within the locked region. In #
-# the 68060, it is done outside of the locked region. #
+# the 68060, it is done outside of the locked region. #
# (6) Use "plpar" instruction to do a re-load of ATC entries for #
# ADDR1 since ADDR2 entries may have pushed ADDR1 out of the #
# ATC. #
@@ -3214,19 +3214,19 @@ cin_no:
# back to itself (as w/ the '040) so we can gracefully unlock #
# the bus (and assert LOCKE*) using BUSCR and the final move. #
# (12)Exit. #
-# (13)Write update operand to the DST locations. Use BUSCR to #
+# (13)Write update operand to the DST locations. Use BUSCR to #
# assert LOCKE* for the final write operation. #
# (14)Exit. #
# #
-# The algorithm is actually implemented slightly differently #
-# depending on the size of the operation and the misalignment of the #
+# The algorithm is actually implemented slightly differently #
+# depending on the size of the operation and the misalignment of the #
# operands. A misaligned operand must be written in aligned chunks or #
# else the BUSCR register control gets confused. #
# #
#########################################################################
#################################################################
-# THIS IS THE STATE OF THE INTEGER REGISTER FILE UPON #
+# THIS IS THE STATE OF THE INTEGER REGISTER FILE UPON #
# ENTERING _isp_cas2(). #
# #
# D0 = xxxxxxxx #
@@ -3236,7 +3236,7 @@ cin_no:
# D4 = update oper 1 #
# D5 = update oper 2 #
# D6 = 'xxxxxxff if supervisor mode; 'xxxxxx00 if user mode #
-# D7 = 'xxxxxxff if longword operation; 'xxxxxx00 if word #
+# D7 = 'xxxxxxff if longword operation; 'xxxxxx00 if word #
# A0 = ADDR1 #
# A1 = ADDR2 #
# A2 = xxxxxxxx #
@@ -3339,22 +3339,22 @@ cas2l:
# A4 = bus unlock value
# A5 = xxxxxxxx
#
- align 0x10
+ align 0x10
CAS2L_START:
movc %a2,%buscr # assert LOCK*
movs.l (%a1),%d1 # fetch Dest2[31:0]
movs.l (%a0),%d0 # fetch Dest1[31:0]
- bra.b CAS2L_CONT
+ bra.b CAS2L_CONT
CAS2L_ENTER:
bra.b ~+16
CAS2L_CONT:
- cmp.l %d0,%d2 # Dest1 - Compare1
+ cmp.l %d0,%d2 # Dest1 - Compare1
bne.b CAS2L_NOUPDATE
- cmp.l %d1,%d3 # Dest2 - Compare2
+ cmp.l %d1,%d3 # Dest2 - Compare2
bne.b CAS2L_NOUPDATE
movs.l %d5,(%a1) # Update2[31:0] -> DEST2
- bra.b CAS2L_UPDATE
+ bra.b CAS2L_UPDATE
bra.b ~+16
CAS2L_UPDATE:
@@ -3384,7 +3384,7 @@ CAS2L_FILLER:
####
#################################################################
-# THIS MUST BE THE STATE OF THE INTEGER REGISTER FILE UPON #
+# THIS MUST BE THE STATE OF THE INTEGER REGISTER FILE UPON #
# ENTERING _isp_cas2(). #
# #
# D0 = destination[31:0] operand 1 #
@@ -3430,22 +3430,22 @@ cas2l_update_done:
bra.l _isp_cas2_finish
####
- align 0x10
+ align 0x10
CAS2L2_START:
movc %a2,%buscr # assert LOCK*
movs.l (%a1),%d1 # fetch Dest2[31:0]
movs.l (%a0),%d0 # fetch Dest1[31:0]
- bra.b CAS2L2_CONT
+ bra.b CAS2L2_CONT
CAS2L2_ENTER:
bra.b ~+16
CAS2L2_CONT:
- cmp.l %d0,%d2 # Dest1 - Compare1
+ cmp.l %d0,%d2 # Dest1 - Compare1
bne.b CAS2L2_NOUPDATE
- cmp.l %d1,%d3 # Dest2 - Compare2
+ cmp.l %d1,%d3 # Dest2 - Compare2
bne.b CAS2L2_NOUPDATE
movs.l %d5,(%a1) # Update2[31:0] -> Dest2
- bra.b CAS2L2_UPDATE
+ bra.b CAS2L2_UPDATE
bra.b ~+16
CAS2L2_UPDATE:
@@ -3490,22 +3490,22 @@ CAS2L2_FILLER:
#################################
- align 0x10
+ align 0x10
CAS2L3_START:
movc %a2,%buscr # assert LOCK*
movs.l (%a1),%d1 # fetch Dest2[31:0]
movs.l (%a0),%d0 # fetch Dest1[31:0]
- bra.b CAS2L3_CONT
+ bra.b CAS2L3_CONT
CAS2L3_ENTER:
bra.b ~+16
CAS2L3_CONT:
- cmp.l %d0,%d2 # Dest1 - Compare1
+ cmp.l %d0,%d2 # Dest1 - Compare1
bne.b CAS2L3_NOUPDATE
- cmp.l %d1,%d3 # Dest2 - Compare2
+ cmp.l %d1,%d3 # Dest2 - Compare2
bne.b CAS2L3_NOUPDATE
movs.l %d5,(%a1) # Update2[31:0] -> DEST2
- bra.b CAS2L3_UPDATE
+ bra.b CAS2L3_UPDATE
bra.b ~+16
CAS2L3_UPDATE:
@@ -3531,7 +3531,7 @@ CAS2L3_UPDATE3:
nop
nop
bra.b ~+16
-
+
CAS2L3_NOUPDATE:
rol.l &0x8,%d0 # get Dest1[31:24]
movs.b %d0,(%a0)+ # Dest1[31:24] -> DEST1
@@ -3639,22 +3639,22 @@ cas2w:
# A4 = bus unlock value
# A5 = xxxxxxxx
#
- align 0x10
+ align 0x10
CAS2W_START:
movc %a2,%buscr # assert LOCK*
movs.w (%a1),%d1 # fetch Dest2[15:0]
movs.w (%a0),%d0 # fetch Dest1[15:0]
- bra.b CAS2W_CONT2
+ bra.b CAS2W_CONT2
CAS2W_ENTER:
bra.b ~+16
CAS2W_CONT2:
- cmp.w %d0,%d2 # Dest1 - Compare1
+ cmp.w %d0,%d2 # Dest1 - Compare1
bne.b CAS2W_NOUPDATE
- cmp.w %d1,%d3 # Dest2 - Compare2
+ cmp.w %d1,%d3 # Dest2 - Compare2
bne.b CAS2W_NOUPDATE
movs.w %d5,(%a1) # Update2[15:0] -> DEST2
- bra.b CAS2W_UPDATE
+ bra.b CAS2W_UPDATE
bra.b ~+16
CAS2W_UPDATE:
@@ -3684,7 +3684,7 @@ CAS2W_FILLER:
####
#################################################################
-# THIS MUST BE THE STATE OF THE INTEGER REGISTER FILE UPON #
+# THIS MUST BE THE STATE OF THE INTEGER REGISTER FILE UPON #
# ENTERING _isp_cas2(). #
# #
# D0 = destination[15:0] operand 1 #
@@ -3730,22 +3730,22 @@ cas2w_update_done:
bra.l _isp_cas2_finish
####
- align 0x10
+ align 0x10
CAS2W2_START:
movc %a2,%buscr # assert LOCK*
movs.w (%a1),%d1 # fetch Dest2[15:0]
movs.w (%a0),%d0 # fetch Dest1[15:0]
- bra.b CAS2W2_CONT2
+ bra.b CAS2W2_CONT2
CAS2W2_ENTER:
bra.b ~+16
CAS2W2_CONT2:
- cmp.w %d0,%d2 # Dest1 - Compare1
+ cmp.w %d0,%d2 # Dest1 - Compare1
bne.b CAS2W2_NOUPDATE
- cmp.w %d1,%d3 # Dest2 - Compare2
+ cmp.w %d1,%d3 # Dest2 - Compare2
bne.b CAS2W2_NOUPDATE
movs.w %d5,(%a1) # Update2[15:0] -> DEST2
- bra.b CAS2W2_UPDATE
+ bra.b CAS2W2_UPDATE
bra.b ~+16
CAS2W2_UPDATE:
@@ -3789,34 +3789,34 @@ CAS2W2_FILLER:
bra.b CAS2W2_START
# ###### ## ######
-# # # # #
+# # # # #
# # ###### ######
# # # # #
# ###### # # ######
#########################################################################
# XDEF **************************************************************** #
-# _isp_cas(): "core" emulation code for the cas instruction #
+# _isp_cas(): "core" emulation code for the cas instruction #
# #
# XREF **************************************************************** #
# _isp_cas_finish() - only exit point for this emulation code; #
# do clean-up #
# #
# INPUT *************************************************************** #
-# *see entry chart below* #
+# *see entry chart below* #
# #
# OUTPUT ************************************************************** #
# *see exit chart below* #
# #
# ALGORITHM *********************************************************** #
-# (1) Make several copies of the effective address. #
-# (2) Save current SR; Then mask off all maskable interrupts. #
+# (1) Make several copies of the effective address. #
+# (2) Save current SR; Then mask off all maskable interrupts. #
# (3) Save current DFC/SFC (ASSUMED TO BE EQUAL!!!); Then set #
# SFC/DFC according to whether exception occurred in user or #
# supervisor mode. #
# (4) Use "plpaw" instruction to pre-load ATC with efective #
# address page(s). THIS SHOULD NOT FAULT!!! The relevant #
-# page(s) should have been made resident prior to entering #
+# page(s) should have been made resident prior to entering #
# this routine. #
# (5) Push the operand lines from the cache w/ "cpushl". #
# In the 68040, this was done within the locked region. In #
@@ -3834,8 +3834,8 @@ CAS2W2_FILLER:
# (12)Write update operand to the DST location. Use BUSCR to #
# assert LOCKE* for the final write operation. #
# (13)Exit. #
-# #
-# The algorithm is actually implemented slightly differently #
+# #
+# The algorithm is actually implemented slightly differently #
# depending on the size of the operation and the misalignment of the #
# operand. A misaligned operand must be written in aligned chunks or #
# else the BUSCR register control gets confused. #
@@ -3934,9 +3934,9 @@ casw:
CASW_START:
movc %a1,%buscr # assert LOCK*
movs.w (%a0),%d0 # fetch Dest[15:0]
- cmp.w %d0,%d4 # Dest - Compare
+ cmp.w %d0,%d4 # Dest - Compare
bne.b CASW_NOUPDATE
- bra.b CASW_UPDATE
+ bra.b CASW_UPDATE
CASW_ENTER:
bra.b ~+16
@@ -3961,7 +3961,7 @@ CASW_NOUPDATE:
movs.b %d0,(%a0)+ # Dest[15:8] -> DEST
movc %a2,%buscr # assert LOCKE*
rol.l &0x8,%d0 # get Dest[7:0]
- bra.b CASW_NOUPDATE2
+ bra.b CASW_NOUPDATE2
bra.b ~+16
CASW_NOUPDATE2:
@@ -4090,9 +4090,9 @@ casl:
CASL_START:
movc %a1,%buscr # assert LOCK*
movs.l (%a0),%d0 # fetch Dest[31:0]
- cmp.l %d0,%d4 # Dest - Compare
+ cmp.l %d0,%d4 # Dest - Compare
bne.b CASL_NOUPDATE
- bra.b CASL_UPDATE
+ bra.b CASL_UPDATE
CASL_ENTER:
bra.b ~+16
@@ -4117,7 +4117,7 @@ CASL_NOUPDATE:
movs.w %d0,(%a0)+ # Dest[31:16] -> DEST
swap %d0 # get Dest[15:0]
movc %a2,%buscr # assert LOCKE*
- bra.b CASL_NOUPDATE2
+ bra.b CASL_NOUPDATE2
bra.b ~+16
CASL_NOUPDATE2:
@@ -4214,7 +4214,7 @@ casl2:
mov.l &0xa0000000,%a2 # assert LOCKE* buscr value
mov.l &0x00000000,%a3 # buscr unlock value
-# pre-load the instruction cache for the following algorithm.
+# pre-load the instruction cache for the following algorithm.
# this will minimize the number of cycles that LOCK* will be asserted.
bra.b CASL2_ENTER # start pre-loading icache
@@ -4238,9 +4238,9 @@ casl2:
CASL2_START:
movc %a1,%buscr # assert LOCK*
movs.l (%a0),%d0 # fetch Dest[31:0]
- cmp.l %d0,%d4 # Dest - Compare
+ cmp.l %d0,%d4 # Dest - Compare
bne.b CASL2_NOUPDATE
- bra.b CASL2_UPDATE
+ bra.b CASL2_UPDATE
CASL2_ENTER:
bra.b ~+16
@@ -4263,14 +4263,14 @@ CASL2_NOUPDATE:
movs.b %d0,(%a0)+ # Dest[31:24] -> DEST
swap %d0 # get Dest[23:8]
movs.w %d0,(%a0)+ # Dest[23:8] -> DEST+0x1
- bra.b CASL2_NOUPDATE2
+ bra.b CASL2_NOUPDATE2
bra.b ~+16
CASL2_NOUPDATE2:
rol.l &0x8,%d0 # get Dest[7:0]
movc %a2,%buscr # assert LOCKE*
movs.b %d0,(%a0) # Dest[7:0] -> DEST+0x3
- bra.b CASL2_NOUPDATE3
+ bra.b CASL2_NOUPDATE3
nop
bra.b ~+16
diff -puN arch/m68k/ifpsp060/src/itest.S~m68k-superfluous-whitespace arch/m68k/ifpsp060/src/itest.S
--- 25/arch/m68k/ifpsp060/src/itest.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/ifpsp060/src/itest.S Thu Apr 22 13:43:13 2004
@@ -5,10 +5,10 @@ M68060 Software Package
Production Release P1.00 -- October 10, 1994
M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved.
-
+
THE SOFTWARE is provided on an "AS IS" basis and without warranty.
To the maximum extent permitted by applicable law,
-MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
+MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
and any warranty against infringement with regard to the SOFTWARE
(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
@@ -453,8 +453,8 @@ movp_1:
bne.l error
#####################################################
-# movep.w %d0,(0x0,%a0) #
-# - this test has %cc initially equal to zero #
+# movep.w %d0,(0x0,%a0) #
+# - this test has %cc initially equal to zero #
#####################################################
movp_2:
addq.l &0x1,TESTCTR(%a6)
diff -puN arch/m68k/ifpsp060/src/pfpsp.S~m68k-superfluous-whitespace arch/m68k/ifpsp060/src/pfpsp.S
--- 25/arch/m68k/ifpsp060/src/pfpsp.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/ifpsp060/src/pfpsp.S Thu Apr 22 13:43:13 2004
@@ -5,10 +5,10 @@ M68060 Software Package
Production Release P1.00 -- October 10, 1994
M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved.
-
+
THE SOFTWARE is provided on an "AS IS" basis and without warranty.
To the maximum extent permitted by applicable law,
-MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
+MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
and any warranty against infringement with regard to the SOFTWARE
(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
@@ -89,7 +89,7 @@ _060FPSP_TABLE:
bra.l _fpsp_effadd
short 0x0000
- space 56
+ space 56
###############################################################
global _fpsp_done
@@ -323,33 +323,33 @@ set EXC_D2, EXC_DREGS+(2*4)
set EXC_D1, EXC_DREGS+(1*4)
set EXC_D0, EXC_DREGS+(0*4)
-set EXC_FP0, EXC_FPREGS+(0*12) # offset of saved fp0
-set EXC_FP1, EXC_FPREGS+(1*12) # offset of saved fp1
-set EXC_FP2, EXC_FPREGS+(2*12) # offset of saved fp2 (not used)
+set EXC_FP0, EXC_FPREGS+(0*12) # offset of saved fp0
+set EXC_FP1, EXC_FPREGS+(1*12) # offset of saved fp1
+set EXC_FP2, EXC_FPREGS+(2*12) # offset of saved fp2 (not used)
-set FP_SCR1, LV+80 # fp scratch 1
-set FP_SCR1_EX, FP_SCR1+0
+set FP_SCR1, LV+80 # fp scratch 1
+set FP_SCR1_EX, FP_SCR1+0
set FP_SCR1_SGN, FP_SCR1+2
-set FP_SCR1_HI, FP_SCR1+4
-set FP_SCR1_LO, FP_SCR1+8
+set FP_SCR1_HI, FP_SCR1+4
+set FP_SCR1_LO, FP_SCR1+8
-set FP_SCR0, LV+68 # fp scratch 0
-set FP_SCR0_EX, FP_SCR0+0
+set FP_SCR0, LV+68 # fp scratch 0
+set FP_SCR0_EX, FP_SCR0+0
set FP_SCR0_SGN, FP_SCR0+2
-set FP_SCR0_HI, FP_SCR0+4
-set FP_SCR0_LO, FP_SCR0+8
+set FP_SCR0_HI, FP_SCR0+4
+set FP_SCR0_LO, FP_SCR0+8
-set FP_DST, LV+56 # fp destination operand
-set FP_DST_EX, FP_DST+0
+set FP_DST, LV+56 # fp destination operand
+set FP_DST_EX, FP_DST+0
set FP_DST_SGN, FP_DST+2
-set FP_DST_HI, FP_DST+4
-set FP_DST_LO, FP_DST+8
+set FP_DST_HI, FP_DST+4
+set FP_DST_LO, FP_DST+8
-set FP_SRC, LV+44 # fp source operand
-set FP_SRC_EX, FP_SRC+0
+set FP_SRC, LV+44 # fp source operand
+set FP_SRC_EX, FP_SRC+0
set FP_SRC_SGN, FP_SRC+2
-set FP_SRC_HI, FP_SRC+4
-set FP_SRC_LO, FP_SRC+8
+set FP_SRC_HI, FP_SRC+4
+set FP_SRC_LO, FP_SRC+8
set USER_FPIAR, LV+40 # FP instr address register
@@ -373,7 +373,7 @@ set EXC_TEMP2, LV+24 # temporary spac
set EXC_TEMP, LV+16 # temporary space
set DTAG, LV+15 # destination operand type
-set STAG, LV+14 # source operand type
+set STAG, LV+14 # source operand type
set SPCOND_FLG, LV+10 # flag: special case (see below)
@@ -388,17 +388,17 @@ set EXC_OPWORD, LV+0 # saved operatio
# Helpful macros
set FTEMP, 0 # offsets within an
-set FTEMP_EX, 0 # extended precision
+set FTEMP_EX, 0 # extended precision
set FTEMP_SGN, 2 # value saved in memory.
-set FTEMP_HI, 4
-set FTEMP_LO, 8
+set FTEMP_HI, 4
+set FTEMP_LO, 8
set FTEMP_GRS, 12
set LOCAL, 0 # offsets within an
-set LOCAL_EX, 0 # extended precision
+set LOCAL_EX, 0 # extended precision
set LOCAL_SGN, 2 # value saved in memory.
-set LOCAL_HI, 4
-set LOCAL_LO, 8
+set LOCAL_HI, 4
+set LOCAL_LO, 8
set LOCAL_GRS, 12
set DST, 0 # offsets within an
@@ -488,17 +488,17 @@ set ainex_mask, 0x00000008 # accrued i
######################################
set dzinf_mask, inf_mask+dz_mask+adz_mask
set opnan_mask, nan_mask+operr_mask+aiop_mask
-set nzi_mask, 0x01ffffff #clears N, Z, and I
+set nzi_mask, 0x01ffffff #clears N, Z, and I
set unfinx_mask, unfl_mask+inex2_mask+aunfl_mask+ainex_mask
set unf2inx_mask, unfl_mask+inex2_mask+ainex_mask
set ovfinx_mask, ovfl_mask+inex2_mask+aovfl_mask+ainex_mask
set inx1a_mask, inex1_mask+ainex_mask
set inx2a_mask, inex2_mask+ainex_mask
-set snaniop_mask, nan_mask+snan_mask+aiop_mask
+set snaniop_mask, nan_mask+snan_mask+aiop_mask
set snaniop2_mask, snan_mask+aiop_mask
set naniop_mask, nan_mask+aiop_mask
set neginf_mask, neg_mask+inf_mask
-set infaiop_mask, inf_mask+aiop_mask
+set infaiop_mask, inf_mask+aiop_mask
set negz_mask, neg_mask+z_mask
set opaop_mask, operr_mask+aiop_mask
set unfl_inx_mask, unfl_mask+aunfl_mask+ainex_mask
@@ -527,8 +527,8 @@ set rp_mode, 0x3 # round-to-plus-infi
set mantissalen, 64 # length of mantissa in bits
set BYTE, 1 # len(byte) == 1 byte
-set WORD, 2 # len(word) == 2 bytes
-set LONG, 4 # len(longword) == 2 bytes
+set WORD, 2 # len(word) == 2 bytes
+set LONG, 4 # len(longword) == 2 bytes
set BSUN_VEC, 0xc0 # bsun vector offset
set INEX_VEC, 0xc4 # inexact vector offset
@@ -598,7 +598,7 @@ TWOBYPI:
# INPUT *************************************************************** #
# - The system stack contains the FP Ovfl exception stack frame #
# - The fsave frame contains the source operand #
-# #
+# #
# OUTPUT ************************************************************** #
# Overflow Exception enabled: #
# - The system stack is unchanged #
@@ -609,24 +609,24 @@ TWOBYPI:
# #
# ALGORITHM *********************************************************** #
# On the 060, if an FP overflow is present as the result of any #
-# instruction, the 060 will take an overflow exception whether the #
-# exception is enabled or disabled in the FPCR. For the disabled case, #
+# instruction, the 060 will take an overflow exception whether the #
+# exception is enabled or disabled in the FPCR. For the disabled case, #
# This handler emulates the instruction to determine what the correct #
# default result should be for the operation. This default result is #
-# then stored in either the FP regfile, data regfile, or memory. #
-# Finally, the handler exits through the "callout" _fpsp_done() #
+# then stored in either the FP regfile, data regfile, or memory. #
+# Finally, the handler exits through the "callout" _fpsp_done() #
# denoting that no exceptional conditions exist within the machine. #
-# If the exception is enabled, then this handler must create the #
+# If the exception is enabled, then this handler must create the #
# exceptional operand and plave it in the fsave state frame, and store #
-# the default result (only if the instruction is opclass 3). For #
-# exceptions enabled, this handler must exit through the "callout" #
+# the default result (only if the instruction is opclass 3). For #
+# exceptions enabled, this handler must exit through the "callout" #
# _real_ovfl() so that the operating system enabled overflow handler #
# can handle this case. #
-# Two other conditions exist. First, if overflow was disabled #
-# but the inexact exception was enabled, this handler must exit #
+# Two other conditions exist. First, if overflow was disabled #
+# but the inexact exception was enabled, this handler must exit #
# through the "callout" _real_inex() regardless of whether the result #
# was inexact. #
-# Also, in the case of an opclass three instruction where #
+# Also, in the case of an opclass three instruction where #
# overflow was disabled and the trace exception was enabled, this #
# handler must exit through the "callout" _real_trace(). #
# #
@@ -641,9 +641,9 @@ _fpsp_ovfl:
fsave FP_SRC(%a6) # grab the "busy" frame
- movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
+ movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs
- fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
+ fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
# the FPIAR holds the "current PC" of the faulting instruction
mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6)
@@ -667,7 +667,7 @@ _fpsp_ovfl:
bsr.l set_tag_x # tag the operand type
mov.b %d0,STAG(%a6) # maybe NORM,DENORM
-# bit five of the fp extension word separates the monadic and dyadic operations
+# bit five of the fp extension word separates the monadic and dyadic operations
# that can pass through fpsp_ovfl(). remember that fcmp, ftst, and fsincos
# will never take this exception.
btst &0x5,1+EXC_CMDREG(%a6) # is operation monadic or dyadic?
@@ -740,7 +740,7 @@ fovfl_extract:
fovfl_ovfl_on:
fmovm.x &0x40,FP_SRC(%a6) # save EXOP (fp1) to stack
- mov.w &0xe005,2+FP_SRC(%a6) # save exc status
+ mov.w &0xe005,2+FP_SRC(%a6) # save exc status
fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
@@ -756,10 +756,10 @@ fovfl_ovfl_on:
# we must jump to real_inex().
fovfl_inex_on:
- fmovm.x &0x40,FP_SRC(%a6) # save EXOP (fp1) to stack
+ fmovm.x &0x40,FP_SRC(%a6) # save EXOP (fp1) to stack
mov.b &0xc4,1+EXC_VOFF(%a6) # vector offset = 0xc4
- mov.w &0xe001,2+FP_SRC(%a6) # save exc status
+ mov.w &0xe001,2+FP_SRC(%a6) # save exc status
fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
@@ -810,7 +810,7 @@ fovfl_out:
btst &0x7,(%sp) # is trace on?
beq.l _fpsp_done # no
- fmov.l %fpiar,0x8(%sp) # "Current PC" is in FPIAR
+ fmov.l %fpiar,0x8(%sp) # "Current PC" is in FPIAR
mov.w &0x2024,0x6(%sp) # stk fmt = 0x2; voff = 0x024
bra.l _real_trace
@@ -838,7 +838,7 @@ fovfl_out:
# INPUT *************************************************************** #
# - The system stack contains the FP Unfl exception stack frame #
# - The fsave frame contains the source operand #
-# #
+# #
# OUTPUT ************************************************************** #
# Underflow Exception enabled: #
# - The system stack is unchanged #
@@ -849,24 +849,24 @@ fovfl_out:
# #
# ALGORITHM *********************************************************** #
# On the 060, if an FP underflow is present as the result of any #
-# instruction, the 060 will take an underflow exception whether the #
-# exception is enabled or disabled in the FPCR. For the disabled case, #
+# instruction, the 060 will take an underflow exception whether the #
+# exception is enabled or disabled in the FPCR. For the disabled case, #
# This handler emulates the instruction to determine what the correct #
# default result should be for the operation. This default result is #
-# then stored in either the FP regfile, data regfile, or memory. #
-# Finally, the handler exits through the "callout" _fpsp_done() #
+# then stored in either the FP regfile, data regfile, or memory. #
+# Finally, the handler exits through the "callout" _fpsp_done() #
# denoting that no exceptional conditions exist within the machine. #
-# If the exception is enabled, then this handler must create the #
+# If the exception is enabled, then this handler must create the #
# exceptional operand and plave it in the fsave state frame, and store #
-# the default result (only if the instruction is opclass 3). For #
-# exceptions enabled, this handler must exit through the "callout" #
+# the default result (only if the instruction is opclass 3). For #
+# exceptions enabled, this handler must exit through the "callout" #
# _real_unfl() so that the operating system enabled overflow handler #
# can handle this case. #
-# Two other conditions exist. First, if underflow was disabled #
-# but the inexact exception was enabled and the result was inexact, #
+# Two other conditions exist. First, if underflow was disabled #
+# but the inexact exception was enabled and the result was inexact, #
# this handler must exit through the "callout" _real_inex(). #
# was inexact. #
-# Also, in the case of an opclass three instruction where #
+# Also, in the case of an opclass three instruction where #
# underflow was disabled and the trace exception was enabled, this #
# handler must exit through the "callout" _real_trace(). #
# #
@@ -881,12 +881,12 @@ _fpsp_unfl:
fsave FP_SRC(%a6) # grab the "busy" frame
- movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
+ movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs
- fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
+ fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
# the FPIAR holds the "current PC" of the faulting instruction
- mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6)
+ mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6)
mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
bsr.l _imem_read_long # fetch the instruction words
@@ -905,13 +905,13 @@ _fpsp_unfl:
bsr.l set_tag_x # tag the operand type
mov.b %d0,STAG(%a6) # maybe NORM,DENORM
-# bit five of the fp ext word separates the monadic and dyadic operations
+# bit five of the fp ext word separates the monadic and dyadic operations
# that can pass through fpsp_unfl(). remember that fcmp, and ftst
# will never take this exception.
btst &0x5,1+EXC_CMDREG(%a6) # is op monadic or dyadic?
beq.b funfl_extract # monadic
-# now, what's left that's not dyadic is fsincos. we can distinguish it
+# now, what's left that's not dyadic is fsincos. we can distinguish it
# from all dyadics by the '0110xxx pattern
btst &0x4,1+EXC_CMDREG(%a6) # is op an fsincos?
bne.b funfl_extract # yes
@@ -962,7 +962,7 @@ funfl_extract:
# (0x00000000_80000000_00000000), then the machine will take an
# underflow exception. Since this is incorrect, we need to check
# if our emulation, after re-doing the operation, decided that
-# no underflow was called for. We do these checks only in
+# no underflow was called for. We do these checks only in
# funfl_{unfl,inex}_on() because w/ both exceptions disabled, this
# special case will simply exit gracefully with the correct result.
@@ -1002,7 +1002,7 @@ funfl_unfl_on:
funfl_unfl_on2:
fmovm.x &0x40,FP_SRC(%a6) # save EXOP (fp1) to stack
- mov.w &0xe003,2+FP_SRC(%a6) # save exc status
+ mov.w &0xe003,2+FP_SRC(%a6) # save exc status
fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
@@ -1021,7 +1021,7 @@ funfl_inex_on:
# The `060 FPU multiplier hardware is such that if the result of a
# multiply operation is the smallest possible normalized number
# (0x00000000_80000000_00000000), then the machine will take an
-# underflow exception.
+# underflow exception.
# But, whether bogus or not, if inexact is enabled AND it occurred,
# then we have to branch to real_inex.
@@ -1030,10 +1030,10 @@ funfl_inex_on:
funfl_inex_on2:
- fmovm.x &0x40,FP_SRC(%a6) # save EXOP to stack
+ fmovm.x &0x40,FP_SRC(%a6) # save EXOP to stack
mov.b &0xc4,1+EXC_VOFF(%a6) # vector offset = 0xc4
- mov.w &0xe001,2+FP_SRC(%a6) # save exc status
+ mov.w &0xe001,2+FP_SRC(%a6) # save exc status
fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0-fp1
fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
@@ -1119,7 +1119,7 @@ funfl_out:
# INPUT *************************************************************** #
# - The system stack contains the "Unimp Data Type" stk frame #
# - The fsave frame contains the ssrc op (for UNNORM/DENORM) #
-# #
+# #
# OUTPUT ************************************************************** #
# If Inexact exception (opclass 3): #
# - The system stack is changed to an Inexact exception stk frame #
@@ -1138,12 +1138,12 @@ funfl_out:
# #
# ALGORITHM *********************************************************** #
# Two main instruction types can enter here: (1) DENORM or UNNORM #
-# unimplemented data types. These can be either opclass 0,2 or 3 #
+# unimplemented data types. These can be either opclass 0,2 or 3 #
# instructions, and (2) PACKED unimplemented data format instructions #
# also of opclasses 0,2, or 3. #
# For UNNORM/DENORM opclass 0 and 2, the handler fetches the src #
# operand from the fsave state frame and the dst operand (if dyadic) #
-# from the FP register file. The instruction is then emulated by #
+# from the FP register file. The instruction is then emulated by #
# choosing an emulation routine from a table of routines indexed by #
# instruction type. Once the instruction has been emulated and result #
# saved, then we check to see if any enabled exceptions resulted from #
@@ -1165,7 +1165,7 @@ funfl_out:
# (a Trace stack frame must be created here, too). If an FP exception #
# should occur, then we must create an exception stack frame of that #
# type and jump to either _real_snan(), _real_operr(), _real_inex(), #
-# _real_unfl(), or _real_ovfl() as appropriate. PACKED opclass 3 #
+# _real_unfl(), or _real_ovfl() as appropriate. PACKED opclass 3 #
# emulation is performed in a similar manner. #
# #
#########################################################################
@@ -1177,7 +1177,7 @@ funfl_out:
# *****************
# * EA *
# pre-instruction * *
-# ***************** *****************
+# ***************** *****************
# * 0x0 * 0x0dc * * 0x3 * 0x0dc *
# ***************** *****************
# * Next * * Next *
@@ -1206,9 +1206,9 @@ _fpsp_unsupp:
fsave FP_SRC(%a6) # save fp state
- movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
+ movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs
- fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
+ fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
btst &0x5,EXC_SR(%a6) # user or supervisor mode?
bne.b fu_s
@@ -1257,7 +1257,7 @@ fu_cont:
fmov.l &0x0,%fpsr
# Opclass two w/ memory-to-fpn operation will have an incorrect extended
-# precision format if the src format was single or double and the
+# precision format if the src format was single or double and the
# source data type was an INF, NAN, DENORM, or UNNORM
lea FP_SRC(%a6),%a0 # pass ptr to input
bsr.l fix_skewed_ops
@@ -1276,7 +1276,7 @@ fu_op2:
bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg
-# bit five of the fp extension word separates the monadic and dyadic operations
+# bit five of the fp extension word separates the monadic and dyadic operations
# at this point
btst &0x5,1+EXC_CMDREG(%a6) # is operation monadic or dyadic?
beq.b fu_extract # monadic
@@ -1307,13 +1307,13 @@ fu_extract:
#
# Exceptions in order of precedence:
-# BSUN : none
+# BSUN : none
# SNAN : all dyadic ops
# OPERR : fsqrt(-NORM)
# OVFL : all except ftst,fcmp
# UNFL : all except ftst,fcmp
# DZ : fdiv
-# INEX2 : all except ftst,fcmp
+# INEX2 : all except ftst,fcmp
# INEX1 : none (packed doesn't go through here)
#
@@ -1350,16 +1350,16 @@ fu_in_ena:
#
# No exceptions occurred that were also enabled. Now:
#
-# if (OVFL && ovfl_disabled && inexact_enabled) {
+# if (OVFL && ovfl_disabled && inexact_enabled) {
# branch to _real_inex() (even if the result was exact!);
-# } else {
+# } else {
# save the result in the proper fp reg (unless the op is fcmp or ftst);
# return;
-# }
+# }
#
btst &ovfl_bit,FPSR_EXCEPT(%a6) # was overflow set?
beq.b fu_in_cont # no
-
+
fu_in_ovflchk:
btst &inex2_bit,FPCR_ENABLE(%a6) # was inexact enabled?
beq.b fu_in_cont # no
@@ -1379,7 +1379,7 @@ fu_in_ovflchk:
# } else {
# restore exc state (SNAN||OPERR||OVFL||UNFL||DZ||INEX) into the FPU;
# }
-#
+#
fu_in_exc:
subi.l &24,%d0 # fix offset to be 0-8
cmpi.b %d0,&0x6 # is exception INEX? (6)
@@ -1392,7 +1392,7 @@ fu_in_exc:
bne.w fu_in_exc_ovfl # yes
# here, we insert the correct fsave status value into the fsave frame for the
-# corresponding exception. the operand in the fsave frame should be the original
+# corresponding exception. the operand in the fsave frame should be the original
# src operand.
fu_in_exc_exit:
mov.l %d0,-(%sp) # save d0
@@ -1423,8 +1423,8 @@ fu_in_exc_ovfl:
bra.b fu_in_exc_exit
# If the input operand to this operation was opclass two and a single
-# or double precision denorm, inf, or nan, the operand needs to be
-# "corrected" in order to have the proper equivalent extended precision
+# or double precision denorm, inf, or nan, the operand needs to be
+# "corrected" in order to have the proper equivalent extended precision
# number.
global fix_skewed_ops
fix_skewed_ops:
@@ -1452,7 +1452,7 @@ fso_sgl_dnrm:
bsr.l norm # normalize mantissa
neg.w %d0 # -shft amt
addi.w &0x3f81,%d0 # adjust new exponent
- andi.w &0x8000,LOCAL_EX(%a0) # clear old exponent
+ andi.w &0x8000,LOCAL_EX(%a0) # clear old exponent
or.w %d0,LOCAL_EX(%a0) # insert new exponent
rts
@@ -1461,7 +1461,7 @@ fso_zero:
rts
fso_infnan:
- andi.b &0x7f,LOCAL_HI(%a0) # clear j-bit
+ andi.b &0x7f,LOCAL_HI(%a0) # clear j-bit
ori.w &0x7fff,LOCAL_EX(%a0) # make exponent = $7fff
rts
@@ -1484,7 +1484,7 @@ fso_dbl_dnrm:
bsr.l norm # normalize mantissa
neg.w %d0 # -shft amt
addi.w &0x3c01,%d0 # adjust new exponent
- andi.w &0x8000,LOCAL_EX(%a0) # clear old exponent
+ andi.w &0x8000,LOCAL_EX(%a0) # clear old exponent
or.w %d0,LOCAL_EX(%a0) # insert new exponent
rts
@@ -1536,13 +1536,13 @@ fu_out_cont:
bsr.l fout # call fmove out routine
# Exceptions in order of precedence:
-# BSUN : none
+# BSUN : none
# SNAN : none
# OPERR : fmove.{b,w,l} out of large UNNORM
# OVFL : fmove.{s,d}
# UNFL : fmove.{s,d,x}
# DZ : none
-# INEX2 : all
+# INEX2 : all
# INEX1 : none (packed doesn't travel through here)
# determine the highest priority exception(if any) set by the
@@ -1554,7 +1554,7 @@ fu_out_done:
mov.l EXC_A6(%a6),(%a6) # in case a6 changed
-# on extended precision opclass three instructions using pre-decrement or
+# on extended precision opclass three instructions using pre-decrement or
# post-increment addressing mode, the address register is not updated. is the
# address register was the stack pointer used from user mode, then let's update
# it here. if it was used from supervisor mode, then we have to handle this
@@ -1578,7 +1578,7 @@ fu_out_done_cont:
bra.l _fpsp_done
# is the ea mode pre-decrement of the stack pointer from supervisor mode?
-# ("fmov.x fpm,-(a7)") if so,
+# ("fmov.x fpm,-(a7)") if so,
fu_out_done_s:
cmpi.b SPCOND_FLG(%a6),&mda7_flg
bne.b fu_out_done_cont
@@ -1616,7 +1616,7 @@ fu_out_ena:
bfffo %d0{&24:&8},%d0 # find highest priority exception
bne.b fu_out_exc # there is at least one set
-# no exceptions were set.
+# no exceptions were set.
# if a disabled overflow occurred and inexact was enabled but the result
# was exact, then a branch to _real_inex() is made.
btst &ovfl_bit,FPSR_EXCEPT(%a6) # was overflow set?
@@ -1633,7 +1633,7 @@ fu_out_ovflchk:
# from FPIAR and put it in the trace stack frame then jump to _real_trace().
#
# UNSUPP FRAME TRACE FRAME
-# ***************** *****************
+# ***************** *****************
# * EA * * Current *
# * * * PC *
# ***************** *****************
@@ -1650,7 +1650,7 @@ fu_out_trace:
fmov.l %fpiar,0x8(%sp)
bra.l _real_trace
-# an exception occurred and that exception was enabled.
+# an exception occurred and that exception was enabled.
fu_out_exc:
subi.l &24,%d0 # fix offset to be 0-8
@@ -1662,15 +1662,15 @@ fu_out_exc:
swbeg &0x8
tbl_fu_out:
short tbl_fu_out - tbl_fu_out # BSUN can't happen
- short tbl_fu_out - tbl_fu_out # SNAN can't happen
+ short tbl_fu_out - tbl_fu_out # SNAN can't happen
short fu_operr - tbl_fu_out # OPERR
- short fu_ovfl - tbl_fu_out # OVFL
- short fu_unfl - tbl_fu_out # UNFL
+ short fu_ovfl - tbl_fu_out # OVFL
+ short fu_unfl - tbl_fu_out # UNFL
short tbl_fu_out - tbl_fu_out # DZ can't happen
- short fu_inex - tbl_fu_out # INEX2
+ short fu_inex - tbl_fu_out # INEX2
short tbl_fu_out - tbl_fu_out # INEX1 won't make it here
-# for snan,operr,ovfl,unfl, src op is still in FP_SRC so just
+# for snan,operr,ovfl,unfl, src op is still in FP_SRC so just
# frestore it.
fu_snan:
fmovm.x EXC_FPREGS(%a6),&0xc0 # restore fp0/fp1
@@ -1721,7 +1721,7 @@ fu_ovfl:
# underflow can happen for extended precision. extended precision opclass
# three instruction exceptions don't update the stack pointer. so, if the
# exception occurred from user mode, then simply update a7 and exit normally.
-# if the exception occurred from supervisor mode, check if
+# if the exception occurred from supervisor mode, check if
fu_unfl:
mov.l EXC_A6(%a6),(%a6) # restore a6
@@ -1730,7 +1730,7 @@ fu_unfl:
mov.l EXC_A7(%a6),%a0 # restore a7 whether we need
mov.l %a0,%usp # to or not...
-
+
fu_unfl_cont:
fmovm.x &0x40,FP_SRC(%a6) # save EXOP to the stack
@@ -1821,7 +1821,7 @@ fu_in_pack:
bfextu EXC_CMDREG(%a6){&6:&3},%d0 # dyadic; load dst reg
-# bit five of the fp extension word separates the monadic and dyadic operations
+# bit five of the fp extension word separates the monadic and dyadic operations
# at this point
btst &0x5,1+EXC_CMDREG(%a6) # is operation monadic or dyadic?
beq.b fu_extract_p # monadic
@@ -1852,13 +1852,13 @@ fu_extract_p:
#
# Exceptions in order of precedence:
-# BSUN : none
+# BSUN : none
# SNAN : all dyadic ops
# OPERR : fsqrt(-NORM)
# OVFL : all except ftst,fcmp
# UNFL : all except ftst,fcmp
# DZ : fdiv
-# INEX2 : all except ftst,fcmp
+# INEX2 : all except ftst,fcmp
# INEX1 : all
#
@@ -1928,16 +1928,16 @@ fu_in_ena_p:
#
# No exceptions occurred that were also enabled. Now:
#
-# if (OVFL && ovfl_disabled && inexact_enabled) {
+# if (OVFL && ovfl_disabled && inexact_enabled) {
# branch to _real_inex() (even if the result was exact!);
-# } else {
+# } else {
# save the result in the proper fp reg (unless the op is fcmp or ftst);
# return;
-# }
+# }
#
btst &ovfl_bit,FPSR_EXCEPT(%a6) # was overflow set?
beq.w fu_in_cont_p # no
-
+
fu_in_ovflchk_p:
btst &inex2_bit,FPCR_ENABLE(%a6) # was inexact enabled?
beq.w fu_in_cont_p # no
@@ -1957,7 +1957,7 @@ fu_in_ovflchk_p:
# } else {
# restore exc state (SNAN||OPERR||OVFL||UNFL||DZ||INEX) into the FPU;
# }
-#
+#
fu_in_exc_p:
subi.l &24,%d0 # fix offset to be 0-8
cmpi.b %d0,&0x6 # is exception INEX? (6 or 7)
@@ -1970,7 +1970,7 @@ fu_in_exc_p:
bne.w fu_in_exc_ovfl_p # yes
# here, we insert the correct fsave status value into the fsave frame for the
-# corresponding exception. the operand in the fsave frame should be the original
+# corresponding exception. the operand in the fsave frame should be the original
# src operand.
# as a reminder for future predicted pain and agony, we are passing in fsave the
# "non-skewed" operand for cases of sgl and dbl src INFs,NANs, and DENORMs.
@@ -2033,21 +2033,21 @@ fu_in_exc_exit_s_p:
bne.b fu_trace_p # yes
bra.l _fpsp_done # exit to os
-
+
#
-# The opclass two PACKED instruction that took an "Unimplemented Data Type"
-# exception was being traced. Make the "current" PC the FPIAR and put it in the
+# The opclass two PACKED instruction that took an "Unimplemented Data Type"
+# exception was being traced. Make the "current" PC the FPIAR and put it in the
# trace stack frame then jump to _real_trace().
-#
+#
# UNSUPP FRAME TRACE FRAME
# ***************** *****************
# * EA * * Current *
# * * * PC *
# ***************** *****************
-# * 0x2 * 0x0dc * * 0x2 * 0x024 *
+# * 0x2 * 0x0dc * * 0x2 * 0x024 *
# ***************** *****************
# * Next * * Next *
-# * PC * * PC *
+# * PC * * PC *
# ***************** *****************
# * SR * * SR *
# ***************** *****************
@@ -2093,13 +2093,13 @@ fu_op2_p:
bsr.l fout # call fmove out routine
# Exceptions in order of precedence:
-# BSUN : no
+# BSUN : no
# SNAN : yes
# OPERR : if ((k_factor > +17) || (dec. exp exceeds 3 digits))
# OVFL : no
# UNFL : no
# DZ : no
-# INEX2 : yes
+# INEX2 : yes
# INEX1 : no
# determine the highest priority exception(if any) set by the
@@ -2163,7 +2163,7 @@ fu_out_ena_p:
mov.l EXC_A6(%a6),(%a6) # restore a6
-# an exception occurred and that exception was enabled.
+# an exception occurred and that exception was enabled.
# the only exception possible on packed move out are INEX, OPERR, and SNAN.
fu_out_exc_p:
cmpi.b %d0,&0x1a
@@ -2190,7 +2190,7 @@ fu_snan_s_p:
movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
mov.w &0x30d8,EXC_VOFF(%a6) # vector offset = 0xd0
- mov.w &0xe006,2+FP_SRC(%a6) # set fsave status
+ mov.w &0xe006,2+FP_SRC(%a6) # set fsave status
frestore FP_SRC(%a6) # restore src operand
@@ -2230,7 +2230,7 @@ fu_operr_p_s:
movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
mov.w &0x30d0,EXC_VOFF(%a6) # vector offset = 0xd0
- mov.w &0xe004,2+FP_SRC(%a6) # set fsave status
+ mov.w &0xe004,2+FP_SRC(%a6) # set fsave status
frestore FP_SRC(%a6) # restore src operand
@@ -2269,8 +2269,8 @@ fu_inex_s_p2:
fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
- mov.w &0x30c4,EXC_VOFF(%a6) # vector offset = 0xc4
- mov.w &0xe001,2+FP_SRC(%a6) # set fsave status
+ mov.w &0x30c4,EXC_VOFF(%a6) # vector offset = 0xc4
+ mov.w &0xe001,2+FP_SRC(%a6) # set fsave status
frestore FP_SRC(%a6) # restore src operand
@@ -2311,7 +2311,7 @@ funimp_skew_sgl:
andi.w &0x7fff,%d0 # strip sign
beq.b funimp_skew_sgl_not
cmpi.w %d0,&0x3f80
- bgt.b funimp_skew_sgl_not
+ bgt.b funimp_skew_sgl_not
neg.w %d0 # make exponent negative
addi.w &0x3f81,%d0 # find amt to shift
mov.l FP_SRC_HI(%a6),%d1 # fetch DENORM hi(man)
@@ -2328,7 +2328,7 @@ funimp_skew_dbl:
andi.w &0x7fff,%d0 # strip sign
beq.b funimp_skew_dbl_not
cmpi.w %d0,&0x3c00
- bgt.b funimp_skew_dbl_not
+ bgt.b funimp_skew_dbl_not
tst.b FP_SRC_EX(%a6) # make "internal format"
smi.b 0x2+FP_SRC(%a6)
@@ -2361,7 +2361,7 @@ _mem_write2:
#########################################################################
# XDEF **************************************************************** #
# _fpsp_effadd(): 060FPSP entry point for FP "Unimplemented #
-# effective address" exception. #
+# effective address" exception. #
# #
# This handler should be the first code executed upon taking the #
# FP Unimplemented Effective Address exception in an operating #
@@ -2386,7 +2386,7 @@ _mem_write2:
# #
# INPUT *************************************************************** #
# - The system stack contains the "Unimplemented <ea>" stk frame #
-# #
+# #
# OUTPUT ************************************************************** #
# If access error: #
# - The system stack is changed to an access error stack frame #
@@ -2407,17 +2407,17 @@ _mem_write2:
# For immediate data operations, the data is read in w/ a #
# _mem_read() "callout", converted to FP binary (if packed), and used #
# as the source operand to the instruction specified by the instruction #
-# word. If no FP exception should be reported ads a result of the #
+# word. If no FP exception should be reported ads a result of the #
# emulation, then the result is stored to the destination register and #
# the handler exits through _fpsp_done(). If an enabled exc has been #
# signalled as a result of emulation, then an fsave state frame #
# corresponding to the FP exception type must be entered into the 060 #
-# FPU before exiting. In either the enabled or disabled cases, we #
+# FPU before exiting. In either the enabled or disabled cases, we #
# must also check if a Trace exception is pending, in which case, we #
# must create a Trace exception stack frame from the current exception #
# stack frame. If no Trace is pending, we simply exit through #
# _fpsp_done(). #
-# For "fmovm.x", call the routine fmovm_dynamic() which will #
+# For "fmovm.x", call the routine fmovm_dynamic() which will #
# decode and emulate the instruction. No FP exceptions can be pending #
# as a result of this operation emulation. A Trace exception can be #
# pending, though, which means the current stack frame must be changed #
@@ -2436,11 +2436,11 @@ _mem_write2:
# before the "FPU disabled" exception, but the "FPU disabled" exception #
# has higher priority, we check the disabled bit in the PCR. If set, #
# then we must create an 8 word "FPU disabled" exception stack frame #
-# from the current 4 word exception stack frame. This includes #
-# reproducing the effective address of the instruction to put on the #
+# from the current 4 word exception stack frame. This includes #
+# reproducing the effective address of the instruction to put on the #
# new stack frame. #
# #
-# In the process of all emulation work, if a _mem_read() #
+# In the process of all emulation work, if a _mem_read() #
# "callout" returns a failing result indicating an access error, then #
# we must create an access error stack frame from the current stack #
# frame. This information includes a faulting address and a fault- #
@@ -2481,18 +2481,18 @@ _fpsp_effadd:
#
# here, we will have:
-# fabs fdabs fsabs facos fmod
+# fabs fdabs fsabs facos fmod
# fadd fdadd fsadd fasin frem
-# fcmp fatan fscale
+# fcmp fatan fscale
# fdiv fddiv fsdiv fatanh fsin
# fint fcos fsincos
# fintrz fcosh fsinh
# fmove fdmove fsmove fetox ftan
-# fmul fdmul fsmul fetoxm1 ftanh
+# fmul fdmul fsmul fetoxm1 ftanh
# fneg fdneg fsneg fgetexp ftentox
# fsgldiv fgetman ftwotox
-# fsglmul flog10
-# fsqrt flog2
+# fsglmul flog10
+# fsqrt flog2
# fsub fdsub fssub flogn
# ftst flognp1
# which can all use f<op>.{x,p}
@@ -2584,8 +2584,8 @@ iea_op_spec:
# store a result. then, only fcmp will branch back and pick up a dst operand.
st STORE_FLG(%a6) # don't store a final result
btst &0x1,1+EXC_CMDREG(%a6) # is operation fcmp?
- beq.b iea_op_loaddst # yes
-
+ beq.b iea_op_loaddst # yes
+
iea_op_extract:
clr.l %d0
mov.b FPCR_MODE(%a6),%d0 # pass: rnd mode,prec
@@ -2658,7 +2658,7 @@ iea_op_ovfl:
btst &inex2_bit,FPCR_ENABLE(%a6) # is inexact enabled?
beq.b iea_op_store # no
bra.b iea_op_exc_ovfl # yes
-
+
# an enabled exception occurred. we have to insert the exception type back into
# the machine.
iea_op_exc:
@@ -2697,7 +2697,7 @@ iea_op_exit2:
fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
- frestore FP_SRC(%a6) # restore exceptional state
+ frestore FP_SRC(%a6) # restore exceptional state
unlk %a6 # unravel the frame
@@ -2705,12 +2705,12 @@ iea_op_exit2:
bne.b iea_op_trace # yes
bra.l _fpsp_done # exit to os
-
+
#
# The opclass two instruction that took an "Unimplemented Effective Address"
# exception was being traced. Make the "current" PC the FPIAR and put it in
# the trace stack frame then jump to _real_trace().
-#
+#
# UNIMP EA FRAME TRACE FRAME
# ***************** *****************
# * 0x0 * 0x0f0 * * Current *
@@ -2743,7 +2743,7 @@ iea_fmovm_data:
iea_fmovm_data_u:
mov.l %usp,%a0
- mov.l %a0,EXC_A7(%a6) # store current a7
+ mov.l %a0,EXC_A7(%a6) # store current a7
bsr.l fmovm_dynamic # do dynamic fmovm
mov.l EXC_A7(%a6),%a0 # load possibly new a7
mov.l %a0,%usp # update usp
@@ -2774,10 +2774,10 @@ iea_fmovm_data_postinc:
lea (EXC_SR,%a6,%d0),%a0
mov.l %a0,EXC_SR(%a6)
-
+
fmovm.x EXC_FP0(%a6),&0xc0 # restore fp0-fp1
fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
- movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
+ movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
unlk %a6
mov.l (%sp)+,%sp
@@ -2791,15 +2791,15 @@ iea_fmovm_data_pi_trace:
lea (EXC_SR-0x4,%a6,%d0),%a0
mov.l %a0,EXC_SR(%a6)
-
+
fmovm.x EXC_FP0(%a6),&0xc0 # restore fp0-fp1
fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
- movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
+ movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
unlk %a6
mov.l (%sp)+,%sp
bra.l _real_trace
-
+
# right now, d1 = size and d0 = the strg.
iea_fmovm_data_predec:
mov.b %d1,EXC_VOFF(%a6) # store strg
@@ -2807,7 +2807,7 @@ iea_fmovm_data_predec:
fmovm.x EXC_FP0(%a6),&0xc0 # restore fp0-fp1
fmovm.l USER_FPCR(%a6),%fpcr,%fpsr,%fpiar # restore ctrl regs
- movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
+ movm.l EXC_DREGS(%a6),&0x0303 # restore d0-d1/a0-a1
mov.l (%a6),-(%sp) # make a copy of a6
mov.l %d0,-(%sp) # save d0
@@ -2909,10 +2909,10 @@ iea_fmovm_exit:
#
# The control reg instruction that took an "Unimplemented Effective Address"
-# exception was being traced. The "Current PC" for the trace frame is the
+# exception was being traced. The "Current PC" for the trace frame is the
# PC stacked for Unimp EA. The "Next PC" is in EXC_EXTWPTR.
# After fixing the stack frame, jump to _real_trace().
-#
+#
# UNIMP EA FRAME TRACE FRAME
# ***************** *****************
# * 0x0 * 0x0f0 * * Current *
@@ -3065,7 +3065,7 @@ iea_dacc_cont:
# _fpsp_operr(): 060FPSP entry point for FP Operr exception. #
# #
# This handler should be the first code executed upon taking the #
-# FP Operand Error exception in an operating system. #
+# FP Operand Error exception in an operating system. #
# #
# XREF **************************************************************** #
# _imem_read_long() - read instruction longword #
@@ -3078,7 +3078,7 @@ iea_dacc_cont:
# INPUT *************************************************************** #
# - The system stack contains the FP Operr exception frame #
# - The fsave frame contains the source operand #
-# #
+# #
# OUTPUT ************************************************************** #
# No access error: #
# - The system stack is unchanged #
@@ -3087,16 +3087,16 @@ iea_dacc_cont:
# ALGORITHM *********************************************************** #
# In a system where the FP Operr exception is enabled, the goal #
# is to get to the handler specified at _real_operr(). But, on the 060, #
-# for opclass zero and two instruction taking this exception, the #
+# for opclass zero and two instruction taking this exception, the #
# input operand in the fsave frame may be incorrect for some cases #
# and needs to be corrected. This handler calls fix_skewed_ops() to #
# do just this and then exits through _real_operr(). #
# For opclass 3 instructions, the 060 doesn't store the default #
# operr result out to memory or data register file as it should. #
# This code must emulate the move out before finally exiting through #
-# _real_inex(). The move out, if to memory, is performed using #
+# _real_inex(). The move out, if to memory, is performed using #
# _mem_write() "callout" routines that may return a failing result. #
-# In this special case, the handler must exit through facc_out() #
+# In this special case, the handler must exit through facc_out() #
# which creates an access error stack frame from the current operr #
# stack frame. #
# #
@@ -3109,13 +3109,13 @@ _fpsp_operr:
fsave FP_SRC(%a6) # grab the "busy" frame
- movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
+ movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs
- fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
+ fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
# the FPIAR holds the "current PC" of the faulting instruction
mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6)
-
+
mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
bsr.l _imem_read_long # fetch the instruction words
@@ -3129,7 +3129,7 @@ _fpsp_operr:
# here, we simply see if the operand in the fsave frame needs to be "unskewed".
# this would be the case for opclass two operations with a source infinity or
-# denorm operand in the sgl or dbl format. NANs also become skewed, but can't
+# denorm operand in the sgl or dbl format. NANs also become skewed, but can't
# cause an operr so we don't need to check for them here.
lea FP_SRC(%a6),%a0 # pass: ptr to src op
bsr.l fix_skewed_ops # fix src op
@@ -3200,7 +3200,7 @@ tbl_operr:
short tbl_operr - tbl_operr # dbl prec shouldn't happen
short foperr_out_b - tbl_operr # byte integer
short tbl_operr - tbl_operr # packed won't enter here
-
+
foperr_out_b:
mov.b L_SCR1(%a6),%d0 # load positive default result
cmpi.b %d1,&0x7 # is <ea> mode a data reg?
@@ -3254,7 +3254,7 @@ foperr_out_l_save_dn:
# _fpsp_snan(): 060FPSP entry point for FP SNAN exception. #
# #
# This handler should be the first code executed upon taking the #
-# FP Signalling NAN exception in an operating system. #
+# FP Signalling NAN exception in an operating system. #
# #
# XREF **************************************************************** #
# _imem_read_long() - read instruction longword #
@@ -3268,7 +3268,7 @@ foperr_out_l_save_dn:
# INPUT *************************************************************** #
# - The system stack contains the FP SNAN exception frame #
# - The fsave frame contains the source operand #
-# #
+# #
# OUTPUT ************************************************************** #
# No access error: #
# - The system stack is unchanged #
@@ -3277,16 +3277,16 @@ foperr_out_l_save_dn:
# ALGORITHM *********************************************************** #
# In a system where the FP SNAN exception is enabled, the goal #
# is to get to the handler specified at _real_snan(). But, on the 060, #
-# for opclass zero and two instructions taking this exception, the #
+# for opclass zero and two instructions taking this exception, the #
# input operand in the fsave frame may be incorrect for some cases #
# and needs to be corrected. This handler calls fix_skewed_ops() to #
# do just this and then exits through _real_snan(). #
# For opclass 3 instructions, the 060 doesn't store the default #
# SNAN result out to memory or data register file as it should. #
# This code must emulate the move out before finally exiting through #
-# _real_snan(). The move out, if to memory, is performed using #
+# _real_snan(). The move out, if to memory, is performed using #
# _mem_write() "callout" routines that may return a failing result. #
-# In this special case, the handler must exit through facc_out() #
+# In this special case, the handler must exit through facc_out() #
# which creates an access error stack frame from the current SNAN #
# stack frame. #
# For the case of an extended precision opclass 3 instruction, #
@@ -3305,13 +3305,13 @@ _fpsp_snan:
fsave FP_SRC(%a6) # grab the "busy" frame
- movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
+ movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs
- fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
+ fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
# the FPIAR holds the "current PC" of the faulting instruction
mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6)
-
+
mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
bsr.l _imem_read_long # fetch the instruction words
@@ -3339,7 +3339,7 @@ fsnan_exit:
unlk %a6
bra.l _real_snan
-
+
########################################################################
#
@@ -3349,7 +3349,7 @@ fsnan_exit:
#
# byte, word, long, and packed destination format operations can pass
# through here. since packed format operations already were handled by
-# fpsp_unsupp(), then we need to do nothing else for them here.
+# fpsp_unsupp(), then we need to do nothing else for them here.
# for byte, word, and long, we simply need to test the sign of the src
# operand and save the appropriate minimum or maximum integer value
# to the effective address as pointed to by the stacked effective address.
@@ -3370,7 +3370,7 @@ tbl_snan:
short fsnan_out_d - tbl_snan # dbl prec shouldn't happen
short fsnan_out_b - tbl_snan # byte integer
short tbl_snan - tbl_snan # packed needs no help
-
+
fsnan_out_b:
mov.b FP_SRC_HI(%a6),%d0 # load upper byte of SNAN
bset &6,%d0 # set SNAN bit
@@ -3496,7 +3496,7 @@ fsnan_out_x:
mov.l %usp,%a0 # fetch user stack pointer
mov.l %a0,EXC_A7(%a6) # save on stack for calc_ea()
mov.l (%a6),EXC_A6(%a6)
-
+
bsr.l _calc_ea_fout # find the correct ea,update An
mov.l %a0,%a1
mov.l %a0,EXC_EA(%a6) # stack correct <ea>
@@ -3545,7 +3545,7 @@ fsnan_out_x_s:
mov.l LOCAL_SIZE+FP_SCR0_LO(%sp),LOCAL_SIZE+EXC_EA(%sp)
add.l &LOCAL_SIZE-0x8,%sp
-
+
bra.l _real_snan
#########################################################################
@@ -3553,7 +3553,7 @@ fsnan_out_x_s:
# _fpsp_inex(): 060FPSP entry point for FP Inexact exception. #
# #
# This handler should be the first code executed upon taking the #
-# FP Inexact exception in an operating system. #
+# FP Inexact exception in an operating system. #
# #
# XREF **************************************************************** #
# _imem_read_long() - read instruction longword #
@@ -3570,7 +3570,7 @@ fsnan_out_x_s:
# INPUT *************************************************************** #
# - The system stack contains the FP Inexact exception frame #
# - The fsave frame contains the source operand #
-# #
+# #
# OUTPUT ************************************************************** #
# - The system stack is unchanged #
# - The fsave frame contains the adjusted src op for opclass 0,2 #
@@ -3578,10 +3578,10 @@ fsnan_out_x_s:
# ALGORITHM *********************************************************** #
# In a system where the FP Inexact exception is enabled, the goal #
# is to get to the handler specified at _real_inex(). But, on the 060, #
-# for opclass zero and two instruction taking this exception, the #
+# for opclass zero and two instruction taking this exception, the #
# hardware doesn't store the correct result to the destination FP #
-# register as did the '040 and '881/2. This handler must emulate the #
-# instruction in order to get this value and then store it to the #
+# register as did the '040 and '881/2. This handler must emulate the #
+# instruction in order to get this value and then store it to the #
# correct register before calling _real_inex(). #
# For opclass 3 instructions, the 060 doesn't store the default #
# inexact result out to memory or data register file as it should. #
@@ -3597,13 +3597,13 @@ _fpsp_inex:
fsave FP_SRC(%a6) # grab the "busy" frame
- movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
+ movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs
- fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
+ fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
# the FPIAR holds the "current PC" of the faulting instruction
mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6)
-
+
mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
bsr.l _imem_read_long # fetch the instruction words
@@ -3615,7 +3615,7 @@ _fpsp_inex:
bne.w finex_out # fmove out
-# the hardware, for "fabs" and "fneg" w/ a long source format, puts the
+# the hardware, for "fabs" and "fneg" w/ a long source format, puts the
# longword integer directly into the upper longword of the mantissa along
# w/ an exponent value of 0x401e. we convert this to extended precision here.
bfextu %d0{&19:&3},%d0 # fetch instr size
@@ -3749,7 +3749,7 @@ finex_out:
# INPUT *************************************************************** #
# - The system stack contains the FP DZ exception stack. #
# - The fsave frame contains the source operand. #
-# #
+# #
# OUTPUT ************************************************************** #
# - The system stack contains the FP DZ exception stack. #
# - The fsave frame contains the adjusted source operand. #
@@ -3760,7 +3760,7 @@ finex_out:
# exception is taken, the input operand in the fsave state frame may #
# be incorrect for some cases and need to be adjusted. So, this package #
# adjusts the operand using fix_skewed_ops() and then branches to #
-# _real_dz(). #
+# _real_dz(). #
# #
#########################################################################
@@ -3771,13 +3771,13 @@ _fpsp_dz:
fsave FP_SRC(%a6) # grab the "busy" frame
- movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
+ movm.l &0x0303,EXC_DREGS(%a6) # save d0-d1/a0-a1
fmovm.l %fpcr,%fpsr,%fpiar,USER_FPCR(%a6) # save ctrl regs
- fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
+ fmovm.x &0xc0,EXC_FPREGS(%a6) # save fp0-fp1 on stack
# the FPIAR holds the "current PC" of the faulting instruction
mov.l USER_FPIAR(%a6),EXC_EXTWPTR(%a6)
-
+
mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
bsr.l _imem_read_long # fetch the instruction words
@@ -3805,7 +3805,7 @@ fdz_exit:
#########################################################################
# XDEF **************************************************************** #
# _fpsp_fline(): 060FPSP entry point for "Line F emulator" #
-# exception when the "reduced" version of the #
+# exception when the "reduced" version of the #
# FPSP is implemented that does not emulate #
# FP unimplemented instructions. #
# #
@@ -3820,12 +3820,12 @@ fdz_exit:
# INPUT *************************************************************** #
# - The system stack contains a "Line F Emulator" exception #
# stack frame. #
-# #
+# #
# OUTPUT ************************************************************** #
# - The system stack is unchanged. #
# #
# ALGORITHM *********************************************************** #
-# When a "Line F Emulator" exception occurs in a system where #
+# When a "Line F Emulator" exception occurs in a system where #
# "FPU Unimplemented" instructions will not be emulated, the exception #
# can occur because then FPU is disabled or the instruction is to be #
# classifed as "Line F". This module determines which case exists and #
@@ -3853,21 +3853,21 @@ _fpsp_fline:
# #
# INPUT *************************************************************** #
# d0 = number of bytes to adjust <ea> by #
-# #
+# #
# OUTPUT ************************************************************** #
# None #
# #
# ALGORITHM *********************************************************** #
# "Dummy" CALCulate Effective Address: #
-# The stacked <ea> for FP unimplemented instructions and opclass #
+# The stacked <ea> for FP unimplemented instructions and opclass #
# two packed instructions is correct with the exception of... #
# #
# 1) -(An) : The register is not updated regardless of size. #
-# Also, for extended precision and packed, the #
+# Also, for extended precision and packed, the #
# stacked <ea> value is 8 bytes too big #
# 2) (An)+ : The register is not updated. #
-# 3) #<data> : The upper longword of the immediate operand is #
-# stacked b,w,l and s sizes are completely stacked. #
+# 3) #<data> : The upper longword of the immediate operand is #
+# stacked b,w,l and s sizes are completely stacked. #
# d,x, and p are not. #
# #
#########################################################################
@@ -3903,8 +3903,8 @@ dcea_imm:
lea ([USER_FPIAR,%a6],0x4),%a0 # no; return <ea>
rts
-# here, the <ea> is stacked correctly. however, we must update the
-# address register...
+# here, the <ea> is stacked correctly. however, we must update the
+# address register...
dcea_pi:
mov.l %a0,%d0 # pass amt to inc by
bsr.l inc_areg # inc addr register
@@ -3912,7 +3912,7 @@ dcea_pi:
mov.l EXC_EA(%a6),%a0 # stacked <ea> is correct
rts
-# the <ea> is stacked correctly for all but extended and packed which
+# the <ea> is stacked correctly for all but extended and packed which
# the <ea>s are 8 bytes too large.
# it would make no sense to have a pre-decrement to a7 in supervisor
# mode so we don't even worry about this tricky case here : )
@@ -3932,7 +3932,7 @@ dcea_pd2:
#########################################################################
# XDEF **************************************************************** #
-# _calc_ea_fout(): calculate correct stacked <ea> for extended #
+# _calc_ea_fout(): calculate correct stacked <ea> for extended #
# and packed data opclass 3 operations. #
# #
# XREF **************************************************************** #
@@ -3940,22 +3940,22 @@ dcea_pd2:
# #
# INPUT *************************************************************** #
# None #
-# #
+# #
# OUTPUT ************************************************************** #
# a0 = return correct effective address #
# #
# ALGORITHM *********************************************************** #
# For opclass 3 extended and packed data operations, the <ea> #
# stacked for the exception is incorrect for -(an) and (an)+ addressing #
-# modes. Also, while we're at it, the index register itself must get #
+# modes. Also, while we're at it, the index register itself must get #
# updated. #
-# So, for -(an), we must subtract 8 off of the stacked <ea> value #
+# So, for -(an), we must subtract 8 off of the stacked <ea> value #
# and return that value as the correct <ea> and store that value in An. #
# For (an)+, the stacked <ea> is correct but we must adjust An by +12. #
# #
#########################################################################
-# This calc_ea is currently used to retrieve the correct <ea>
+# This calc_ea is currently used to retrieve the correct <ea>
# for fmove outs of type extended and packed.
global _calc_ea_fout
_calc_ea_fout:
@@ -3976,7 +3976,7 @@ _calc_ea_fout:
# (An)+ : extended and packed fmove out
# : stacked <ea> is correct
-# : "An" not updated
+# : "An" not updated
ceaf_pi:
mov.w (tbl_ceaf_pi.b,%pc,%d1.w*2),%d1
mov.l EXC_EA(%a6),%a0
@@ -4077,11 +4077,11 @@ ceaf_pd7:
swbeg &109
tbl_unsupp:
- long fin - tbl_unsupp # 00: fmove
- long fint - tbl_unsupp # 01: fint
- long tbl_unsupp - tbl_unsupp # 02: fsinh
- long fintrz - tbl_unsupp # 03: fintrz
- long fsqrt - tbl_unsupp # 04: fsqrt
+ long fin - tbl_unsupp # 00: fmove
+ long fint - tbl_unsupp # 01: fint
+ long tbl_unsupp - tbl_unsupp # 02: fsinh
+ long fintrz - tbl_unsupp # 03: fintrz
+ long fsqrt - tbl_unsupp # 04: fsqrt
long tbl_unsupp - tbl_unsupp
long tbl_unsupp - tbl_unsupp # 06: flognp1
long tbl_unsupp - tbl_unsupp
@@ -4101,23 +4101,23 @@ tbl_unsupp:
long tbl_unsupp - tbl_unsupp # 15: flog10
long tbl_unsupp - tbl_unsupp # 16: flog2
long tbl_unsupp - tbl_unsupp
- long fabs - tbl_unsupp # 18: fabs
+ long fabs - tbl_unsupp # 18: fabs
long tbl_unsupp - tbl_unsupp # 19: fcosh
- long fneg - tbl_unsupp # 1a: fneg
+ long fneg - tbl_unsupp # 1a: fneg
long tbl_unsupp - tbl_unsupp
long tbl_unsupp - tbl_unsupp # 1c: facos
long tbl_unsupp - tbl_unsupp # 1d: fcos
long tbl_unsupp - tbl_unsupp # 1e: fgetexp
long tbl_unsupp - tbl_unsupp # 1f: fgetman
- long fdiv - tbl_unsupp # 20: fdiv
+ long fdiv - tbl_unsupp # 20: fdiv
long tbl_unsupp - tbl_unsupp # 21: fmod
- long fadd - tbl_unsupp # 22: fadd
- long fmul - tbl_unsupp # 23: fmul
- long fsgldiv - tbl_unsupp # 24: fsgldiv
+ long fadd - tbl_unsupp # 22: fadd
+ long fmul - tbl_unsupp # 23: fmul
+ long fsgldiv - tbl_unsupp # 24: fsgldiv
long tbl_unsupp - tbl_unsupp # 25: frem
long tbl_unsupp - tbl_unsupp # 26: fscale
- long fsglmul - tbl_unsupp # 27: fsglmul
- long fsub - tbl_unsupp # 28: fsub
+ long fsglmul - tbl_unsupp # 27: fsglmul
+ long fsub - tbl_unsupp # 28: fsub
long tbl_unsupp - tbl_unsupp
long tbl_unsupp - tbl_unsupp
long tbl_unsupp - tbl_unsupp
@@ -4133,20 +4133,20 @@ tbl_unsupp:
long tbl_unsupp - tbl_unsupp # 35: fsincos
long tbl_unsupp - tbl_unsupp # 36: fsincos
long tbl_unsupp - tbl_unsupp # 37: fsincos
- long fcmp - tbl_unsupp # 38: fcmp
+ long fcmp - tbl_unsupp # 38: fcmp
long tbl_unsupp - tbl_unsupp
- long ftst - tbl_unsupp # 3a: ftst
+ long ftst - tbl_unsupp # 3a: ftst
long tbl_unsupp - tbl_unsupp
long tbl_unsupp - tbl_unsupp
long tbl_unsupp - tbl_unsupp
long tbl_unsupp - tbl_unsupp
long tbl_unsupp - tbl_unsupp
- long fsin - tbl_unsupp # 40: fsmove
- long fssqrt - tbl_unsupp # 41: fssqrt
+ long fsin - tbl_unsupp # 40: fsmove
+ long fssqrt - tbl_unsupp # 41: fssqrt
long tbl_unsupp - tbl_unsupp
long tbl_unsupp - tbl_unsupp
long fdin - tbl_unsupp # 44: fdmove
- long fdsqrt - tbl_unsupp # 45: fdsqrt
+ long fdsqrt - tbl_unsupp # 45: fdsqrt
long tbl_unsupp - tbl_unsupp
long tbl_unsupp - tbl_unsupp
long tbl_unsupp - tbl_unsupp
@@ -4165,27 +4165,27 @@ tbl_unsupp:
long tbl_unsupp - tbl_unsupp
long tbl_unsupp - tbl_unsupp
long tbl_unsupp - tbl_unsupp
- long fsabs - tbl_unsupp # 58: fsabs
+ long fsabs - tbl_unsupp # 58: fsabs
long tbl_unsupp - tbl_unsupp
- long fsneg - tbl_unsupp # 5a: fsneg
+ long fsneg - tbl_unsupp # 5a: fsneg
long tbl_unsupp - tbl_unsupp
long fdabs - tbl_unsupp # 5c: fdabs
long tbl_unsupp - tbl_unsupp
- long fdneg - tbl_unsupp # 5e: fdneg
+ long fdneg - tbl_unsupp # 5e: fdneg
long tbl_unsupp - tbl_unsupp
long fsdiv - tbl_unsupp # 60: fsdiv
long tbl_unsupp - tbl_unsupp
long fsadd - tbl_unsupp # 62: fsadd
long fsmul - tbl_unsupp # 63: fsmul
- long fddiv - tbl_unsupp # 64: fddiv
+ long fddiv - tbl_unsupp # 64: fddiv
long tbl_unsupp - tbl_unsupp
long fdadd - tbl_unsupp # 66: fdadd
- long fdmul - tbl_unsupp # 67: fdmul
+ long fdmul - tbl_unsupp # 67: fdmul
long fssub - tbl_unsupp # 68: fssub
long tbl_unsupp - tbl_unsupp
long tbl_unsupp - tbl_unsupp
long tbl_unsupp - tbl_unsupp
- long fdsub - tbl_unsupp # 6c: fdsub
+ long fdsub - tbl_unsupp # 6c: fdsub
#################################################
# Add this here so non-fp modules can compile.
@@ -4208,7 +4208,7 @@ smovcr:
# #
# INPUT *************************************************************** #
# None #
-# #
+# #
# OUTPUT ************************************************************** #
# If instr is "fmovm Dn,-(A7)" from supervisor mode, #
# d0 = size of dump #
@@ -4230,25 +4230,25 @@ smovcr:
# The data register is determined and its value loaded to get the #
# string of FP registers affected. This value is used as an index into #
# a lookup table such that we can determine the number of bytes #
-# involved. #
+# involved. #
# If the instruction is "fmovm.x <ea>,Dn", a _mem_read() is used #
# to read in all FP values. Again, _mem_read() may fail and require a #
-# special exit. #
+# special exit. #
# If the instruction is "fmovm.x DN,<ea>", a _mem_write() is used #
# to write all FP values. _mem_write() may also fail. #
-# If the instruction is "fmovm.x DN,-(a7)" from supervisor mode, #
+# If the instruction is "fmovm.x DN,-(a7)" from supervisor mode, #
# then we return the size of the dump and the string to the caller #
# so that the move can occur outside of this routine. This special #
# case is required so that moves to the system stack are handled #
# correctly. #
# #
# DYNAMIC: #
-# fmovm.x dn, <ea> #
-# fmovm.x <ea>, dn #
+# fmovm.x dn, <ea> #
+# fmovm.x <ea>, dn #
# #
# <WORD 1> <WORD2> #
# 1111 0010 00 |<ea>| 11@& 1000 0$$$ 0000 #
-# #
+# #
# & = (0): predecrement addressing mode #
# (1): postincrement or control addressing mode #
# @ = (0): move listed regs from memory to the FPU #
@@ -4517,12 +4517,12 @@ tbl_fmovm_size:
byte 0x24,0x30,0x30,0x3c,0x30,0x3c,0x3c,0x48
byte 0x30,0x3c,0x3c,0x48,0x3c,0x48,0x48,0x54
byte 0x30,0x3c,0x3c,0x48,0x3c,0x48,0x48,0x54
- byte 0x3c,0x48,0x48,0x54,0x48,0x54,0x54,0x60
+ byte 0x3c,0x48,0x48,0x54,0x48,0x54,0x54,0x60
#
# table to convert a pre-decrement bit string into a post-increment
# or control bit string.
-# ex: 0x00 ==> 0x00
+# ex: 0x00 ==> 0x00
# 0x01 ==> 0x80
# 0x02 ==> 0x40
# .
@@ -4604,59 +4604,59 @@ tbl_fea_mode:
short tbl_fea_mode - tbl_fea_mode
short tbl_fea_mode - tbl_fea_mode
- short faddr_ind_a0 - tbl_fea_mode
- short faddr_ind_a1 - tbl_fea_mode
- short faddr_ind_a2 - tbl_fea_mode
- short faddr_ind_a3 - tbl_fea_mode
- short faddr_ind_a4 - tbl_fea_mode
- short faddr_ind_a5 - tbl_fea_mode
- short faddr_ind_a6 - tbl_fea_mode
- short faddr_ind_a7 - tbl_fea_mode
-
- short faddr_ind_p_a0 - tbl_fea_mode
- short faddr_ind_p_a1 - tbl_fea_mode
- short faddr_ind_p_a2 - tbl_fea_mode
- short faddr_ind_p_a3 - tbl_fea_mode
- short faddr_ind_p_a4 - tbl_fea_mode
- short faddr_ind_p_a5 - tbl_fea_mode
- short faddr_ind_p_a6 - tbl_fea_mode
- short faddr_ind_p_a7 - tbl_fea_mode
-
- short faddr_ind_m_a0 - tbl_fea_mode
- short faddr_ind_m_a1 - tbl_fea_mode
- short faddr_ind_m_a2 - tbl_fea_mode
- short faddr_ind_m_a3 - tbl_fea_mode
- short faddr_ind_m_a4 - tbl_fea_mode
- short faddr_ind_m_a5 - tbl_fea_mode
- short faddr_ind_m_a6 - tbl_fea_mode
- short faddr_ind_m_a7 - tbl_fea_mode
-
- short faddr_ind_disp_a0 - tbl_fea_mode
- short faddr_ind_disp_a1 - tbl_fea_mode
- short faddr_ind_disp_a2 - tbl_fea_mode
- short faddr_ind_disp_a3 - tbl_fea_mode
- short faddr_ind_disp_a4 - tbl_fea_mode
- short faddr_ind_disp_a5 - tbl_fea_mode
- short faddr_ind_disp_a6 - tbl_fea_mode
+ short faddr_ind_a0 - tbl_fea_mode
+ short faddr_ind_a1 - tbl_fea_mode
+ short faddr_ind_a2 - tbl_fea_mode
+ short faddr_ind_a3 - tbl_fea_mode
+ short faddr_ind_a4 - tbl_fea_mode
+ short faddr_ind_a5 - tbl_fea_mode
+ short faddr_ind_a6 - tbl_fea_mode
+ short faddr_ind_a7 - tbl_fea_mode
+
+ short faddr_ind_p_a0 - tbl_fea_mode
+ short faddr_ind_p_a1 - tbl_fea_mode
+ short faddr_ind_p_a2 - tbl_fea_mode
+ short faddr_ind_p_a3 - tbl_fea_mode
+ short faddr_ind_p_a4 - tbl_fea_mode
+ short faddr_ind_p_a5 - tbl_fea_mode
+ short faddr_ind_p_a6 - tbl_fea_mode
+ short faddr_ind_p_a7 - tbl_fea_mode
+
+ short faddr_ind_m_a0 - tbl_fea_mode
+ short faddr_ind_m_a1 - tbl_fea_mode
+ short faddr_ind_m_a2 - tbl_fea_mode
+ short faddr_ind_m_a3 - tbl_fea_mode
+ short faddr_ind_m_a4 - tbl_fea_mode
+ short faddr_ind_m_a5 - tbl_fea_mode
+ short faddr_ind_m_a6 - tbl_fea_mode
+ short faddr_ind_m_a7 - tbl_fea_mode
+
+ short faddr_ind_disp_a0 - tbl_fea_mode
+ short faddr_ind_disp_a1 - tbl_fea_mode
+ short faddr_ind_disp_a2 - tbl_fea_mode
+ short faddr_ind_disp_a3 - tbl_fea_mode
+ short faddr_ind_disp_a4 - tbl_fea_mode
+ short faddr_ind_disp_a5 - tbl_fea_mode
+ short faddr_ind_disp_a6 - tbl_fea_mode
short faddr_ind_disp_a7 - tbl_fea_mode
- short faddr_ind_ext - tbl_fea_mode
- short faddr_ind_ext - tbl_fea_mode
- short faddr_ind_ext - tbl_fea_mode
- short faddr_ind_ext - tbl_fea_mode
- short faddr_ind_ext - tbl_fea_mode
- short faddr_ind_ext - tbl_fea_mode
- short faddr_ind_ext - tbl_fea_mode
- short faddr_ind_ext - tbl_fea_mode
-
- short fabs_short - tbl_fea_mode
- short fabs_long - tbl_fea_mode
- short fpc_ind - tbl_fea_mode
- short fpc_ind_ext - tbl_fea_mode
- short tbl_fea_mode - tbl_fea_mode
- short tbl_fea_mode - tbl_fea_mode
- short tbl_fea_mode - tbl_fea_mode
- short tbl_fea_mode - tbl_fea_mode
+ short faddr_ind_ext - tbl_fea_mode
+ short faddr_ind_ext - tbl_fea_mode
+ short faddr_ind_ext - tbl_fea_mode
+ short faddr_ind_ext - tbl_fea_mode
+ short faddr_ind_ext - tbl_fea_mode
+ short faddr_ind_ext - tbl_fea_mode
+ short faddr_ind_ext - tbl_fea_mode
+ short faddr_ind_ext - tbl_fea_mode
+
+ short fabs_short - tbl_fea_mode
+ short fabs_long - tbl_fea_mode
+ short fpc_ind - tbl_fea_mode
+ short fpc_ind_ext - tbl_fea_mode
+ short tbl_fea_mode - tbl_fea_mode
+ short tbl_fea_mode - tbl_fea_mode
+ short tbl_fea_mode - tbl_fea_mode
+ short tbl_fea_mode - tbl_fea_mode
###################################
# Address register indirect: (An) #
@@ -4952,7 +4952,7 @@ faddr_ind_ext:
btst &0x8,%d0
bne.w fcalc_mem_ind
-
+
mov.l %d0,L_SCR1(%a6) # hold opword
mov.l %d0,%d1
@@ -5048,7 +5048,7 @@ fpc_ind_ext:
btst &0x8,%d0 # is disp only 8 bits?
bne.w fcalc_mem_ind # calc memory indirect
-
+
mov.l %d0,L_SCR1(%a6) # store opword
mov.l %d0,%d1 # make extword copy
@@ -5125,7 +5125,7 @@ fno_base_sup:
bfextu %d5{&26:&2},%d0 # get bd size
# beq.l fmovm_error # if (size == 0) it's reserved
- cmpi.b %d0,&0x2
+ cmpi.b %d0,&0x2
blt.b fno_bd
beq.b fget_word_bd
@@ -5147,7 +5147,7 @@ fget_word_bd:
bne.l fcea_iacc # yes
ext.l %d0 # sign extend bd
-
+
fchk_ind:
add.l %d0,%d3 # base += bd
@@ -5156,10 +5156,10 @@ fno_bd:
bfextu %d5{&30:&2},%d0 # is od suppressed?
beq.w faii_bd
- cmpi.b %d0,&0x2
+ cmpi.b %d0,&0x2
blt.b fnull_od
beq.b fword_od
-
+
mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
addq.l &0x4,EXC_EXTWPTR(%a6) # incr instruction ptr
bsr.l _imem_read_long
@@ -5167,7 +5167,7 @@ fno_bd:
tst.l %d1 # did ifetch fail?
bne.l fcea_iacc # yes
- bra.b fadd_them
+ bra.b fadd_them
fword_od:
mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
@@ -5220,7 +5220,7 @@ fdone_ea:
rts
#########################################################
-fcea_err:
+fcea_err:
mov.l %d3,%a0
movm.l (%sp)+,&0x003c # restore d2-d5
@@ -5230,7 +5230,7 @@ fcea_err:
fcea_iacc:
movm.l (%sp)+,&0x003c # restore d2-d5
bra.l iea_iacc
-
+
fmovm_out_err:
bsr.l restore
mov.w &0x00e1,%d0
@@ -5246,7 +5246,7 @@ fmovm_err:
#########################################################################
# XDEF **************************************************************** #
-# fmovm_ctrl(): emulate fmovm.l of control registers instr #
+# fmovm_ctrl(): emulate fmovm.l of control registers instr #
# #
# XREF **************************************************************** #
# _imem_read_long() - read longword from memory #
@@ -5254,7 +5254,7 @@ fmovm_err:
# #
# INPUT *************************************************************** #
# None #
-# #
+# #
# OUTPUT ************************************************************** #
# If _imem_read_long() doesn't fail: #
# USER_FPCR(a6) = new FPCR value #
@@ -5262,14 +5262,14 @@ fmovm_err:
# USER_FPIAR(a6) = new FPIAR value #
# #
# ALGORITHM *********************************************************** #
-# Decode the instruction type by looking at the extension word #
+# Decode the instruction type by looking at the extension word #
# in order to see how many control registers to fetch from memory. #
# Fetch them using _imem_read_long(). If this fetch fails, exit through #
# the special access error exit handler iea_iacc(). #
# #
# Instruction word decoding: #
# #
-# fmovem.l #<data>, {FPIAR&|FPCR&|FPSR} #
+# fmovem.l #<data>, {FPIAR&|FPCR&|FPSR} #
# #
# WORD1 WORD2 #
# 1111 0010 00 111100 100$ $$00 0000 0000 #
@@ -5290,7 +5290,7 @@ fmovm_ctrl:
beq.w fctrl_in_6 # yes
cmpi.b %d0,&0x94 # fpcr & fpiar ?
beq.b fctrl_in_5 # yes
-
+
# fmovem.l #<data>, fpsr/fpiar
fctrl_in_3:
mov.l EXC_EXTWPTR(%a6),%a0 # fetch instruction addr
@@ -5392,14 +5392,14 @@ fctrl_in_7:
# INPUT *************************************************************** #
# FP_SRC(a6) = fp op1(src) #
# FP_DST(a6) = fp op2(dst) #
-# #
+# #
# OUTPUT ************************************************************** #
# FP_SRC(a6) = fp op1 scaled(src) #
# FP_DST(a6) = fp op2 scaled(dst) #
# d0 = scale amount #
# #
# ALGORITHM *********************************************************** #
-# If the DST exponent is > the SRC exponent, set the DST exponent #
+# If the DST exponent is > the SRC exponent, set the DST exponent #
# equal to 0x3fff and scale the SRC exponent by the value that the #
# DST exponent was scaled by. If the SRC exponent is greater or equal, #
# do the opposite. Return this scale factor in d0. #
@@ -5462,7 +5462,7 @@ quick_scale12:
andi.w &0x8000,FP_SCR0_EX(%a6) # zero src exponent
bset &0x0,1+FP_SCR0_EX(%a6) # set exp = 1
- mov.l (%sp)+,%d0 # return SCALE factor
+ mov.l (%sp)+,%d0 # return SCALE factor
rts
# src exp is >= dst exp; scale src to exp = 0x3fff
@@ -5498,7 +5498,7 @@ quick_scale22:
andi.w &0x8000,FP_SCR1_EX(%a6) # zero dst exponent
bset &0x0,1+FP_SCR1_EX(%a6) # set exp = 1
- mov.l (%sp)+,%d0 # return SCALE factor
+ mov.l (%sp)+,%d0 # return SCALE factor
rts
##########################################################################
@@ -5513,14 +5513,14 @@ quick_scale22:
# #
# INPUT *************************************************************** #
# FP_SCR0(a6) = extended precision operand to be scaled #
-# #
+# #
# OUTPUT ************************************************************** #
# FP_SCR0(a6) = scaled extended precision operand #
# d0 = scale value #
# #
# ALGORITHM *********************************************************** #
-# Set the exponent of the input operand to 0x3fff. Save the value #
-# of the difference between the original and new exponent. Then, #
+# Set the exponent of the input operand to 0x3fff. Save the value #
+# of the difference between the original and new exponent. Then, #
# normalize the operand if it was a DENORM. Add this normalization #
# value to the previous value. Return the result. #
# #
@@ -5566,17 +5566,17 @@ stzs_denorm:
# #
# INPUT *************************************************************** #
# FP_SCR0(a6) = extended precision operand to be scaled #
-# #
+# #
# OUTPUT ************************************************************** #
# FP_SCR0(a6) = scaled extended precision operand #
# d0 = scale value #
# #
# ALGORITHM *********************************************************** #
# If the input operand is a DENORM, normalize it. #
-# If the exponent of the input operand is even, set the exponent #
-# to 0x3ffe and return a scale factor of "(exp-0x3ffe)/2". If the #
+# If the exponent of the input operand is even, set the exponent #
+# to 0x3ffe and return a scale factor of "(exp-0x3ffe)/2". If the #
# exponent of the input operand is off, set the exponent to ox3fff and #
-# return a scale factor of "(exp-0x3fff)/2". #
+# return a scale factor of "(exp-0x3fff)/2". #
# #
#########################################################################
@@ -5640,14 +5640,14 @@ ss_denorm_even:
# #
# INPUT *************************************************************** #
# FP_SCR1(a6) = extended precision operand to be scaled #
-# #
+# #
# OUTPUT ************************************************************** #
# FP_SCR1(a6) = scaled extended precision operand #
# d0 = scale value #
# #
# ALGORITHM *********************************************************** #
-# Set the exponent of the input operand to 0x3fff. Save the value #
-# of the difference between the original and new exponent. Then, #
+# Set the exponent of the input operand to 0x3fff. Save the value #
+# of the difference between the original and new exponent. Then, #
# normalize the operand if it was a DENORM. Add this normalization #
# value to the previous value. Return the result. #
# #
@@ -5695,21 +5695,21 @@ stzd_denorm:
# INPUT *************************************************************** #
# FP_SRC(a6) = pointer to extended precision src operand #
# FP_DST(a6) = pointer to extended precision dst operand #
-# #
+# #
# OUTPUT ************************************************************** #
# fp0 = default result #
# #
# ALGORITHM *********************************************************** #
-# If either operand (but not both operands) of an operation is a #
+# If either operand (but not both operands) of an operation is a #
# nonsignalling NAN, then that NAN is returned as the result. If both #
-# operands are nonsignalling NANs, then the destination operand #
+# operands are nonsignalling NANs, then the destination operand #
# nonsignalling NAN is returned as the result. #
-# If either operand to an operation is a signalling NAN (SNAN), #
+# If either operand to an operation is a signalling NAN (SNAN), #
# then, the SNAN bit is set in the FPSR EXC byte. If the SNAN trap #
-# enable bit is set in the FPCR, then the trap is taken and the #
+# enable bit is set in the FPCR, then the trap is taken and the #
# destination is not modified. If the SNAN trap enable bit is not set, #
-# then the SNAN is converted to a nonsignalling NAN (by setting the #
-# SNAN bit in the operand to one), and the operation continues as #
+# then the SNAN is converted to a nonsignalling NAN (by setting the #
+# SNAN bit in the operand to one), and the operation continues as #
# described in the preceding paragraph, for nonsignalling NANs. #
# Make sure the appropriate FPSR bits are set before exiting. #
# #
@@ -5748,7 +5748,7 @@ dst_qnan2:
lea FP_DST(%a6), %a0
cmp.b STAG(%a6), &SNAN
bne nan_done
- or.l &aiop_mask+snan_mask, USER_FPSR(%a6)
+ or.l &aiop_mask+snan_mask, USER_FPSR(%a6)
nan_done:
or.l &nan_mask, USER_FPSR(%a6)
nan_comp:
@@ -5761,14 +5761,14 @@ nan_not_neg:
#########################################################################
# XDEF **************************************************************** #
-# res_operr(): return default result during operand error #
+# res_operr(): return default result during operand error #
# #
# XREF **************************************************************** #
# None #
# #
# INPUT *************************************************************** #
# None #
-# #
+# #
# OUTPUT ************************************************************** #
# fp0 = default operand error result #
# #
@@ -5776,8 +5776,8 @@ nan_not_neg:
# An nonsignalling NAN is returned as the default result when #
# an operand error occurs for the following cases: #
# #
-# Multiply: (Infinity x Zero) #
-# Divide : (Zero / Zero) || (Infinity / Infinity) #
+# Multiply: (Infinity x Zero) #
+# Divide : (Zero / Zero) || (Infinity / Infinity) #
# #
#########################################################################
@@ -5787,12 +5787,12 @@ res_operr:
fmovm.x nan_return(%pc), &0x80
rts
-nan_return:
+nan_return:
long 0x7fff0000, 0xffffffff, 0xffffffff
#########################################################################
# XDEF **************************************************************** #
-# _denorm(): denormalize an intermediate result #
+# _denorm(): denormalize an intermediate result #
# #
# XREF **************************************************************** #
# None #
@@ -5800,7 +5800,7 @@ nan_return:
# INPUT *************************************************************** #
# a0 = points to the operand to be denormalized #
# (in the internal extended format) #
-# #
+# #
# d0 = rounding precision #
# #
# OUTPUT ************************************************************** #
@@ -5810,10 +5810,10 @@ nan_return:
# d0 = guard,round,sticky #
# #
# ALGORITHM *********************************************************** #
-# According to the exponent underflow threshold for the given #
+# According to the exponent underflow threshold for the given #
# precision, shift the mantissa bits to the right in order raise the #
-# exponent of the operand to the threshold value. While shifting the #
-# mantissa bits right, maintain the value of the guard, round, and #
+# exponent of the operand to the threshold value. While shifting the #
+# mantissa bits right, maintain the value of the guard, round, and #
# sticky bits. #
# other notes: #
# (1) _denorm() is called by the underflow routines #
@@ -5833,7 +5833,7 @@ tbl_thresh:
_denorm:
#
# Load the exponent threshold for the precision selected and check
-# to see if (threshold - exponent) is > 65 in which case we can
+# to see if (threshold - exponent) is > 65 in which case we can
# simply calculate the sticky bit and zero the mantissa. otherwise
# we have to call the denormalization routine.
#
@@ -5872,7 +5872,7 @@ denorm_set_stky:
# %d0{31:29} : initial guard,round,sticky #
# %d1{15:0} : denormalization threshold #
# OUTPUT: #
-# %a0 : points to the denormalized operand #
+# %a0 : points to the denormalized operand #
# %d0{31:29} : final guard,round,sticky #
# #
@@ -5892,7 +5892,7 @@ dnrm_lp:
#
# check to see how much less than the underflow threshold the operand
-# exponent is.
+# exponent is.
#
mov.l %d1, %d0 # copy the denorm threshold
sub.w FTEMP_EX(%a0), %d1 # d1 = threshold - uns exponent
@@ -5907,7 +5907,7 @@ dnrm_lp:
# No normalization necessary
#
dnrm_no_lp:
- mov.l GRS(%a6), %d0 # restore original g,r,s
+ mov.l GRS(%a6), %d0 # restore original g,r,s
rts
#
@@ -5917,7 +5917,7 @@ dnrm_no_lp:
# %d1 = "n" = amt to shift
#
# ---------------------------------------------------------
-# | FTEMP_HI | FTEMP_LO |grs000.........000|
+# | FTEMP_HI | FTEMP_LO |grs000.........000|
# ---------------------------------------------------------
# <-(32 - n)-><-(n)-><-(32 - n)-><-(n)-><-(32 - n)-><-(n)->
# \ \ \ \
@@ -5928,7 +5928,7 @@ dnrm_no_lp:
# \ \ \ \
# \ \ \ \
# \ \ \ \
-# <-(n)-><-(32 - n)-><------(32)-------><------(32)------->
+# <-(n)-><-(32 - n)-><------(32)-------><------(32)------->
# ---------------------------------------------------------
# |0.....0| NEW_HI | NEW_FTEMP_LO |grs |
# ---------------------------------------------------------
@@ -5969,17 +5969,17 @@ case1_sticky_clear:
# %d1 = "n" = amt to shift
#
# ---------------------------------------------------------
-# | FTEMP_HI | FTEMP_LO |grs000.........000|
+# | FTEMP_HI | FTEMP_LO |grs000.........000|
# ---------------------------------------------------------
# <-(32 - n)-><-(n)-><-(32 - n)-><-(n)-><-(32 - n)-><-(n)->
# \ \ \
# \ \ \
# \ \ -------------------
# \ -------------------- \
-# ------------------- \ \
-# \ \ \
-# \ \ \
-# \ \ \
+# ------------------- \ \
+# \ \ \
+# \ \ \
+# \ \ \
# <-------(32)------><-(n)-><-(32 - n)-><------(32)------->
# ---------------------------------------------------------
# |0...............0|0....0| NEW_LO |grs |
@@ -6050,17 +6050,17 @@ case_3:
# case (d1 == 64)
#
# ---------------------------------------------------------
-# | FTEMP_HI | FTEMP_LO |grs000.........000|
+# | FTEMP_HI | FTEMP_LO |grs000.........000|
# ---------------------------------------------------------
# <-------(32)------>
-# \ \
-# \ \
-# \ \
-# \ ------------------------------
+# \ \
+# \ \
+# \ \
+# \ ------------------------------
# ------------------------------- \
-# \ \
-# \ \
-# \ \
+# \ \
+# \ \
+# \ \
# <-------(32)------>
# ---------------------------------------------------------
# |0...............0|0................0|grs |
@@ -6078,17 +6078,17 @@ case3_64:
# case (d1 == 65)
#
# ---------------------------------------------------------
-# | FTEMP_HI | FTEMP_LO |grs000.........000|
+# | FTEMP_HI | FTEMP_LO |grs000.........000|
# ---------------------------------------------------------
# <-------(32)------>
-# \ \
-# \ \
-# \ \
-# \ ------------------------------
+# \ \
+# \ \
+# \ \
+# \ ------------------------------
# -------------------------------- \
-# \ \
-# \ \
-# \ \
+# \ \
+# \ \
+# \ \
# <-------(31)----->
# ---------------------------------------------------------
# |0...............0|0................0|0rs |
@@ -6136,7 +6136,7 @@ case3_set_sticky:
# None #
# #
# INPUT *************************************************************** #
-# a0 = ptr to input operand in internal extended format #
+# a0 = ptr to input operand in internal extended format #
# d1(hi) = contains rounding precision: #
# ext = $0000xxxx #
# sgl = $0004xxxx #
@@ -6167,7 +6167,7 @@ _round:
#
# ext_grs() looks at the rounding precision and sets the appropriate
# G,R,S bits.
-# If (G,R,S == 0) then result is exact and round is done, else set
+# If (G,R,S == 0) then result is exact and round is done, else set
# the inex flag in status reg and continue.
#
bsr.l ext_grs # extract G,R,S
@@ -6213,7 +6213,7 @@ rnd_plus:
# If sign of fp number = 1 (negative), then add 1 to l. #
#################################################################
rnd_mnus:
- tst.b FTEMP_SGN(%a0) # check for sign
+ tst.b FTEMP_SGN(%a0) # check for sign
bpl.w truncate # if negative then truncate
mov.l &0xffffffff, %d0 # force g,r,s to be all f's
@@ -6324,7 +6324,7 @@ truncate:
#
# INPUT
# d0 = extended precision g,r,s (in d0{31:29})
-# d1 = {PREC,ROUND}
+# d1 = {PREC,ROUND}
# OUTPUT
# d0{31:29} = guard, round, sticky
#
@@ -6375,7 +6375,7 @@ ext_grs_sgl:
mov.l &30, %d2 # of the sgl prec. limits
lsl.l %d2, %d3 # shift g-r bits to MSB of d3
mov.l FTEMP_HI(%a0), %d2 # get word 2 for s-bit test
- and.l &0x0000003f, %d2 # s bit is the or of all other
+ and.l &0x0000003f, %d2 # s bit is the or of all other
bne.b ext_grs_st_stky # bits to the right of g-r
tst.l FTEMP_LO(%a0) # test lower mantissa
bne.b ext_grs_st_stky # if any are set, set sticky
@@ -6385,9 +6385,9 @@ ext_grs_sgl:
#
# dbl:
-# 96 64 32 11 0
+# 96 64 32 11 0
# -----------------------------------------------------
-# | EXP |XXXXXXX| | |xx |grs|
+# | EXP |XXXXXXX| | |xx |grs|
# -----------------------------------------------------
# nn\ /
# ee -------
@@ -6400,7 +6400,7 @@ ext_grs_dbl:
mov.l &30, %d2 # of the dbl prec. limits
lsl.l %d2, %d3 # shift g-r bits to the MSB of d3
mov.l FTEMP_LO(%a0), %d2 # get lower mantissa for s-bit test
- and.l &0x000001ff, %d2 # s bit is the or-ing of all
+ and.l &0x000001ff, %d2 # s bit is the or-ing of all
bne.b ext_grs_st_stky # other bits to the right of g-r
tst.l %d0 # test word original g,r,s
bne.b ext_grs_st_stky # if any are set, set sticky
@@ -6430,7 +6430,7 @@ ext_grs_end_sd:
# a0 = pointer fp extended precision operand to normalize #
# #
# OUTPUT ************************************************************** #
-# d0 = number of bit positions the mantissa was shifted #
+# d0 = number of bit positions the mantissa was shifted #
# a0 = the input operand's mantissa is normalized; the exponent #
# is unchanged. #
# #
@@ -6457,7 +6457,7 @@ norm_hi:
mov.l %d1, FTEMP_LO(%a0) # store new lo(man)
mov.l %d2, %d0 # return shift amount
-
+
mov.l (%sp)+, %d3 # restore temp regs
mov.l (%sp)+, %d2
@@ -6472,7 +6472,7 @@ norm_lo:
clr.l FTEMP_LO(%a0) # lo(man) is now zero
mov.l %d2, %d0 # return shift amount
-
+
mov.l (%sp)+, %d3 # restore temp regs
mov.l (%sp)+, %d2
@@ -6577,27 +6577,27 @@ unnorm_nrm_zero_lrg:
# whole mantissa is zero so this UNNORM is actually a zero
#
unnorm_zero:
- and.w &0x8000, FTEMP_EX(%a0) # force exponent to zero
+ and.w &0x8000, FTEMP_EX(%a0) # force exponent to zero
mov.b &ZERO, %d0 # fix optype tag
rts
#########################################################################
# XDEF **************************************************************** #
-# set_tag_x(): return the optype of the input ext fp number #
+# set_tag_x(): return the optype of the input ext fp number #
# #
# XREF **************************************************************** #
# None #
# #
# INPUT *************************************************************** #
# a0 = pointer to extended precision operand #
-# #
+# #
# OUTPUT ************************************************************** #
# d0 = value of type tag #
-# one of: NORM, INF, QNAN, SNAN, DENORM, UNNORM, ZERO #
+# one of: NORM, INF, QNAN, SNAN, DENORM, UNNORM, ZERO #
# #
# ALGORITHM *********************************************************** #
-# Simply test the exponent, j-bit, and mantissa values to #
+# Simply test the exponent, j-bit, and mantissa values to #
# determine the type of operand. #
# If it's an unnormalized zero, alter the operand and force it #
# to be a normal zero. #
@@ -6664,20 +6664,20 @@ is_snan_x:
#########################################################################
# XDEF **************************************************************** #
-# set_tag_d(): return the optype of the input dbl fp number #
+# set_tag_d(): return the optype of the input dbl fp number #
# #
# XREF **************************************************************** #
# None #
# #
# INPUT *************************************************************** #
# a0 = points to double precision operand #
-# #
+# #
# OUTPUT ************************************************************** #
# d0 = value of type tag #
-# one of: NORM, INF, QNAN, SNAN, DENORM, ZERO #
+# one of: NORM, INF, QNAN, SNAN, DENORM, ZERO #
# #
# ALGORITHM *********************************************************** #
-# Simply test the exponent, j-bit, and mantissa values to #
+# Simply test the exponent, j-bit, and mantissa values to #
# determine the type of operand. #
# #
#########################################################################
@@ -6727,20 +6727,20 @@ is_qnan_d:
#########################################################################
# XDEF **************************************************************** #
-# set_tag_s(): return the optype of the input sgl fp number #
+# set_tag_s(): return the optype of the input sgl fp number #
# #
# XREF **************************************************************** #
# None #
# #
# INPUT *************************************************************** #
# a0 = pointer to single precision operand #
-# #
+# #
# OUTPUT ************************************************************** #
# d0 = value of type tag #
-# one of: NORM, INF, QNAN, SNAN, DENORM, ZERO #
+# one of: NORM, INF, QNAN, SNAN, DENORM, ZERO #
# #
# ALGORITHM *********************************************************** #
-# Simply test the exponent, j-bit, and mantissa values to #
+# Simply test the exponent, j-bit, and mantissa values to #
# determine the type of operand. #
# #
#########################################################################
@@ -6786,15 +6786,15 @@ is_qnan_s:
#########################################################################
# XDEF **************************************************************** #
-# unf_res(): routine to produce default underflow result of a #
-# scaled extended precision number; this is used by #
+# unf_res(): routine to produce default underflow result of a #
+# scaled extended precision number; this is used by #
# fadd/fdiv/fmul/etc. emulation routines. #
-# unf_res4(): same as above but for fsglmul/fsgldiv which use #
+# unf_res4(): same as above but for fsglmul/fsgldiv which use #
# single round prec and extended prec mode. #
# #
# XREF **************************************************************** #
# _denorm() - denormalize according to scale factor #
-# _round() - round denormalized number according to rnd prec #
+# _round() - round denormalized number according to rnd prec #
# #
# INPUT *************************************************************** #
# a0 = pointer to extended precison operand #
@@ -6806,15 +6806,15 @@ is_qnan_s:
# d0.b = result FPSR_cc which caller may or may not want to save #
# #
# ALGORITHM *********************************************************** #
-# Convert the input operand to "internal format" which means the #
+# Convert the input operand to "internal format" which means the #
# exponent is extended to 16 bits and the sign is stored in the unused #
# portion of the extended precison operand. Denormalize the number #
-# according to the scale factor passed in d0. Then, round the #
+# according to the scale factor passed in d0. Then, round the #
# denormalized result. #
-# Set the FPSR_exc bits as appropriate but return the cc bits in #
+# Set the FPSR_exc bits as appropriate but return the cc bits in #
# d0 in case the caller doesn't want to save them (as is the case for #
# fmove out). #
-# unf_res4() for fsglmul/fsgldiv forces the denorm to extended #
+# unf_res4() for fsglmul/fsgldiv forces the denorm to extended #
# precision and the rounding mode to single. #
# #
#########################################################################
@@ -6952,23 +6952,23 @@ unf_res4_end:
# none #
# #
# INPUT *************************************************************** #
-# d1.b = '-1' => (-); '0' => (+) #
+# d1.b = '-1' => (-); '0' => (+) #
# ovf_res(): #
-# d0 = rnd mode/prec #
+# d0 = rnd mode/prec #
# ovf_res2(): #
-# hi(d0) = rnd prec #
+# hi(d0) = rnd prec #
# lo(d0) = rnd mode #
# #
# OUTPUT ************************************************************** #
-# a0 = points to extended precision result #
-# d0.b = condition code bits #
+# a0 = points to extended precision result #
+# d0.b = condition code bits #
# #
# ALGORITHM *********************************************************** #
# The default overflow result can be determined by the sign of #
# the result and the rounding mode/prec in effect. These bits are #
-# concatenated together to create an index into the default result #
+# concatenated together to create an index into the default result #
# table. A pointer to the correct result is returned in a0. The #
-# resulting condition codes are returned in d0 in case the caller #
+# resulting condition codes are returned in d0 in case the caller #
# doesn't want FPSR_cc altered (as is the case for fmove out). #
# #
#########################################################################
@@ -6998,7 +6998,7 @@ ovf_res2:
ovf_res_load:
mov.b (tbl_ovfl_cc.b,%pc,%d0.w*1), %d0 # fetch result ccodes
lea (tbl_ovfl_result.b,%pc,%d1.w*8), %a0 # return result ptr
-
+
rts
tbl_ovfl_cc:
@@ -7048,7 +7048,7 @@ tbl_ovfl_result:
#########################################################################
# XDEF **************************************************************** #
-# fout(): move from fp register to memory or data register #
+# fout(): move from fp register to memory or data register #
# #
# XREF **************************************************************** #
# _round() - needed to create EXOP for sgl/dbl precision #
@@ -7068,7 +7068,7 @@ tbl_ovfl_result:
# INPUT *************************************************************** #
# a0 = pointer to extended precision source operand #
# d0 = round prec,mode #
-# #
+# #
# OUTPUT ************************************************************** #
# fp0 : intermediate underflow or overflow result if #
# OVFL/UNFL occurred for a sgl or dbl operand #
@@ -7087,9 +7087,9 @@ tbl_ovfl_result:
# w/ the address index register as appropriate w/ _calc_ea_fout(). If #
# the source is a denorm and if underflow is enabled, an EXOP must be #
# created. #
-# For packed, the k-factor must be fetched from the instruction #
-# word or a data register. The <ea> must be fixed as w/ extended #
-# precision. Then, bindec() is called to create the appropriate #
+# For packed, the k-factor must be fetched from the instruction #
+# word or a data register. The <ea> must be fixed as w/ extended #
+# precision. Then, bindec() is called to create the appropriate #
# packed result. #
# If at any time an access error is flagged by one of the move- #
# to-memory routines, then a special exit must be made so that the #
@@ -7205,7 +7205,7 @@ fout_word_denorm:
ori.l &0x00800000,%d1 # make smallest sgl
fmov.s %d1,%fp0
bra.b fout_word_norm
-
+
#################################################################
# fmove.l out ###################################################
#################################################################
@@ -7279,7 +7279,7 @@ fout_ext:
mov.l &0xc,%d0 # pass: opsize is 12 bytes
# we must not yet write the extended precision data to the stack
-# in the pre-decrement case from supervisor mode or else we'll corrupt
+# in the pre-decrement case from supervisor mode or else we'll corrupt
# the stack frame. so, leave it in FP_SRC for now and deal with it later...
cmpi.b SPCOND_FLG(%a6),&mda7_flg
beq.b fout_ext_a7
@@ -7366,7 +7366,7 @@ fout_sgl_exg:
fmov.l &0x0,%fpcr # clear FPCR
fmov.l %fpsr,%d1 # save FPSR
- or.w %d1,2+USER_FPSR(%a6) # set possible inex2/ainex
+ or.w %d1,2+USER_FPSR(%a6) # set possible inex2/ainex
fout_sgl_exg_write:
mov.b 1+EXC_OPWORD(%a6),%d1 # extract dst mode
@@ -7407,7 +7407,7 @@ fout_sgl_unfl:
lea FP_SCR0(%a6),%a0
bsr.l norm # normalize the DENORM
-
+
fout_sgl_unfl_cont:
lea FP_SCR0(%a6),%a0 # pass: ptr to operand
mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode
@@ -7458,7 +7458,7 @@ fout_sgl_ovfl_cont:
# call ovf_res() w/ sgl prec and the correct rnd mode to create the default
# overflow result. DON'T save the returned ccodes from ovf_res() since
-# fmove out doesn't alter them.
+# fmove out doesn't alter them.
tst.b SRC_EX(%a0) # is operand negative?
smi %d1 # set if so
mov.l L_SCR3(%a6),%d0 # pass: sgl prec,rnd mode
@@ -7513,7 +7513,7 @@ fout_sgl_may_ovfl:
fabs.x %fp0 # need absolute value
fcmp.b %fp0,&0x2 # did exponent increase?
- fblt.w fout_sgl_exg # no; go finish NORM
+ fblt.w fout_sgl_exg # no; go finish NORM
bra.w fout_sgl_ovfl # yes; go handle overflow
################
@@ -7604,7 +7604,7 @@ fout_dbl_exg:
fmov.l &0x0,%fpcr # clear FPCR
fmov.l %fpsr,%d0 # save FPSR
- or.w %d0,2+USER_FPSR(%a6) # set possible inex2/ainex
+ or.w %d0,2+USER_FPSR(%a6) # set possible inex2/ainex
mov.l EXC_EA(%a6),%a1 # pass: dst addr
lea L_SCR1(%a6),%a0 # pass: src addr
@@ -7614,7 +7614,7 @@ fout_dbl_exg:
tst.l %d1 # did dstore fail?
bne.l facc_out_d # yes
- rts # no; so we're finished
+ rts # no; so we're finished
#
# here, we know that the operand would UNFL if moved out to double prec,
@@ -7636,7 +7636,7 @@ fout_dbl_unfl:
lea FP_SCR0(%a6),%a0
bsr.l norm # normalize the DENORM
-
+
fout_dbl_unfl_cont:
lea FP_SCR0(%a6),%a0 # pass: ptr to operand
mov.l L_SCR3(%a6),%d1 # pass: rnd prec,mode
@@ -7679,7 +7679,7 @@ fout_dbl_ovfl_cont:
# call ovf_res() w/ dbl prec and the correct rnd mode to create the default
# overflow result. DON'T save the returned ccodes from ovf_res() since
-# fmove out doesn't alter them.
+# fmove out doesn't alter them.
tst.b SRC_EX(%a0) # is operand negative?
smi %d1 # set if so
mov.l L_SCR3(%a6),%d0 # pass: dbl prec,rnd mode
@@ -7724,19 +7724,19 @@ fout_dbl_may_ovfl:
fabs.x %fp0 # need absolute value
fcmp.b %fp0,&0x2 # did exponent increase?
- fblt.w fout_dbl_exg # no; go finish NORM
+ fblt.w fout_dbl_exg # no; go finish NORM
bra.w fout_dbl_ovfl # yes; go handle overflow
#########################################################################
# XDEF **************************************************************** #
-# dst_dbl(): create double precision value from extended prec. #
+# dst_dbl(): create double precision value from extended prec. #
# #
# XREF **************************************************************** #
# None #
# #
# INPUT *************************************************************** #
# a0 = pointer to source operand in extended precision #
-# #
+# #
# OUTPUT ************************************************************** #
# d0 = hi(double precision result) #
# d1 = lo(double precision result) #
@@ -7750,18 +7750,18 @@ fout_dbl_may_ovfl:
# get rid of ext integer bit #
# dbl_mant = ext_mant{62:12} #
# #
-# --------------- --------------- --------------- #
+# --------------- --------------- --------------- #
# extended -> |s| exp | |1| ms mant | | ls mant | #
-# --------------- --------------- --------------- #
-# 95 64 63 62 32 31 11 0 #
+# --------------- --------------- --------------- #
+# 95 64 63 62 32 31 11 0 #
# | | #
# | | #
# | | #
-# v v #
-# --------------- --------------- #
-# double -> |s|exp| mant | | mant | #
-# --------------- --------------- #
-# 63 51 32 31 0 #
+# v v #
+# --------------- --------------- #
+# double -> |s|exp| mant | | mant | #
+# --------------- --------------- #
+# 63 51 32 31 0 #
# #
#########################################################################
@@ -7797,13 +7797,13 @@ dst_get_dman:
#########################################################################
# XDEF **************************************************************** #
-# dst_sgl(): create single precision value from extended prec #
+# dst_sgl(): create single precision value from extended prec #
# #
# XREF **************************************************************** #
# #
# INPUT *************************************************************** #
# a0 = pointer to source operand in extended precision #
-# #
+# #
# OUTPUT ************************************************************** #
# d0 = single precision result #
# #
@@ -7815,18 +7815,18 @@ dst_get_dman:
# get rid of ext integer bit #
# sgl_mant = ext_mant{62:12} #
# #
-# --------------- --------------- --------------- #
+# --------------- --------------- --------------- #
# extended -> |s| exp | |1| ms mant | | ls mant | #
-# --------------- --------------- --------------- #
-# 95 64 63 62 40 32 31 12 0 #
+# --------------- --------------- --------------- #
+# 95 64 63 62 40 32 31 12 0 #
# | | #
# | | #
# | | #
-# v v #
-# --------------- #
-# single -> |s|exp| mant | #
-# --------------- #
-# 31 22 0 #
+# v v #
+# --------------- #
+# single -> |s|exp| mant | #
+# --------------- #
+# 31 22 0 #
# #
#########################################################################
@@ -7899,7 +7899,7 @@ fout_pack_type:
# add the extra condition that only if the k-factor was zero, too, should
# we zero the exponent
tst.l %d0
- bne.b fout_pack_set
+ bne.b fout_pack_set
# "mantissa" is all zero which means that the answer is zero. but, the '040
# algorithm allows the exponent to be non-zero. the 881/2 do not. therefore,
# if the mantissa is zero, I will zero the exponent, too.
@@ -7951,7 +7951,7 @@ fout_pack_snan:
#########################################################################
# XDEF **************************************************************** #
-# fmul(): emulates the fmul instruction #
+# fmul(): emulates the fmul instruction #
# fsmul(): emulates the fsmul instruction #
# fdmul(): emulates the fdmul instruction #
# #
@@ -7960,8 +7960,8 @@ fout_pack_snan:
# scale_to_zero_dst() - scale dst exponent to zero #
# unf_res() - return default underflow result #
# ovf_res() - return default overflow result #
-# res_qnan() - return QNAN result #
-# res_snan() - return SNAN result #
+# res_qnan() - return QNAN result #
+# res_snan() - return SNAN result #
# #
# INPUT *************************************************************** #
# a0 = pointer to extended precision source operand #
@@ -7979,12 +7979,12 @@ fout_pack_snan:
# instruction won't cause an exception. Use the regular fmul to #
# compute a result. Check if the regular operands would have taken #
# an exception. If so, return the default overflow/underflow result #
-# and return the EXOP if exceptions are enabled. Else, scale the #
+# and return the EXOP if exceptions are enabled. Else, scale the #
# result operand to the proper exponent. #
# #
#########################################################################
- align 0x10
+ align 0x10
tbl_fmul_ovfl:
long 0x3fff - 0x7ffe # ext_max
long 0x3fff - 0x407e # sgl_max
@@ -8045,7 +8045,7 @@ fmul_norm:
#
# NORMAL:
# - the result of the multiply operation will neither overflow nor underflow.
-# - do the multiply to the proper precision and rounding mode.
+# - do the multiply to the proper precision and rounding mode.
# - scale the result exponent using the scale factor. if both operands were
# normalized then we really don't need to go through this scaling. but for now,
# this will do.
@@ -8056,7 +8056,7 @@ fmul_normal:
fmov.l L_SCR3(%a6),%fpcr # set FPCR
fmov.l &0x0,%fpsr # clear FPSR
- fmul.x FP_SCR0(%a6),%fp0 # execute multiply
+ fmul.x FP_SCR0(%a6),%fp0 # execute multiply
fmov.l %fpsr,%d1 # save status
fmov.l &0x0,%fpcr # clear FPCR
@@ -8096,7 +8096,7 @@ fmul_ovfl:
fmov.l L_SCR3(%a6),%fpcr # set FPCR
fmov.l &0x0,%fpsr # clear FPSR
- fmul.x FP_SCR0(%a6),%fp0 # execute multiply
+ fmul.x FP_SCR0(%a6),%fp0 # execute multiply
fmov.l %fpsr,%d1 # save status
fmov.l &0x0,%fpcr # clear FPCR
@@ -8175,7 +8175,7 @@ fmul_may_ovfl:
fmov.l &0x0,%fpsr # clear FPSR
fmul.x FP_SCR0(%a6),%fp0 # execute multiply
-
+
fmov.l %fpsr,%d1 # save status
fmov.l &0x0,%fpcr # clear FPCR
@@ -8184,7 +8184,7 @@ fmul_may_ovfl:
fabs.x %fp0,%fp1 # make a copy of result
fcmp.b %fp1,&0x2 # is |result| >= 2.b?
fbge.w fmul_ovfl_tst # yes; overflow has occurred
-
+
# no, it didn't overflow; we have correct result
bra.w fmul_normal_exit
@@ -8201,7 +8201,7 @@ fmul_may_ovfl:
# of this operation then has its exponent scaled by -0x6000 to create the
# exceptional operand.
#
-fmul_unfl:
+fmul_unfl:
bset &unfl_bit,FPSR_EXCEPT(%a6) # set unfl exc bit
# for fun, let's use only extended precision, round to zero. then, let
@@ -8234,7 +8234,7 @@ fmul_unfl_dis:
rts
#
-# UNFL is enabled.
+# UNFL is enabled.
#
fmul_unfl_ena:
fmovm.x FP_SCR1(%a6),&0x40 # load dst op
@@ -8250,7 +8250,7 @@ fmul_unfl_ena:
fmul_unfl_ena_cont:
fmov.l &0x0,%fpsr # clear FPSR
- fmul.x FP_SCR0(%a6),%fp1 # execute multiply
+ fmul.x FP_SCR0(%a6),%fp1 # execute multiply
fmov.l &0x0,%fpcr # clear FPCR
@@ -8285,7 +8285,7 @@ fmul_may_unfl:
fmov.l L_SCR3(%a6),%fpcr # set FPCR
fmov.l &0x0,%fpsr # clear FPSR
- fmul.x FP_SCR0(%a6),%fp0 # execute multiply
+ fmul.x FP_SCR0(%a6),%fp0 # execute multiply
fmov.l %fpsr,%d1 # save status
fmov.l &0x0,%fpcr # clear FPCR
@@ -8309,11 +8309,11 @@ fmul_may_unfl:
mov.l L_SCR3(%a6),%d1
andi.b &0xc0,%d1 # keep rnd prec
ori.b &rz_mode*0x10,%d1 # insert RZ
-
+
fmov.l %d1,%fpcr # set FPCR
fmov.l &0x0,%fpsr # clear FPSR
- fmul.x FP_SCR0(%a6),%fp1 # execute multiply
+ fmul.x FP_SCR0(%a6),%fp1 # execute multiply
fmov.l &0x0,%fpcr # clear FPCR
fabs.x %fp1 # make absolute value
@@ -8455,22 +8455,22 @@ fmul_inf_src:
# norm() - normalize mantissa for EXOP on denorm #
# scale_to_zero_src() - scale src exponent to zero #
# ovf_res() - return default overflow result #
-# unf_res() - return default underflow result #
+# unf_res() - return default underflow result #
# res_qnan_1op() - return QNAN result #
# res_snan_1op() - return SNAN result #
# #
# INPUT *************************************************************** #
# a0 = pointer to extended precision source operand #
# d0 = round prec/mode #
-# #
+# #
# OUTPUT ************************************************************** #
# fp0 = result #
# fp1 = EXOP (if exception occurred) #
# #
# ALGORITHM *********************************************************** #
-# Handle NANs, infinities, and zeroes as special cases. Divide #
+# Handle NANs, infinities, and zeroes as special cases. Divide #
# norms into extended, single, and double precision. #
-# Norms can be emulated w/ a regular fmove instruction. For #
+# Norms can be emulated w/ a regular fmove instruction. For #
# sgl/dbl, must scale exponent and perform an "fmove". Check to see #
# if the result would have overflowed/underflowed. If so, use unf_res() #
# or ovf_res() to return the default result. Also return EXOP if #
@@ -8496,7 +8496,7 @@ fin:
mov.b STAG(%a6),%d1 # fetch src optype tag
bne.w fin_not_norm # optimize on non-norm input
-
+
#
# FP MOVE IN: NORMs and DENORMs ONLY!
#
@@ -8557,9 +8557,9 @@ fin_denorm_unfl_ena:
#
# operand is to be rounded to single or double precision
-#
+#
fin_not_ext:
- cmpi.b %d0,&s_mode*0x10 # separate sgl/dbl prec
+ cmpi.b %d0,&s_mode*0x10 # separate sgl/dbl prec
bne.b fin_dbl
#
@@ -8643,10 +8643,10 @@ fin_sd_unfl_dis:
bsr.l unf_res # calculate default result
or.b %d0,FPSR_CC(%a6) # unf_res may have set 'Z'
fmovm.x FP_SCR0(%a6),&0x80 # return default result in fp0
- rts
+ rts
#
-# operand will underflow AND underflow or inexact is enabled.
+# operand will underflow AND underflow or inexact is enabled.
# therefore, we must return the result rounded to extended precision.
#
fin_sd_unfl_ena:
@@ -8768,7 +8768,7 @@ fin_not_norm:
#########################################################################
# XDEF **************************************************************** #
-# fdiv(): emulates the fdiv instruction #
+# fdiv(): emulates the fdiv instruction #
# fsdiv(): emulates the fsdiv instruction #
# fddiv(): emulates the fddiv instruction #
# #
@@ -8777,8 +8777,8 @@ fin_not_norm:
# scale_to_zero_dst() - scale dst exponent to zero #
# unf_res() - return default underflow result #
# ovf_res() - return default overflow result #
-# res_qnan() - return QNAN result #
-# res_snan() - return SNAN result #
+# res_qnan() - return QNAN result #
+# res_snan() - return SNAN result #
# #
# INPUT *************************************************************** #
# a0 = pointer to extended precision source operand #
@@ -8796,7 +8796,7 @@ fin_not_norm:
# instruction won't cause an exception. Use the regular fdiv to #
# compute a result. Check if the regular operands would have taken #
# an exception. If so, return the default overflow/underflow result #
-# and return the EXOP if exceptions are enabled. Else, scale the #
+# and return the EXOP if exceptions are enabled. Else, scale the #
# result operand to the proper exponent. #
# #
#########################################################################
@@ -8833,7 +8833,7 @@ fdiv:
or.b STAG(%a6),%d1 # combine src tags
bne.w fdiv_not_norm # optimize on non-norm input
-
+
#
# DIVIDE: NORMs and DENORMs ONLY!
#
@@ -8899,7 +8899,7 @@ tbl_fdiv_ovfl2:
fdiv_no_ovfl:
mov.l (%sp)+,%d0 # restore scale factor
bra.b fdiv_normal_exit
-
+
fdiv_may_ovfl:
mov.l %d0,-(%sp) # save scale factor
@@ -8932,7 +8932,7 @@ fdiv_ovfl_tst:
bne.b fdiv_ovfl_ena # yes
fdiv_ovfl_dis:
- btst &neg_bit,FPSR_CC(%a6) # is result negative?
+ btst &neg_bit,FPSR_CC(%a6) # is result negative?
sne %d1 # set sign param accordingly
mov.l L_SCR3(%a6),%d0 # pass prec:rnd
bsr.l ovf_res # calculate default result
@@ -9004,7 +9004,7 @@ fdiv_unfl_dis:
rts
#
-# UNFL is enabled.
+# UNFL is enabled.
#
fdiv_unfl_ena:
fmovm.x FP_SCR1(%a6),&0x40 # load dst op
@@ -9068,8 +9068,8 @@ fdiv_may_unfl:
#
# we still don't know if underflow occurred. result is ~ equal to 1. but,
# we don't know if the result was an underflow that rounded up to a 1
-# or a normalized number that rounded down to a 1. so, redo the entire
-# operation using RZ as the rounding mode to see what the pre-rounded
+# or a normalized number that rounded down to a 1. so, redo the entire
+# operation using RZ as the rounding mode to see what the pre-rounded
# result is. this case should be relatively rare.
#
fmovm.x FP_SCR1(%a6),&0x40 # load dst op into fp1
@@ -9196,8 +9196,8 @@ fdiv_inf_load_p:
rts
#
-# The destination was an INF w/ an In Range or ZERO source, the result is
-# an INF w/ the proper sign.
+# The destination was an INF w/ an In Range or ZERO source, the result is
+# an INF w/ the proper sign.
# The 68881/882 returns the destination INF w/ the new sign(if the j-bit of the
# dst INF is set, then then j-bit of the result INF is also set).
#
@@ -9227,11 +9227,11 @@ fdiv_inf_dst_p:
# fdneg(): emulates the fdneg instruction #
# #
# XREF **************************************************************** #
-# norm() - normalize a denorm to provide EXOP #
+# norm() - normalize a denorm to provide EXOP #
# scale_to_zero_src() - scale sgl/dbl source exponent #
# ovf_res() - return default overflow result #
# unf_res() - return default underflow result #
-# res_qnan_1op() - return QNAN result #
+# res_qnan_1op() - return QNAN result #
# res_snan_1op() - return SNAN result #
# #
# INPUT *************************************************************** #
@@ -9269,7 +9269,7 @@ fneg:
mov.l %d0,L_SCR3(%a6) # store rnd info
mov.b STAG(%a6),%d1
bne.w fneg_not_norm # optimize on non-norm input
-
+
#
# NEGATE SIGN : norms and denorms ONLY!
#
@@ -9328,7 +9328,7 @@ fneg_ext_unfl_ena:
neg.w %d0 # new exponent = -(shft val)
addi.w &0x6000,%d0 # add new bias to exponent
mov.w FP_SCR0_EX(%a6),%d1 # fetch old sign,exp
- andi.w &0x8000,%d1 # keep old sign
+ andi.w &0x8000,%d1 # keep old sign
andi.w &0x7fff,%d0 # clear sign position
or.w %d1,%d0 # concat old sign, new exponent
mov.w %d0,FP_SCR0_EX(%a6) # insert new exponent
@@ -9407,7 +9407,7 @@ fneg_dbl:
fneg_sd_unfl:
bset &unfl_bit,FPSR_EXCEPT(%a6) # set unfl exc bit
- eori.b &0x80,FP_SCR0_EX(%a6) # negate sign
+ eori.b &0x80,FP_SCR0_EX(%a6) # negate sign
bpl.b fneg_sd_unfl_tst
bset &neg_bit,FPSR_CC(%a6) # set 'N' ccode bit
@@ -9423,10 +9423,10 @@ fneg_sd_unfl_dis:
bsr.l unf_res # calculate default result
or.b %d0,FPSR_CC(%a6) # unf_res may have set 'Z'
fmovm.x FP_SCR0(%a6),&0x80 # return default result in fp0
- rts
+ rts
#
-# operand will underflow AND underflow is enabled.
+# operand will underflow AND underflow is enabled.
# therefore, we must return the result rounded to extended precision.
#
fneg_sd_unfl_ena:
@@ -9548,19 +9548,19 @@ fneg_not_norm:
#########################################################################
# XDEF **************************************************************** #
-# ftst(): emulates the ftest instruction #
+# ftst(): emulates the ftest instruction #
# #
# XREF **************************************************************** #
-# res{s,q}nan_1op() - set NAN result for monadic instruction #
+# res{s,q}nan_1op() - set NAN result for monadic instruction #
# #
# INPUT *************************************************************** #
-# a0 = pointer to extended precision source operand #
+# a0 = pointer to extended precision source operand #
# #
# OUTPUT ************************************************************** #
# none #
# #
# ALGORITHM *********************************************************** #
-# Check the source operand tag (STAG) and set the FPCR according #
+# Check the source operand tag (STAG) and set the FPCR according #
# to the operand type and sign. #
# #
#########################################################################
@@ -9569,7 +9569,7 @@ fneg_not_norm:
ftst:
mov.b STAG(%a6),%d1
bne.b ftst_not_norm # optimize on non-norm input
-
+
#
# Norm:
#
@@ -9617,7 +9617,7 @@ ftst_inf_p:
ftst_inf_m:
mov.b &inf_bmask+neg_bmask,FPSR_CC(%a6) # set 'I','N' ccode bits
rts
-
+
#
# Zero:
#
@@ -9646,13 +9646,13 @@ ftst_zero_m:
# fp0 = result #
# #
# ALGORITHM *********************************************************** #
-# Separate according to operand type. Unnorms don't pass through #
-# here. For norms, load the rounding mode/prec, execute a "fint", then #
+# Separate according to operand type. Unnorms don't pass through #
+# here. For norms, load the rounding mode/prec, execute a "fint", then #
# store the resulting FPSR bits. #
-# For denorms, force the j-bit to a one and do the same as for #
-# norms. Denorms are so low that the answer will either be a zero or a #
+# For denorms, force the j-bit to a one and do the same as for #
+# norms. Denorms are so low that the answer will either be a zero or a #
# one. #
-# For zeroes/infs/NANs, return the same while setting the FPSR #
+# For zeroes/infs/NANs, return the same while setting the FPSR #
# as appropriate. #
# #
#########################################################################
@@ -9661,7 +9661,7 @@ ftst_zero_m:
fint:
mov.b STAG(%a6),%d1
bne.b fint_not_norm # optimize on non-norm input
-
+
#
# Norm:
#
@@ -9671,7 +9671,7 @@ fint_norm:
fmov.l %d0,%fpcr # set FPCR
fmov.l &0x0,%fpsr # clear FPSR
- fint.x SRC(%a0),%fp0 # execute fint
+ fint.x SRC(%a0),%fp0 # execute fint
fmov.l &0x0,%fpcr # clear FPCR
fmov.l %fpsr,%d0 # save FPSR
@@ -9749,16 +9749,16 @@ fint_inf_m:
# d0 = round precision/mode #
# #
# OUTPUT ************************************************************** #
-# fp0 = result #
+# fp0 = result #
# #
# ALGORITHM *********************************************************** #
# Separate according to operand type. Unnorms don't pass through #
-# here. For norms, load the rounding mode/prec, execute a "fintrz", #
+# here. For norms, load the rounding mode/prec, execute a "fintrz", #
# then store the resulting FPSR bits. #
-# For denorms, force the j-bit to a one and do the same as for #
+# For denorms, force the j-bit to a one and do the same as for #
# norms. Denorms are so low that the answer will either be a zero or a #
# one. #
-# For zeroes/infs/NANs, return the same while setting the FPSR #
+# For zeroes/infs/NANs, return the same while setting the FPSR #
# as appropriate. #
# #
#########################################################################
@@ -9767,7 +9767,7 @@ fint_inf_m:
fintrz:
mov.b STAG(%a6),%d1
bne.b fintrz_not_norm # optimize on non-norm input
-
+
#
# Norm:
#
@@ -9862,17 +9862,17 @@ fintrz_inf_m:
# #
# ALGORITHM *********************************************************** #
# Handle NANs, infinities, and zeroes as special cases. Divide #
-# norms into extended, single, and double precision. #
-# Simply clear sign for extended precision norm. Ext prec denorm #
+# norms into extended, single, and double precision. #
+# Simply clear sign for extended precision norm. Ext prec denorm #
# gets an EXOP created for it since it's an underflow. #
# Double and single precision can overflow and underflow. First, #
# scale the operand such that the exponent is zero. Perform an "fabs" #
-# using the correct rnd mode/prec. Check to see if the original #
+# using the correct rnd mode/prec. Check to see if the original #
# exponent would take an exception. If so, use unf_res() or ovf_res() #
# to calculate the default result. Also, create the EXOP for the #
-# exceptional case. If no exception should occur, insert the correct #
+# exceptional case. If no exception should occur, insert the correct #
# result exponent and return. #
-# Unnorms don't pass through here. #
+# Unnorms don't pass through here. #
# #
#########################################################################
@@ -9892,7 +9892,7 @@ fabs:
mov.l %d0,L_SCR3(%a6) # store rnd info
mov.b STAG(%a6),%d1
bne.w fabs_not_norm # optimize on non-norm input
-
+
#
# ABSOLUTE VALUE: norms and denorms ONLY!
#
@@ -10038,10 +10038,10 @@ fabs_sd_unfl_dis:
bsr.l unf_res # calculate default result
or.b %d0,FPSR_CC(%a6) # set possible 'Z' ccode
fmovm.x FP_SCR0(%a6),&0x80 # return default result in fp0
- rts
+ rts
#
-# operand will underflow AND underflow is enabled.
+# operand will underflow AND underflow is enabled.
# therefore, we must return the result rounded to extended precision.
#
fabs_sd_unfl_ena:
@@ -10163,10 +10163,10 @@ fabs_inf:
#########################################################################
# XDEF **************************************************************** #
-# fcmp(): fp compare op routine #
+# fcmp(): fp compare op routine #
# #
# XREF **************************************************************** #
-# res_qnan() - return QNAN result #
+# res_qnan() - return QNAN result #
# res_snan() - return SNAN result #
# #
# INPUT *************************************************************** #
@@ -10178,7 +10178,7 @@ fabs_inf:
# None #
# #
# ALGORITHM *********************************************************** #
-# Handle NANs and denorms as special cases. For everything else, #
+# Handle NANs and denorms as special cases. For everything else, #
# just use the actual fcmp instruction to produce the correct condition #
# codes. #
# #
@@ -10191,14 +10191,14 @@ fcmp:
lsl.b &0x3,%d1
or.b STAG(%a6),%d1
bne.b fcmp_not_norm # optimize on non-norm input
-
+
#
# COMPARE FP OPs : NORMs, ZEROs, INFs, and "corrected" DENORMs
#
fcmp_norm:
fmovm.x DST(%a1),&0x80 # load dst op
- fcmp.x %fp0,SRC(%a0) # do compare
+ fcmp.x %fp0,SRC(%a0) # do compare
fmov.l %fpsr,%d0 # save FPSR
rol.l &0x8,%d0 # extract ccode bits
@@ -10219,7 +10219,7 @@ tbl_fcmp_op:
short fcmp_norm - tbl_fcmp_op # NORM - ZERO
short fcmp_norm - tbl_fcmp_op # NORM - INF
short fcmp_res_qnan - tbl_fcmp_op # NORM - QNAN
- short fcmp_nrm_dnrm - tbl_fcmp_op # NORM - DENORM
+ short fcmp_nrm_dnrm - tbl_fcmp_op # NORM - DENORM
short fcmp_res_snan - tbl_fcmp_op # NORM - SNAN
short tbl_fcmp_op - tbl_fcmp_op #
short tbl_fcmp_op - tbl_fcmp_op #
@@ -10281,8 +10281,8 @@ fcmp_res_snan:
rts
#
-# DENORMs are a little more difficult.
-# If you have a 2 DENORMs, then you can just force the j-bit to a one
+# DENORMs are a little more difficult.
+# If you have a 2 DENORMs, then you can just force the j-bit to a one
# and use the fcmp_norm routine.
# If you have a DENORM and an INF or ZERO, just force the DENORM's j-bit to a one
# and use the fcmp_norm routine.
@@ -10323,7 +10323,7 @@ fcmp_dnrm_sd:
mov.l SRC_LO(%a0),FP_SCR0_LO(%a6)
lea FP_SCR1(%a6),%a1
lea FP_SCR0(%a6),%a0
- bra.w fcmp_norm
+ bra.w fcmp_norm
fcmp_nrm_dnrm:
mov.b SRC_EX(%a0),%d0 # determine if like signs
@@ -10355,15 +10355,15 @@ fcmp_dnrm_nrm_m:
#########################################################################
# XDEF **************************************************************** #
-# fsglmul(): emulates the fsglmul instruction #
+# fsglmul(): emulates the fsglmul instruction #
# #
# XREF **************************************************************** #
# scale_to_zero_src() - scale src exponent to zero #
# scale_to_zero_dst() - scale dst exponent to zero #
# unf_res4() - return default underflow result for sglop #
# ovf_res() - return default overflow result #
-# res_qnan() - return QNAN result #
-# res_snan() - return SNAN result #
+# res_qnan() - return QNAN result #
+# res_snan() - return SNAN result #
# #
# INPUT *************************************************************** #
# a0 = pointer to extended precision source operand #
@@ -10381,7 +10381,7 @@ fcmp_dnrm_nrm_m:
# instruction won't cause an exception. Use the regular fsglmul to #
# compute a result. Check if the regular operands would have taken #
# an exception. If so, return the default overflow/underflow result #
-# and return the EXOP if exceptions are enabled. Else, scale the #
+# and return the EXOP if exceptions are enabled. Else, scale the #
# result operand to the proper exponent. #
# #
#########################################################################
@@ -10413,11 +10413,11 @@ fsglmul_norm:
add.l (%sp)+,%d0 # SCALE_FACTOR = scale1 + scale2
- cmpi.l %d0,&0x3fff-0x7ffe # would result ovfl?
+ cmpi.l %d0,&0x3fff-0x7ffe # would result ovfl?
beq.w fsglmul_may_ovfl # result may rnd to overflow
blt.w fsglmul_ovfl # result will overflow
- cmpi.l %d0,&0x3fff+0x0001 # would result unfl?
+ cmpi.l %d0,&0x3fff+0x0001 # would result unfl?
beq.w fsglmul_may_unfl # result may rnd to no unfl
bgt.w fsglmul_unfl # result will underflow
@@ -10504,7 +10504,7 @@ fsglmul_may_ovfl:
fmov.l &0x0,%fpsr # clear FPSR
fsglmul.x FP_SCR0(%a6),%fp0 # execute sgl multiply
-
+
fmov.l %fpsr,%d1 # save status
fmov.l &0x0,%fpcr # clear FPCR
@@ -10513,7 +10513,7 @@ fsglmul_may_ovfl:
fabs.x %fp0,%fp1 # make a copy of result
fcmp.b %fp1,&0x2 # is |result| >= 2.b?
fbge.w fsglmul_ovfl_tst # yes; overflow has occurred
-
+
# no, it didn't overflow; we have correct result
bra.w fsglmul_normal_exit
@@ -10547,7 +10547,7 @@ fsglmul_unfl_dis:
rts
#
-# UNFL is enabled.
+# UNFL is enabled.
#
fsglmul_unfl_ena:
fmovm.x FP_SCR1(%a6),&0x40 # load dst op
@@ -10555,7 +10555,7 @@ fsglmul_unfl_ena:
fmov.l L_SCR3(%a6),%fpcr # set FPCR
fmov.l &0x0,%fpsr # clear FPSR
- fsglmul.x FP_SCR0(%a6),%fp1 # execute sgl multiply
+ fsglmul.x FP_SCR0(%a6),%fp1 # execute sgl multiply
fmov.l &0x0,%fpcr # clear FPCR
@@ -10580,7 +10580,7 @@ fsglmul_may_unfl:
fmov.l L_SCR3(%a6),%fpcr # set FPCR
fmov.l &0x0,%fpsr # clear FPSR
- fsglmul.x FP_SCR0(%a6),%fp0 # execute sgl multiply
+ fsglmul.x FP_SCR0(%a6),%fp0 # execute sgl multiply
fmov.l %fpsr,%d1 # save status
fmov.l &0x0,%fpcr # clear FPCR
@@ -10604,11 +10604,11 @@ fsglmul_may_unfl:
mov.l L_SCR3(%a6),%d1
andi.b &0xc0,%d1 # keep rnd prec
ori.b &rz_mode*0x10,%d1 # insert RZ
-
+
fmov.l %d1,%fpcr # set FPCR
fmov.l &0x0,%fpsr # clear FPSR
- fsglmul.x FP_SCR0(%a6),%fp1 # execute sgl multiply
+ fsglmul.x FP_SCR0(%a6),%fp1 # execute sgl multiply
fmov.l &0x0,%fpcr # clear FPCR
fabs.x %fp1 # make absolute value
@@ -10696,15 +10696,15 @@ fsglmul_inf_dst:
#########################################################################
# XDEF **************************************************************** #
-# fsgldiv(): emulates the fsgldiv instruction #
+# fsgldiv(): emulates the fsgldiv instruction #
# #
# XREF **************************************************************** #
# scale_to_zero_src() - scale src exponent to zero #
# scale_to_zero_dst() - scale dst exponent to zero #
# unf_res4() - return default underflow result for sglop #
# ovf_res() - return default overflow result #
-# res_qnan() - return QNAN result #
-# res_snan() - return SNAN result #
+# res_qnan() - return QNAN result #
+# res_snan() - return SNAN result #
# #
# INPUT *************************************************************** #
# a0 = pointer to extended precision source operand #
@@ -10722,7 +10722,7 @@ fsglmul_inf_dst:
# instruction won't cause an exception. Use the regular fsgldiv to #
# compute a result. Check if the regular operands would have taken #
# an exception. If so, return the default overflow/underflow result #
-# and return the EXOP if exceptions are enabled. Else, scale the #
+# and return the EXOP if exceptions are enabled. Else, scale the #
# result operand to the proper exponent. #
# #
#########################################################################
@@ -10737,7 +10737,7 @@ fsgldiv:
or.b STAG(%a6),%d1 # combine src tags
bne.w fsgldiv_not_norm # optimize on non-norm input
-
+
#
# DIVIDE: NORMs and DENORMs ONLY!
#
@@ -10764,7 +10764,7 @@ fsgldiv_norm:
cmpi.l %d0,&0x3fff-0x7ffe
ble.w fsgldiv_may_ovfl
- cmpi.l %d0,&0x3fff-0x0000 # will result underflow?
+ cmpi.l %d0,&0x3fff-0x0000 # will result underflow?
beq.w fsgldiv_may_unfl # maybe
bgt.w fsgldiv_unfl # yes; go handle underflow
@@ -10824,7 +10824,7 @@ fsgldiv_ovfl_tst:
bne.b fsgldiv_ovfl_ena # yes
fsgldiv_ovfl_dis:
- btst &neg_bit,FPSR_CC(%a6) # is result negative
+ btst &neg_bit,FPSR_CC(%a6) # is result negative
sne %d1 # set sign param accordingly
mov.l L_SCR3(%a6),%d0 # pass prec:rnd
andi.b &0x30,%d0 # kill precision
@@ -10880,7 +10880,7 @@ fsgldiv_unfl_dis:
rts
#
-# UNFL is enabled.
+# UNFL is enabled.
#
fsgldiv_unfl_ena:
fmovm.x FP_SCR1(%a6),&0x40 # load dst op
@@ -10931,8 +10931,8 @@ fsgldiv_may_unfl:
#
# we still don't know if underflow occurred. result is ~ equal to 1. but,
# we don't know if the result was an underflow that rounded up to a 1
-# or a normalized number that rounded down to a 1. so, redo the entire
-# operation using RZ as the rounding mode to see what the pre-rounded
+# or a normalized number that rounded down to a 1. so, redo the entire
+# operation using RZ as the rounding mode to see what the pre-rounded
# result is. this case should be relatively rare.
#
fmovm.x FP_SCR1(%a6),&0x40 # load dst op into %fp1
@@ -11036,25 +11036,25 @@ fsgldiv_inf_dst:
# fdadd(): emulates the fdadd instruction #
# #
# XREF **************************************************************** #
-# addsub_scaler2() - scale the operands so they won't take exc #
+# addsub_scaler2() - scale the operands so they won't take exc #
# ovf_res() - return default overflow result #
# unf_res() - return default underflow result #
# res_qnan() - set QNAN result #
-# res_snan() - set SNAN result #
+# res_snan() - set SNAN result #
# res_operr() - set OPERR result #
# scale_to_zero_src() - set src operand exponent equal to zero #
# scale_to_zero_dst() - set dst operand exponent equal to zero #
# #
# INPUT *************************************************************** #
# a0 = pointer to extended precision source operand #
-# a1 = pointer to extended precision destination operand #
+# a1 = pointer to extended precision destination operand #
# #
# OUTPUT ************************************************************** #
# fp0 = result #
# fp1 = EXOP (if exception occurred) #
# #
# ALGORITHM *********************************************************** #
-# Handle NANs, infinities, and zeroes as special cases. Divide #
+# Handle NANs, infinities, and zeroes as special cases. Divide #
# norms into extended, single, and double precision. #
# Do addition after scaling exponents such that exception won't #
# occur. Then, check result exponent to see if exception would have #
@@ -11268,7 +11268,7 @@ fadd_unfl_ena_sd:
#
# result is equal to the smallest normalized number in the selected precision
-# if the precision is extended, this result could not have come from an
+# if the precision is extended, this result could not have come from an
# underflow that rounded up.
#
fadd_may_unfl:
@@ -11290,7 +11290,7 @@ fadd_may_unfl:
# ok, so now the result has a exponent equal to the smallest normalized
# exponent for the selected precision. also, the mantissa is equal to
# 0x8000000000000000 and this mantissa is the result of rounding non-zero
-# g,r,s.
+# g,r,s.
# now, we must determine whether the pre-rounded result was an underflow
# rounded "up" or a normalized number rounded "down".
# so, we do this be re-executing the add using RZ as the rounding mode and
@@ -11401,7 +11401,7 @@ fadd_zero_2:
fmov.s &0x00000000,%fp0 # return +ZERO
mov.b &z_bmask,FPSR_CC(%a6) # set Z
rts
-
+
#
# the ZEROes have opposite signs:
# - therefore, we return +ZERO if the rounding modes are RN,RZ, or RP.
@@ -11455,7 +11455,7 @@ fadd_inf_2:
eor.b %d1,%d0
bmi.l res_operr # weed out (-INF)+(+INF)
-# ok, so it's not an OPERR. but, we do have to remember to return the
+# ok, so it's not an OPERR. but, we do have to remember to return the
# src INF since that's where the 881/882 gets the j-bit from...
#
@@ -11489,25 +11489,25 @@ fadd_inf_done:
# fdsub(): emulates the fdsub instruction #
# #
# XREF **************************************************************** #
-# addsub_scaler2() - scale the operands so they won't take exc #
+# addsub_scaler2() - scale the operands so they won't take exc #
# ovf_res() - return default overflow result #
# unf_res() - return default underflow result #
# res_qnan() - set QNAN result #
-# res_snan() - set SNAN result #
+# res_snan() - set SNAN result #
# res_operr() - set OPERR result #
# scale_to_zero_src() - set src operand exponent equal to zero #
# scale_to_zero_dst() - set dst operand exponent equal to zero #
# #
# INPUT *************************************************************** #
# a0 = pointer to extended precision source operand #
-# a1 = pointer to extended precision destination operand #
+# a1 = pointer to extended precision destination operand #
# #
# OUTPUT ************************************************************** #
# fp0 = result #
# fp1 = EXOP (if exception occurred) #
# #
# ALGORITHM *********************************************************** #
-# Handle NANs, infinities, and zeroes as special cases. Divide #
+# Handle NANs, infinities, and zeroes as special cases. Divide #
# norms into extended, single, and double precision. #
# Do subtraction after scaling exponents such that exception won't#
# occur. Then, check result exponent to see if exception would have #
@@ -11657,7 +11657,7 @@ fsub_unfl:
add.l &0xc,%sp
fmovm.x FP_SCR1(%a6),&0x80 # load dst op
-
+
fmov.l &rz_mode*0x10,%fpcr # set FPCR
fmov.l &0x0,%fpsr # clear FPSR
@@ -11721,7 +11721,7 @@ fsub_unfl_ena_sd:
#
# result is equal to the smallest normalized number in the selected precision
-# if the precision is extended, this result could not have come from an
+# if the precision is extended, this result could not have come from an
# underflow that rounded up.
#
fsub_may_unfl:
@@ -11743,7 +11743,7 @@ fsub_may_unfl:
# ok, so now the result has a exponent equal to the smallest normalized
# exponent for the selected precision. also, the mantissa is equal to
# 0x8000000000000000 and this mantissa is the result of rounding non-zero
-# g,r,s.
+# g,r,s.
# now, we must determine whether the pre-rounded result was an underflow
# rounded "up" or a normalized number rounded "down".
# so, we do this be re-executing the add using RZ as the rounding mode and
@@ -11899,7 +11899,7 @@ fsub_zero_src:
#
# both operands are INFs. an OPERR will result if the INFs have the
-# same signs. else,
+# same signs. else,
#
fsub_inf_2:
mov.b SRC_EX(%a0),%d0 # exclusive or the signs
@@ -11914,7 +11914,7 @@ fsub_inf_src:
fmovm.x SRC(%a0),&0x80 # return src INF
fneg.x %fp0 # invert sign
fbge.w fsub_inf_done # sign is now positive
- mov.b &neg_bmask+inf_bmask,FPSR_CC(%a6) # set INF/NEG
+ mov.b &neg_bmask+inf_bmask,FPSR_CC(%a6) # set INF/NEG
rts
fsub_inf_dst:
@@ -11930,7 +11930,7 @@ fsub_inf_done:
#########################################################################
# XDEF **************************************************************** #
-# fsqrt(): emulates the fsqrt instruction #
+# fsqrt(): emulates the fsqrt instruction #
# fssqrt(): emulates the fssqrt instruction #
# fdsqrt(): emulates the fdsqrt instruction #
# #
@@ -11938,8 +11938,8 @@ fsub_inf_done:
# scale_sqrt() - scale the source operand #
# unf_res() - return default underflow result #
# ovf_res() - return default overflow result #
-# res_qnan_1op() - return QNAN result #
-# res_snan_1op() - return SNAN result #
+# res_qnan_1op() - return QNAN result #
+# res_snan_1op() - return SNAN result #
# #
# INPUT *************************************************************** #
# a0 = pointer to extended precision source operand #
@@ -11956,7 +11956,7 @@ fsub_inf_done:
# instruction won't cause an exception. Use the regular fsqrt to #
# compute a result. Check if the regular operands would have taken #
# an exception. If so, return the default overflow/underflow result #
-# and return the EXOP if exceptions are enabled. Else, scale the #
+# and return the EXOP if exceptions are enabled. Else, scale the #
# result operand to the proper exponent. #
# #
#########################################################################
@@ -11978,7 +11978,7 @@ fsqrt:
clr.w %d1
mov.b STAG(%a6),%d1
bne.w fsqrt_not_norm # optimize on non-norm input
-
+
#
# SQUARE ROOT: norms and denorms ONLY!
#
@@ -12100,7 +12100,7 @@ fsqrt_sd_unfl:
fmov.l &rz_mode*0x10,%fpcr # set FPCR
fmov.l &0x0,%fpsr # clear FPSR
- fsqrt.x FP_SCR0(%a6),%fp0 # execute square root
+ fsqrt.x FP_SCR0(%a6),%fp0 # execute square root
fmov.l %fpsr,%d1 # save status
fmov.l &0x0,%fpcr # clear FPCR
@@ -12120,10 +12120,10 @@ fsqrt_sd_unfl_dis:
bsr.l unf_res # calculate default result
or.b %d0,FPSR_CC(%a6) # set possible 'Z' ccode
fmovm.x FP_SCR0(%a6),&0x80 # return default result in fp0
- rts
+ rts
#
-# operand will underflow AND underflow is enabled.
+# operand will underflow AND underflow is enabled.
# therefore, we must return the result rounded to extended precision.
#
fsqrt_sd_unfl_ena:
@@ -12239,15 +12239,15 @@ fsqrt_not_norm:
bra.l res_qnan_1op
#
-# fsqrt(+0) = +0
-# fsqrt(-0) = -0
+# fsqrt(+0) = +0
+# fsqrt(-0) = -0
# fsqrt(+INF) = +INF
-# fsqrt(-INF) = OPERR
+# fsqrt(-INF) = OPERR
#
fsqrt_zero:
tst.b SRC_EX(%a0) # is ZERO positive or negative?
bmi.b fsqrt_zero_m # negative
-fsqrt_zero_p:
+fsqrt_zero_p:
fmov.s &0x00000000,%fp0 # return +ZERO
mov.b &z_bmask,FPSR_CC(%a6) # set 'Z' ccode bit
rts
@@ -12273,13 +12273,13 @@ fsqrt_inf_p:
# #
# INPUT *************************************************************** #
# d1 = index of register to fetch from #
-# #
+# #
# OUTPUT ************************************************************** #
# d0 = value of register fetched #
# #
# ALGORITHM *********************************************************** #
-# According to the index value in d1 which can range from zero #
-# to fifteen, load the corresponding register file value (where #
+# According to the index value in d1 which can range from zero #
+# to fifteen, load the corresponding register file value (where #
# address register indexes start at 8). D0/D1/A0/A1/A6/A7 are on the #
# stack. The rest should still be in their original places. #
# #
@@ -12368,7 +12368,7 @@ fdregf:
# INPUT *************************************************************** #
# d0 = longowrd value to store #
# d1 = index of register to fetch from #
-# #
+# #
# OUTPUT ************************************************************** #
# (data register is updated) #
# #
@@ -12429,7 +12429,7 @@ sdregl7:
# INPUT *************************************************************** #
# d0 = word value to store #
# d1 = index of register to fetch from #
-# #
+# #
# OUTPUT ************************************************************** #
# (data register is updated) #
# #
@@ -12490,7 +12490,7 @@ sdregw7:
# INPUT *************************************************************** #
# d0 = byte value to store #
# d1 = index of register to fetch from #
-# #
+# #
# OUTPUT ************************************************************** #
# (data register is updated) #
# #
@@ -12551,16 +12551,16 @@ sdregb7:
# INPUT *************************************************************** #
# d0 = amount to increment by #
# d1 = index of address register to increment #
-# #
+# #
# OUTPUT ************************************************************** #
# (address register is updated) #
# #
# ALGORITHM *********************************************************** #
-# Typically used for an instruction w/ a post-increment <ea>, #
+# Typically used for an instruction w/ a post-increment <ea>, #
# this routine adds the increment value in d0 to the address register #
# specified by d1. A0/A1/A6/A7 reside on the stack. The rest reside #
# in their original places. #
-# For a7, if the increment amount is one, then we have to #
+# For a7, if the increment amount is one, then we have to #
# increment by two. For any a7 update, set the mia7_flag so that if #
# an access error exception occurs later in emulation, this address #
# register update can be undone. #
@@ -12615,16 +12615,16 @@ iareg7b:
# INPUT *************************************************************** #
# d0 = amount to decrement by #
# d1 = index of address register to decrement #
-# #
+# #
# OUTPUT ************************************************************** #
# (address register is updated) #
# #
# ALGORITHM *********************************************************** #
-# Typically used for an instruction w/ a pre-decrement <ea>, #
+# Typically used for an instruction w/ a pre-decrement <ea>, #
# this routine adds the decrement value in d0 to the address register #
# specified by d1. A0/A1/A6/A7 reside on the stack. The rest reside #
# in their original places. #
-# For a7, if the decrement amount is one, then we have to #
+# For a7, if the decrement amount is one, then we have to #
# decrement by two. For any a7 update, set the mda7_flag so that if #
# an access error exception occurs later in emulation, this address #
# register update can be undone. #
@@ -12680,17 +12680,17 @@ dareg7b:
# #
# INPUT *************************************************************** #
# d0 = index of FP register to load #
-# #
+# #
# OUTPUT ************************************************************** #
# FP_SRC(a6) = value loaded from FP register file #
# #
# ALGORITHM *********************************************************** #
-# Using the index in d0, load FP_SRC(a6) with a number from the #
+# Using the index in d0, load FP_SRC(a6) with a number from the #
# FP register file. #
# #
#########################################################################
- global load_fpn1
+ global load_fpn1
load_fpn1:
mov.w (tbl_load_fpn1.b,%pc,%d0.w*2), %d0
jmp (tbl_load_fpn1.b,%pc,%d0.w*1)
@@ -12753,12 +12753,12 @@ load_fpn1_7:
# #
# INPUT *************************************************************** #
# d0 = index of FP register to load #
-# #
+# #
# OUTPUT ************************************************************** #
# FP_DST(a6) = value loaded from FP register file #
# #
# ALGORITHM *********************************************************** #
-# Using the index in d0, load FP_DST(a6) with a number from the #
+# Using the index in d0, load FP_DST(a6) with a number from the #
# FP register file. #
# #
#########################################################################
@@ -12819,7 +12819,7 @@ load_fpn2_7:
#########################################################################
# XDEF **************************************************************** #
-# store_fpreg(): store an fp value to the fpreg designated d0. #
+# store_fpreg(): store an fp value to the fpreg designated d0. #
# #
# XREF **************************************************************** #
# None #
@@ -12827,7 +12827,7 @@ load_fpn2_7:
# INPUT *************************************************************** #
# fp0 = extended precision value to store #
# d0 = index of floating-point register #
-# #
+# #
# OUTPUT ************************************************************** #
# None #
# #
@@ -12860,27 +12860,27 @@ store_fpreg_1:
fmovm.x &0x80, EXC_FP1(%a6)
rts
store_fpreg_2:
- fmovm.x &0x01, -(%sp)
+ fmovm.x &0x01, -(%sp)
fmovm.x (%sp)+, &0x20
rts
store_fpreg_3:
- fmovm.x &0x01, -(%sp)
+ fmovm.x &0x01, -(%sp)
fmovm.x (%sp)+, &0x10
rts
store_fpreg_4:
- fmovm.x &0x01, -(%sp)
+ fmovm.x &0x01, -(%sp)
fmovm.x (%sp)+, &0x08
rts
store_fpreg_5:
- fmovm.x &0x01, -(%sp)
+ fmovm.x &0x01, -(%sp)
fmovm.x (%sp)+, &0x04
rts
store_fpreg_6:
- fmovm.x &0x01, -(%sp)
+ fmovm.x &0x01, -(%sp)
fmovm.x (%sp)+, &0x02
rts
store_fpreg_7:
- fmovm.x &0x01, -(%sp)
+ fmovm.x &0x01, -(%sp)
fmovm.x (%sp)+, &0x01
rts
@@ -12897,18 +12897,18 @@ store_fpreg_7:
# #
# INPUT *************************************************************** #
# None #
-# #
+# #
# OUTPUT ************************************************************** #
# If no failure on _mem_read(): #
-# FP_SRC(a6) = packed operand now as a binary FP number #
+# FP_SRC(a6) = packed operand now as a binary FP number #
# #
# ALGORITHM *********************************************************** #
-# Get the correct <ea> whihc is the value on the exception stack #
+# Get the correct <ea> whihc is the value on the exception stack #
# frame w/ maybe a correction factor if the <ea> is -(an) or (an)+. #
# Then, fetch the operand from memory. If the fetch fails, exit #
# through facc_in_x(). #
# If the packed operand is a ZERO,NAN, or INF, convert it to #
-# its binary representation here. Else, call decbin() which will #
+# its binary representation here. Else, call decbin() which will #
# convert the packed value to an extended precision binary value. #
# #
#########################################################################
@@ -12965,7 +12965,7 @@ gp_not_spec:
# and NaN operands are dispatched without entering this routine) #
# value in 68881/882 format at location (a0). #
# #
-# A1. Convert the bcd exponent to binary by successive adds and #
+# A1. Convert the bcd exponent to binary by successive adds and #
# muls. Set the sign according to SE. Subtract 16 to compensate #
# for the mantissa which is to be interpreted as 17 integer #
# digits, rather than 1 integer and 16 fraction digits. #
@@ -13029,7 +13029,7 @@ RTABLE:
global decbin
decbin:
- mov.l 0x0(%a0),FP_SCR0_EX(%a6) # make a copy of input
+ mov.l 0x0(%a0),FP_SCR0_EX(%a6) # make a copy of input
mov.l 0x4(%a0),FP_SCR0_HI(%a6) # so we don't alter it
mov.l 0x8(%a0),FP_SCR0_LO(%a6)
@@ -13318,7 +13318,7 @@ ap_n_en:
#
# Pwrten calculates the exponent factor in the selected rounding mode
# according to the following table:
-#
+#
# Sign of Mant Sign of Exp Rounding Mode PWRTEN Rounding Mode
#
# ANY ANY RN RN
@@ -13406,7 +13406,7 @@ mul:
# it will be inex2, but will be reported as inex1 by get_op.
#
end_dec:
- fmov.l %fpsr,%d0 # get status register
+ fmov.l %fpsr,%d0 # get status register
bclr &inex2_bit+8,%d0 # test for inex2 and clear it
beq.b no_exc # skip this if no exc
ori.w &inx1a_mask,2+USER_FPSR(%a6) # set INEX1/AINEX
@@ -13423,16 +13423,16 @@ no_exc:
# #
# INPUT *************************************************************** #
# a0 = pointer to the input extended precision value in memory. #
-# the input may be either normalized, unnormalized, or #
+# the input may be either normalized, unnormalized, or #
# denormalized. #
-# d0 = contains the k-factor sign-extended to 32-bits. #
+# d0 = contains the k-factor sign-extended to 32-bits. #
# #
# OUTPUT ************************************************************** #
# FP_SCR0(a6) = bcd format result on the stack. #
# #
# ALGORITHM *********************************************************** #
# #
-# A1. Set RM and size ext; Set SIGMA = sign of input. #
+# A1. Set RM and size ext; Set SIGMA = sign of input. #
# The k-factor is saved for use in d7. Clear the #
# BINDEC_FLG for separating normalized/denormalized #
# input. If input is unnormalized or denormalized, #
@@ -13442,15 +13442,15 @@ no_exc:
# #
# A3. Compute ILOG. #
# ILOG is the log base 10 of the input value. It is #
-# approximated by adding e + 0.f when the original #
-# value is viewed as 2^^e * 1.f in extended precision. #
+# approximated by adding e + 0.f when the original #
+# value is viewed as 2^^e * 1.f in extended precision. #
# This value is stored in d6. #
# #
# A4. Clr INEX bit. #
-# The operation in A3 above may have set INEX2. #
+# The operation in A3 above may have set INEX2. #
# #
# A5. Set ICTR = 0; #
-# ICTR is a flag used in A13. It must be set before the #
+# ICTR is a flag used in A13. It must be set before the #
# loop entry A6. #
# #
# A6. Calculate LEN. #
@@ -13472,7 +13472,7 @@ no_exc:
# of ISCALE and X. A table is given in the code. #
# #
# A8. Clr INEX; Force RZ. #
-# The operation in A3 above may have set INEX2. #
+# The operation in A3 above may have set INEX2. #
# RZ mode is forced for the scaling operation to insure #
# only one rounding error. The grs bits are collected in #
# the INEX flag for use in A10. #
@@ -13503,11 +13503,11 @@ no_exc:
# the mantissa by 10. #
# #
# A14. Convert the mantissa to bcd. #
-# The binstr routine is used to convert the LEN digit #
+# The binstr routine is used to convert the LEN digit #
# mantissa to bcd in memory. The input to binstr is #
# to be a fraction; i.e. (mantissa)/10^LEN and adjusted #
# such that the decimal point is to the left of bit 63. #
-# The bcd digits are stored in the correct position in #
+# The bcd digits are stored in the correct position in #
# the final string area in memory. #
# #
# A15. Convert the exponent to bcd. #
@@ -13553,7 +13553,7 @@ RBDTBL:
# d2: upper 32-bits of mantissa for binstr
# d3: scratch;lower 32-bits of mantissa for binstr
# d4: LEN
-# d5: LAMBDA/ICTR
+# d5: LAMBDA/ICTR
# d6: ILOG
# d7: k-factor
# a0: ptr for original operand/final result
@@ -13577,7 +13577,7 @@ bindec:
# separating normalized/denormalized input. If the input
# is a denormalized number, set the BINDEC_FLG memory word
# to signal denorm. If the input is unnormalized, normalize
-# the input and test for denormalized result.
+# the input and test for denormalized result.
#
fmov.l &rm_mode*0x10,%fpcr # set RM and ext
mov.l (%a0),L_SCR2(%a6) # save exponent for sign check
@@ -13658,7 +13658,7 @@ A3_cont:
sub.w &0x3fff,%d0 # strip off bias
fadd.w %d0,%fp0 # add in exp
fsub.s FONE(%pc),%fp0 # subtract off 1.0
- fbge.w pos_res # if pos, branch
+ fbge.w pos_res # if pos, branch
fmul.x PLOG2UP1(%pc),%fp0 # if neg, mul by LOG2UP1
fmov.l %fp0,%d6 # put ILOG in d6 as a lword
bra.b A4_str # go move out ILOG
@@ -13668,14 +13668,14 @@ pos_res:
# A4. Clr INEX bit.
-# The operation in A3 above may have set INEX2.
+# The operation in A3 above may have set INEX2.
A4_str:
fmov.l &0,%fpsr # zero all of fpsr - nothing needed
# A5. Set ICTR = 0;
-# ICTR is a flag used in A13. It must be set before the
+# ICTR is a flag used in A13. It must be set before the
# loop entry A6. The lower word of d5 is used for ICTR.
clr.w %d5 # clear ICTR
@@ -13841,21 +13841,21 @@ e_next2:
bne.b e_loop2 # if not, loop
# A8. Clr INEX; Force RZ.
-# The operation in A3 above may have set INEX2.
+# The operation in A3 above may have set INEX2.
# RZ mode is forced for the scaling operation to insure
-# only one rounding error. The grs bits are collected in
+# only one rounding error. The grs bits are collected in
# the INEX flag for use in A10.
#
# Register usage:
# Input/Output
- fmov.l &0,%fpsr # clr INEX
+ fmov.l &0,%fpsr # clr INEX
fmov.l &rz_mode*0x10,%fpcr # set RZ rounding mode
# A9. Scale X -> Y.
# The mantissa is scaled to the desired number of significant
# digits. The excess digits are collected in INEX2. If mul,
-# Check d2 for excess 10 exponential value. If not zero,
+# Check d2 for excess 10 exponential value. If not zero,
# the iscale value would have caused the pwrten calculation
# to overflow. Only a negative iscale can cause this, so
# multiply by 10^(d2), which is now only allowed to be 24,
@@ -13986,7 +13986,7 @@ A10_st:
A11_st:
mov.l USER_FPCR(%a6),L_SCR1(%a6) # save it for later
- and.l &0x00000030,USER_FPCR(%a6) # set size to ext,
+ and.l &0x00000030,USER_FPCR(%a6) # set size to ext,
# ;block exceptions
@@ -14022,7 +14022,7 @@ A12_st:
lea.l FP_SCR1(%a6),%a0 # a0 is ptr to FP_SCR1(a6)
fmov.x %fp0,(%a0) # move Y to memory at FP_SCR1(a6)
tst.l L_SCR2(%a6) # test sign of original operand
- bge.b do_fint12 # if pos, use Y
+ bge.b do_fint12 # if pos, use Y
or.l &0x80000000,(%a0) # if neg, use -Y
do_fint12:
mov.l USER_FPSR(%a6),-(%sp)
@@ -14118,7 +14118,7 @@ A13_con:
subq.l &1,%d6 # subtract 1 from ILOG
mov.w &1,%d5 # set ICTR
fmov.l &rm_mode*0x10,%fpcr # set rmode to RM
- fmul.s FTEN(%pc),%fp2 # compute 10^LEN
+ fmul.s FTEN(%pc),%fp2 # compute 10^LEN
bra.w A6_str # return to A6 and recompute YINT
test_2:
fmul.s FTEN(%pc),%fp2 # compute 10^LEN
@@ -14134,7 +14134,7 @@ fix_ex:
fmov.l &rm_mode*0x10,%fpcr # set rmode to RM
bra.w A6_str # return to A6 and recompute YINT
#
-# Since ICTR <> 0, we have already been through one adjustment,
+# Since ICTR <> 0, we have already been through one adjustment,
# and shouldn't have another; this is to check if abs(YINT) = 10^LEN
# 10^LEN is again computed using whatever table is in a1 since the
# value calculated cannot be inexact.
@@ -14160,11 +14160,11 @@ z_next:
fmul.s FTEN(%pc),%fp2 # if LEN++, the get 10^^LEN
# A14. Convert the mantissa to bcd.
-# The binstr routine is used to convert the LEN digit
+# The binstr routine is used to convert the LEN digit
# mantissa to bcd in memory. The input to binstr is
# to be a fraction; i.e. (mantissa)/10^LEN and adjusted
# such that the decimal point is to the left of bit 63.
-# The bcd digits are stored in the correct position in
+# The bcd digits are stored in the correct position in
# the final string area in memory.
#
#
@@ -14207,7 +14207,7 @@ A14_st:
bgt.b no_sft # if so, don't shift
neg.l %d0 # make exp positive
m_loop:
- lsr.l &1,%d2 # shift d2:d3 right, add 0s
+ lsr.l &1,%d2 # shift d2:d3 right, add 0s
roxr.l &1,%d3 # the number of places
dbf.w %d0,m_loop # given in d0
no_sft:
@@ -14232,9 +14232,9 @@ zer_m:
#
# Digits are stored in L_SCR1(a6) on return from BINDEC as:
#
-# 32 16 15 0
+# 32 16 15 0
# -----------------------------------------
-# | 0 | e3 | e2 | e1 | e4 | X | X | X |
+# | 0 | e3 | e2 | e1 | e4 | X | X | X |
# -----------------------------------------
#
# And are moved into their proper places in FP_SCR0. If digit e4
@@ -14297,7 +14297,7 @@ convrt:
sub.w &0x3ffd,%d0 # subtract off bias
neg.w %d0 # make exp positive
x_loop:
- lsr.l &1,%d2 # shift d2:d3 right
+ lsr.l &1,%d2 # shift d2:d3 right
roxr.l &1,%d3 # the number of places
dbf.w %d0,x_loop # given in d0
x_loop_fin:
@@ -14308,12 +14308,12 @@ x_loop_fin:
mov.l &4,%d0 # put 4 in d0 for binstr call
lea.l L_SCR1(%a6),%a0 # a0 is ptr to L_SCR1 for exp digits
bsr binstr # call binstr to convert exp
- mov.l L_SCR1(%a6),%d0 # load L_SCR1 lword to d0
+ mov.l L_SCR1(%a6),%d0 # load L_SCR1 lword to d0
mov.l &12,%d1 # use d1 for shift count
lsr.l %d1,%d0 # shift d0 right by 12
bfins %d0,FP_SCR0(%a6){&4:&12} # put e3:e2:e1 in FP_SCR0
lsr.l %d1,%d0 # shift d0 right by 12
- bfins %d0,FP_SCR0(%a6){&16:&4} # put e4 in FP_SCR0
+ bfins %d0,FP_SCR0(%a6){&16:&4} # put e4 in FP_SCR0
tst.b %d0 # check if e4 is zero
beq.b A16_st # if zero, skip rest
or.l &opaop_mask,USER_FPSR(%a6) # set OPERR & AIOP in USER_FPSR
@@ -14344,14 +14344,14 @@ x_loop_fin:
A16_st:
clr.l %d0 # clr d0 for collection of signs
- and.b &0x0f,FP_SCR0(%a6) # clear first nibble of FP_SCR0
+ and.b &0x0f,FP_SCR0(%a6) # clear first nibble of FP_SCR0
tst.l L_SCR2(%a6) # check sign of original mantissa
bge.b mant_p # if pos, don't set SM
mov.l &2,%d0 # move 2 in to d0 for SM
mant_p:
tst.l %d6 # check sign of ILOG
bge.b wr_sgn # if pos, don't set SE
- addq.l &1,%d0 # set bit 0 in d0 for SE
+ addq.l &1,%d0 # set bit 0 in d0 for SE
wr_sgn:
bfins %d0,FP_SCR0(%a6){&0:&2} # insert SM and SE into FP_SCR0
@@ -14417,8 +14417,8 @@ PTENRM:
# d2:d3 = 64-bit binary integer #
# d0 = desired length (LEN) #
# a0 = pointer to start in memory for bcd characters #
-# (This pointer must point to byte 4 of the first #
-# lword of the packed decimal memory string.) #
+# (This pointer must point to byte 4 of the first #
+# lword of the packed decimal memory string.) #
# #
# OUTPUT ************************************************************** #
# a0 = pointer to LEN bcd digits representing the 64-bit integer. #
@@ -14558,14 +14558,14 @@ end_bstr:
# #
# INPUT *************************************************************** #
# None #
-# #
+# #
# OUTPUT ************************************************************** #
# None #
# #
# ALGORITHM *********************************************************** #
-# Flow jumps here when an FP data fetch call gets an error #
+# Flow jumps here when an FP data fetch call gets an error #
# result. This means the operating system wants an access error frame #
-# made out of the current exception stack frame. #
+# made out of the current exception stack frame. #
# So, we first call restore() which makes sure that any updated #
# -(an)+ register gets returned to its pre-exception value and then #
# we change the stack to an access error stack frame. #
@@ -14735,7 +14735,7 @@ ri_a7:
bne.b ri_a7_done # supervisor
movc %usp,%a0 # restore USP
sub.l %d0,%a0
- movc %a0,%usp
+ movc %a0,%usp
ri_a7_done:
rts
diff -puN arch/m68k/ifpsp060/TEST.DOC~m68k-superfluous-whitespace arch/m68k/ifpsp060/TEST.DOC
--- 25/arch/m68k/ifpsp060/TEST.DOC~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/ifpsp060/TEST.DOC Thu Apr 22 13:43:13 2004
@@ -5,10 +5,10 @@ M68060 Software Package
Production Release P1.00 -- October 10, 1994
M68060 Software Package Copyright © 1993, 1994 Motorola Inc. All rights reserved.
-
+
THE SOFTWARE is provided on an "AS IS" basis and without warranty.
To the maximum extent permitted by applicable law,
-MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
+MOTOROLA DISCLAIMS ALL WARRANTIES WHETHER EXPRESS OR IMPLIED,
INCLUDING IMPLIED WARRANTIES OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE
and any warranty against infringement with regard to the SOFTWARE
(INCLUDING ANY MODIFIED VERSIONS THEREOF) and any accompanying written materials.
@@ -56,7 +56,7 @@ Release file structure:
-----------------------
(top of module)
- -----------------
+ -----------------
| | - 128 byte-sized section
(1) | Call-Out | - 4 bytes per entry (user fills these in)
| |
@@ -74,8 +74,8 @@ Release file structure:
The first section of this module is the "Call-out" section. This section
is NOT INCLUDED in {i,f}test.sa (an example "Call-out" section is provided at
the end of this file). The purpose of this section is to allow the test
-routines to reference external printing functions that must be provided
-by the host operating system. This section MUST be exactly 128 bytes in
+routines to reference external printing functions that must be provided
+by the host operating system. This section MUST be exactly 128 bytes in
size. There are 32 fields, each 4 bytes in size. Each field corresponds
to a function required by the test packages (these functions and their
location are listed in "68060{ISP,FPSP}-TEST call-outs" below). Each field
@@ -152,7 +152,7 @@ main fp test: tests (1) unimp effective
(2) unsupported data type exceptions
(3) non-maskable overflow/underflow exceptions
-FP unimplemented: tests FP unimplemented exception. this one is
+FP unimplemented: tests FP unimplemented exception. this one is
separate from the previous tests for systems that don't
want FP unimplemented instructions.
@@ -194,7 +194,7 @@ _print_num:
# beginning of "Call-out" section; provided by integrator.
# MUST be 128 bytes long.
_060FPSP_TEST:
- long _print_str - _060FPSP_TEST
+ long _print_str - _060FPSP_TEST
long _print_num - _060FPSP_TEST
space 120
diff -puN arch/m68k/Kconfig~m68k-superfluous-whitespace arch/m68k/Kconfig
--- 25/arch/m68k/Kconfig~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/Kconfig Thu Apr 22 13:43:13 2004
@@ -76,9 +76,9 @@ config SUN3
select MMU_SUN3 if MMU
help
This option enables support for the Sun 3 series of workstations
- (3/50, 3/60, 3/1xx, 3/2xx systems). Enabling this option requires
- that all other hardware types must be disabled, as Sun 3 kernels
- are incompatible with all other m68k targets (including Sun 3x!).
+ (3/50, 3/60, 3/1xx, 3/2xx systems). Enabling this option requires
+ that all other hardware types must be disabled, as Sun 3 kernels
+ are incompatible with all other m68k targets (including Sun 3x!).
If you don't want to compile a kernel exclusively for a Sun 3, say N.
@@ -687,7 +687,7 @@ config DEBUG_INFO
debugging info resulting in a larger kernel image.
Say Y here only if you plan to use gdb to debug the kernel.
If you don't debug the kernel, you can say N.
-
+
endmenu
source "security/Kconfig"
diff -puN arch/m68k/kernel/bios32.c~m68k-superfluous-whitespace arch/m68k/kernel/bios32.c
--- 25/arch/m68k/kernel/bios32.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/kernel/bios32.c Thu Apr 22 13:43:13 2004
@@ -46,7 +46,7 @@
#define ALIGN(val,align) (((val) + ((align) - 1)) & ~((align) - 1))
-#define MAX(val1, val2) (((val1) > (val2)) ? val1 : val2)
+#define MAX(val1, val2) (((val1) > (val2)) ? val1 : val2)
/*
* Offsets relative to the I/O and memory base addresses from where resources
diff -puN arch/m68k/kernel/entry.S~m68k-superfluous-whitespace arch/m68k/kernel/entry.S
--- 25/arch/m68k/kernel/entry.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/kernel/entry.S Thu Apr 22 13:43:13 2004
@@ -55,7 +55,7 @@
ENTRY(buserr)
SAVE_ALL_INT
GET_CURRENT(%d0)
- movel %sp,%sp@- | stack frame pointer argument
+ movel %sp,%sp@- | stack frame pointer argument
bsrl buserr_c
addql #4,%sp
jra ret_from_exception
@@ -63,7 +63,7 @@ ENTRY(buserr)
ENTRY(trap)
SAVE_ALL_INT
GET_CURRENT(%d0)
- movel %sp,%sp@- | stack frame pointer argument
+ movel %sp,%sp@- | stack frame pointer argument
bsrl trap_c
addql #4,%sp
jra ret_from_exception
@@ -99,18 +99,18 @@ do_trace:
jbsr syscall_trace
ret_from_signal:
- RESTORE_SWITCH_STACK
+ RESTORE_SWITCH_STACK
addql #4,%sp
-/* on 68040 complete pending writebacks if any */
+/* on 68040 complete pending writebacks if any */
#ifdef CONFIG_M68040
- bfextu %sp@(PT_VECTOR){#0,#4},%d0
+ bfextu %sp@(PT_VECTOR){#0,#4},%d0
subql #7,%d0 | bus error frame ?
jbne 1f
movel %sp,%sp@-
jbsr berr_040cleanup
addql #4,%sp
-1:
-#endif
+1:
+#endif
jra ret_from_exception
ENTRY(system_call)
@@ -229,18 +229,18 @@ inthandler:
bfextu %sp@(PT_VECTOR){#4,#10},%d0
movel %sp,%sp@-
- movel %d0,%sp@- | put vector # on stack
+ movel %d0,%sp@- | put vector # on stack
#if defined(MACH_Q40_ONLY) && defined(CONFIG_BLK_DEV_FD)
btstb #4,0xff000000 | Q40 floppy needs very special treatment ...
jbeq 1f
- btstb #3,0xff000004
+ btstb #3,0xff000004
jbeq 1f
jbsr floppy_hardint
jbra 3f
1:
-#endif
+#endif
jbsr process_int | process the IRQ
-3: addql #8,%sp | pop parameters off stack
+3: addql #8,%sp | pop parameters off stack
ret_from_interrupt:
subqb #1,%curptr@(TASK_INFO+TINFO_PREEMPT+2)
@@ -266,7 +266,7 @@ bad_interrupt:
rte
ENTRY(sys_fork)
- SAVE_SWITCH_STACK
+ SAVE_SWITCH_STACK
pea %sp@(SWITCH_STACK_SIZE)
jbsr m68k_fork
addql #4,%sp
@@ -282,7 +282,7 @@ ENTRY(sys_clone)
rts
ENTRY(sys_vfork)
- SAVE_SWITCH_STACK
+ SAVE_SWITCH_STACK
pea %sp@(SWITCH_STACK_SIZE)
jbsr m68k_vfork
addql #4,%sp
@@ -397,7 +397,7 @@ resume:
#if !defined(CPU_M68060_ONLY)
1: tstb %a1@(TASK_THREAD+THREAD_FPSTATE)
jeq 3f
-#endif
+#endif
2: fmovemx %a1@(TASK_THREAD+THREAD_FPREG),%fp0-%fp7
fmoveml %a1@(TASK_THREAD+THREAD_FPCNTL),%fpcr/%fpsr/%fpiar
3: frestore %a1@(TASK_THREAD+THREAD_FPSTATE)
@@ -554,7 +554,7 @@ sys_call_table:
.long sys_adjtimex
.long sys_mprotect /* 125 */
.long sys_sigprocmask
- .long sys_ni_syscall /* old "create_module" */
+ .long sys_ni_syscall /* old "create_module" */
.long sys_init_module
.long sys_delete_module
.long sys_ni_syscall /* 130 - old "get_kernel_syms" */
diff -puN arch/m68k/kernel/head.S~m68k-superfluous-whitespace arch/m68k/kernel/head.S
--- 25/arch/m68k/kernel/head.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/kernel/head.S Thu Apr 22 13:43:13 2004
@@ -19,7 +19,7 @@
** ++ Bjoern & Roman: ATARI-68040 support for the Medusa
** 95/11/18 Richard Hirst: Added MVME166 support
** 96/04/26 Guenther Kelleter: fixed identity mapping for Falcon with
-** Magnum- and FX-alternate ram
+** Magnum- and FX-alternate ram
** 98/04/25 Phil Blundell: added HP300 support
** 1998/08/30 David Kilzer: Added support for font_desc structures
** for linux-2.1.115
@@ -67,7 +67,7 @@
* for the kernel.
* There are new subroutines and data structures to make MMU
* support cleaner and easier to understand.
- * First, you will find a routine call "mmu_map" which maps
+ * First, you will find a routine call "mmu_map" which maps
* a logical to a physical region for some length given a cache
* type on behalf of the caller. This routine makes writing the
* actual per-machine specific code very simple.
@@ -299,7 +299,7 @@
* For the head.S console, there are three supported fonts, 6x11, 8x16 and 8x8.
* The 8x8 font is harder to read but fits more on the screen.
*/
-#define FONT_8x8 /* default */
+#define FONT_8x8 /* default */
/* #define FONT_8x16 */ /* 2nd choice */
/* #define FONT_6x11 */ /* 3rd choice */
diff -puN arch/m68k/kernel/ptrace.c~m68k-superfluous-whitespace arch/m68k/kernel/ptrace.c
--- 25/arch/m68k/kernel/ptrace.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/kernel/ptrace.c Thu Apr 22 13:43:13 2004
@@ -156,7 +156,7 @@ asmlinkage int sys_ptrace(long request,
switch (request) {
/* when I and D space are separate, these will need to be fixed. */
- case PTRACE_PEEKTEXT: /* read word at location addr. */
+ case PTRACE_PEEKTEXT: /* read word at location addr. */
case PTRACE_PEEKDATA: {
unsigned long tmp;
int copied;
@@ -172,12 +172,12 @@ asmlinkage int sys_ptrace(long request,
/* read the word at location addr in the USER area. */
case PTRACE_PEEKUSR: {
unsigned long tmp;
-
+
ret = -EIO;
if ((addr & 3) || addr < 0 ||
addr > sizeof(struct user) - 3)
break;
-
+
tmp = 0; /* Default return condition */
addr = addr >> 2; /* temporary hack. */
ret = -EIO;
@@ -217,7 +217,7 @@ asmlinkage int sys_ptrace(long request,
break;
addr = addr >> 2; /* temporary hack. */
-
+
if (addr == PT_SR) {
data &= SR_MASK;
data <<= 16;
@@ -269,8 +269,8 @@ asmlinkage int sys_ptrace(long request,
}
/*
- * make the child exit. Best I can do is send it a sigkill.
- * perhaps it should be put in the status that it wants to
+ * make the child exit. Best I can do is send it a sigkill.
+ * perhaps it should be put in the status that it wants to
* exit.
*/
case PTRACE_KILL: {
@@ -311,7 +311,7 @@ asmlinkage int sys_ptrace(long request,
break;
case PTRACE_GETREGS: { /* Get all gp regs from the child. */
- int i;
+ int i;
unsigned long tmp;
for (i = 0; i < 19; i++) {
tmp = get_reg(child, i);
diff -puN arch/m68k/kernel/setup.c~m68k-superfluous-whitespace arch/m68k/kernel/setup.c
--- 25/arch/m68k/kernel/setup.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/kernel/setup.c Thu Apr 22 13:43:13 2004
@@ -84,7 +84,7 @@ void (*mach_reset)( void );
void (*mach_halt)( void );
void (*mach_power_off)( void );
long mach_max_dma_address = 0x00ffffff; /* default set to the lower 16MB */
-#if defined(CONFIG_AMIGA_FLOPPY) || defined(CONFIG_ATARI_FLOPPY)
+#if defined(CONFIG_AMIGA_FLOPPY) || defined(CONFIG_ATARI_FLOPPY)
void (*mach_floppy_setup) (char *, int *) __initdata = NULL;
#endif
#ifdef CONFIG_HEARTBEAT
@@ -142,7 +142,7 @@ static void __init m68k_parse_bootinfo(c
/* Already set up by head.S */
break;
- case BI_MEMCHUNK:
+ case BI_MEMCHUNK:
if (m68k_num_memory < NUM_MEMINFO) {
m68k_memory[m68k_num_memory].addr = data[0];
m68k_memory[m68k_num_memory].size = data[1];
@@ -235,7 +235,7 @@ void __init setup_arch(char **cmdline_p)
volatile int zero = 0;
asm __volatile__ ("frestore %0" : : "m" (zero));
}
-#endif
+#endif
init_mm.start_code = PAGE_OFFSET;
init_mm.end_code = (unsigned long) &_etext;
@@ -295,28 +295,28 @@ void __init setup_arch(char **cmdline_p)
#endif
#ifdef CONFIG_SUN3
case MACH_SUN3:
- config_sun3();
- break;
+ config_sun3();
+ break;
#endif
#ifdef CONFIG_APOLLO
case MACH_APOLLO:
- config_apollo();
- break;
+ config_apollo();
+ break;
#endif
#ifdef CONFIG_MVME147
case MACH_MVME147:
- config_mvme147();
- break;
+ config_mvme147();
+ break;
#endif
#ifdef CONFIG_MVME16x
case MACH_MVME16x:
- config_mvme16x();
- break;
+ config_mvme16x();
+ break;
#endif
#ifdef CONFIG_BVME6000
case MACH_BVME6000:
- config_bvme6000();
- break;
+ config_bvme6000();
+ break;
#endif
#ifdef CONFIG_HP300
case MACH_HP300:
@@ -383,11 +383,11 @@ void __init setup_arch(char **cmdline_p)
/* set ISA defs early as possible */
#if defined(CONFIG_ISA) && defined(MULTI_ISA)
-#if defined(CONFIG_Q40)
+#if defined(CONFIG_Q40)
if (MACH_IS_Q40) {
isa_type = Q40_ISA;
isa_sex = 0;
- }
+ }
#elif defined(CONFIG_GG2)
if (MACH_IS_AMIGA && AMIGAHW_PRESENT(GG2_ISA)){
isa_type = GG2_ISA;
diff -puN arch/m68k/kernel/signal.c~m68k-superfluous-whitespace arch/m68k/kernel/signal.c
--- 25/arch/m68k/kernel/signal.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/kernel/signal.c Thu Apr 22 13:43:13 2004
@@ -121,7 +121,7 @@ do_rt_sigsuspend(struct pt_regs *regs)
}
}
-asmlinkage int
+asmlinkage int
sys_sigaction(int sig, const struct old_sigaction *act,
struct old_sigaction *oact)
{
@@ -329,7 +329,7 @@ restore_sigcontext(struct pt_regs *regs,
/* get previous context */
if (copy_from_user(&context, usc, sizeof(context)))
goto badframe;
-
+
/* restore passed registers */
regs->d1 = context.sc_d1;
regs->a0 = context.sc_a0;
@@ -521,7 +521,7 @@ asmlinkage int do_sigreturn(unsigned lon
sigdelsetmask(&set, ~_BLOCKABLE);
current->blocked = set;
recalc_sigpending();
-
+
if (restore_sigcontext(regs, &frame->sc, frame + 1, &d0))
goto badframe;
return d0;
@@ -548,7 +548,7 @@ asmlinkage int do_rt_sigreturn(unsigned
sigdelsetmask(&set, ~_BLOCKABLE);
current->blocked = set;
recalc_sigpending();
-
+
if (rt_restore_ucontext(regs, sw, &frame->uc, &d0))
goto badframe;
return d0;
@@ -1091,7 +1091,7 @@ asmlinkage int do_signal(sigset_t *oldse
current->state = TASK_STOPPED;
current->exit_code = signr;
sighand = current->parent->sighand;
- if (sighand && !(sighand->action[SIGCHLD-1].sa.sa_flags
+ if (sighand && !(sighand->action[SIGCHLD-1].sa.sa_flags
& SA_NOCLDSTOP))
notify_parent(current, SIGCHLD);
schedule();
diff -puN arch/m68k/kernel/sun3-head.S~m68k-superfluous-whitespace arch/m68k/kernel/sun3-head.S
--- 25/arch/m68k/kernel/sun3-head.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/kernel/sun3-head.S Thu Apr 22 13:43:13 2004
@@ -9,7 +9,7 @@ PSL_HIGHIPL = 0x2700
NBSG = 0x20000
ICACHE_ONLY = 0x00000009
CACHES_OFF = 0x00000008 | actually a clear and disable --m
-#define MAS_STACK INT_STACK
+#define MAS_STACK INT_STACK
ROOT_TABLE_SIZE = 128
PAGESIZE = 8192
SUN3_INVALID_PMEG = 255
@@ -35,9 +35,9 @@ ENTRY(_start)
/* Firstly, disable interrupts and set up function codes. */
movew #PSL_HIGHIPL, %sr
- moveq #FC_CONTROL, %d0
- movec %d0, %sfc
- movec %d0, %dfc
+ moveq #FC_CONTROL, %d0
+ movec %d0, %sfc
+ movec %d0, %dfc
/* Make sure we're in context zero. */
moveq #0, %d0
@@ -45,9 +45,9 @@ ENTRY(_start)
/* map everything the bootloader left us into high memory, clean up the
excess later */
- lea (AC_SEGMAP+0),%a0
- lea (AC_SEGMAP+KERNBASE),%a1
-1:
+ lea (AC_SEGMAP+0),%a0
+ lea (AC_SEGMAP+KERNBASE),%a1
+1:
movsb %a0@, %d1
movsb %d1, %a1@
cmpib #SUN3_INVALID_PMEG, %d1
@@ -55,13 +55,13 @@ ENTRY(_start)
addl #NBSG,%a0
addl #NBSG,%a1
jmp 1b
-
-2:
-
+
+2:
+
/* Disable caches and jump to high code. */
moveq #ICACHE_ONLY,%d0 | Cache disabled until we're ready to enable it
movc %d0, %cacr | is this the right value? (yes --m)
- jmp 1f:l
+ jmp 1f:l
/* Following code executes at high addresses (0xE000xxx). */
1: lea init_task,%curptr | get initial thread...
@@ -76,7 +76,7 @@ ENTRY(_start)
movel %a0@, %a1@
addl #4, %a1
dbf %d0, 1b
-
+
/* Point MSP at an invalid page to trap if it's used. --m */
movl #(PAGESIZE),%d0
movc %d0,%msp
@@ -86,9 +86,9 @@ ENTRY(_start)
jbsr sun3_init
jbsr base_trap_init
-
+
jbsr start_kernel
- trap #15
+ trap #15
.data
.even
diff -puN arch/m68k/kernel/sys_m68k.c~m68k-superfluous-whitespace arch/m68k/kernel/sys_m68k.c
--- 25/arch/m68k/kernel/sys_m68k.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/kernel/sys_m68k.c Thu Apr 22 13:43:13 2004
@@ -203,10 +203,10 @@ asmlinkage int sys_ipc (uint call, int f
default:
return -ENOSYS;
}
- if (call <= MSGCTL)
+ if (call <= MSGCTL)
switch (call) {
case MSGSND:
- return sys_msgsnd (first, (struct msgbuf *) ptr,
+ return sys_msgsnd (first, (struct msgbuf *) ptr,
second, third);
case MSGRCV:
switch (version) {
@@ -234,7 +234,7 @@ asmlinkage int sys_ipc (uint call, int f
default:
return -ENOSYS;
}
- if (call <= SHMCTL)
+ if (call <= SHMCTL)
switch (call) {
case SHMAT:
switch (version) {
@@ -247,7 +247,7 @@ asmlinkage int sys_ipc (uint call, int f
return put_user (raddr, (ulong *) third);
}
}
- case SHMDT:
+ case SHMDT:
return sys_shmdt ((char *)ptr);
case SHMGET:
return sys_shmget (first, second, third);
@@ -442,7 +442,7 @@ cache_flush_060 (unsigned long addr, int
unsigned long paddr, i;
/*
- * 68060 manual says:
+ * 68060 manual says:
* cpush %dc : flush DC, remains valid (with our %cacr setup)
* cpush %ic : invalidate IC
* cpush %bc : flush DC + invalidate IC
diff -puN arch/m68k/kernel/traps.c~m68k-superfluous-whitespace arch/m68k/kernel/traps.c
--- 25/arch/m68k/kernel/traps.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/kernel/traps.c Thu Apr 22 13:43:13 2004
@@ -116,7 +116,7 @@ void __init base_trap_init(void)
__asm__ volatile ("movec %%vbr, %0" : "=r" ((void*)sun3x_prom_vbr));
}
-
+
/* setup the exception vector table */
__asm__ volatile ("movec %0,%%vbr" : : "r" ((void*)vectors));
@@ -352,7 +352,7 @@ static inline unsigned long probe040(int
asm volatile (".chip 68040; movec %%mmusr,%0; .chip 68k" : "=r" (mmusr));
- set_fs(old_fs);
+ set_fs(old_fs);
return mmusr;
}
@@ -379,8 +379,8 @@ static inline int do_040writeback1(unsig
}
/* set_fs can not be moved, otherwise put_user() may oops */
- set_fs(old_fs);
-
+ set_fs(old_fs);
+
#ifdef DEBUG
printk("do_040writeback1, res=%d\n",res);
@@ -390,7 +390,7 @@ static inline int do_040writeback1(unsig
}
/* after an exception in a writeback the stack frame corresponding
- * to that exception is discarded, set a few bits in the old frame
+ * to that exception is discarded, set a few bits in the old frame
* to simulate what it should look like
*/
static inline void fix_xframe040(struct frame *fp, unsigned long wba, unsigned short wbs)
@@ -415,7 +415,7 @@ static inline void do_040writebacks(stru
fp->un.fmt7.wb2d);
if (res)
fix_xframe040(fp, fp->un.fmt7.wb2a, fp->un.fmt7.wb2s);
- else
+ else
fp->un.fmt7.wb2s = 0;
}
@@ -461,9 +461,9 @@ static inline void access_error040(struc
#ifdef DEBUG
printk("ssw=%#x, fa=%#lx\n", ssw, fp->un.fmt7.faddr);
- printk("wb1s=%#x, wb2s=%#x, wb3s=%#x\n", fp->un.fmt7.wb1s,
+ printk("wb1s=%#x, wb2s=%#x, wb3s=%#x\n", fp->un.fmt7.wb1s,
fp->un.fmt7.wb2s, fp->un.fmt7.wb3s);
- printk ("wb2a=%lx, wb3a=%lx, wb2d=%lx, wb3d=%lx\n",
+ printk ("wb2a=%lx, wb3a=%lx, wb2d=%lx, wb3d=%lx\n",
fp->un.fmt7.wb2a, fp->un.fmt7.wb3a,
fp->un.fmt7.wb2d, fp->un.fmt7.wb3d);
#endif
@@ -491,7 +491,7 @@ static inline void access_error040(struc
errorcode = 0;
}
- /* despite what documentation seems to say, RMW
+ /* despite what documentation seems to say, RMW
* accesses have always both the LK and RW bits set */
if (!(ssw & RW_040) || (ssw & LK_040))
errorcode |= 2;
@@ -547,7 +547,7 @@ static inline void bus_error030 (struct
fp->ptregs.format == 0xa ? fp->ptregs.pc + 2 : fp->un.fmtb.baddr - 2
:
fp->ptregs.format == 0xa ? fp->ptregs.pc + 4 : fp->un.fmtb.baddr);
- if (ssw & DF)
+ if (ssw & DF)
printk ("Data %s fault at %#010lx in %s (pc=%#lx)\n",
ssw & RW ? "read" : "write",
fp->un.fmtb.daddr,
@@ -559,7 +559,7 @@ static inline void bus_error030 (struct
* the testing for a bad kernel-space access (demand-mapping applies
* to kernel accesses too).
*/
-
+
if ((ssw & DF)
&& (buserr_type & (SUN3_BUSERR_PROTERR | SUN3_BUSERR_INVALID))) {
if (mmu_emu_handle_fault (fp->un.fmtb.daddr, ssw & RW, 0))
@@ -659,7 +659,7 @@ static inline void bus_error030 (struct
printk ("protection fault on insn access (segv).\n");
#endif
force_sig (SIGSEGV, current);
- }
+ }
}
#else
#if defined(CPU_M68020_OR_M68030)
@@ -1035,7 +1035,7 @@ void bad_super_trap (struct frame *fp)
fp->ptregs.format);
else
printk ("*** Exception %d *** FORMAT=%X\n",
- (fp->ptregs.vector) >> 2,
+ (fp->ptregs.vector) >> 2,
fp->ptregs.format);
if (fp->ptregs.vector >> 2 == VEC_ADDRERR && CPU_IS_020_OR_030) {
unsigned short ssw = fp->un.fmtb.ssw;
diff -puN arch/m68k/kernel/vmlinux-std.lds~m68k-superfluous-whitespace arch/m68k/kernel/vmlinux-std.lds
--- 25/arch/m68k/kernel/vmlinux-std.lds~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/kernel/vmlinux-std.lds Thu Apr 22 13:43:13 2004
@@ -41,7 +41,7 @@ SECTIONS
/* will be freed after init */
. = ALIGN(4096); /* Init code and data */
__init_begin = .;
- .init.text : {
+ .init.text : {
_sinittext = .;
*(.init.text)
_einittext = .;
@@ -56,12 +56,12 @@ SECTIONS
__stop___param = .;
__initcall_start = .;
.initcall.init : {
- *(.initcall1.init)
- *(.initcall2.init)
- *(.initcall3.init)
- *(.initcall4.init)
- *(.initcall5.init)
- *(.initcall6.init)
+ *(.initcall1.init)
+ *(.initcall2.init)
+ *(.initcall3.init)
+ *(.initcall4.init)
+ *(.initcall5.init)
+ *(.initcall6.init)
*(.initcall7.init)
}
__initcall_end = .;
diff -puN arch/m68k/kernel/vmlinux-sun3.lds~m68k-superfluous-whitespace arch/m68k/kernel/vmlinux-sun3.lds
--- 25/arch/m68k/kernel/vmlinux-sun3.lds~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/kernel/vmlinux-sun3.lds Thu Apr 22 13:43:13 2004
@@ -24,10 +24,10 @@ SECTIONS
.data : { /* Data */
*(.data)
CONSTRUCTORS
- . = ALIGN(16); /* Exception table */
- __start___ex_table = .;
- *(__ex_table)
- __stop___ex_table = .;
+ . = ALIGN(16); /* Exception table */
+ __start___ex_table = .;
+ *(__ex_table)
+ __stop___ex_table = .;
}
/* End of data goes *here* so that freeing init code works properly. */
_edata = .;
@@ -35,12 +35,12 @@ SECTIONS
/* will be freed after init */
. = ALIGN(8192); /* Init code and data */
__init_begin = .;
- .init.text : {
+ .init.text : {
_sinittext = .;
*(.init.text)
_einittext = .;
}
- .init.data : { *(.init.data) }
+ .init.data : { *(.init.data) }
. = ALIGN(16);
__setup_start = .;
.init.setup : { *(.init.setup) }
@@ -50,12 +50,12 @@ __init_begin = .;
__stop___param = .;
__initcall_start = .;
.initcall.init : {
- *(.initcall1.init)
- *(.initcall2.init)
- *(.initcall3.init)
- *(.initcall4.init)
- *(.initcall5.init)
- *(.initcall6.init)
+ *(.initcall1.init)
+ *(.initcall2.init)
+ *(.initcall3.init)
+ *(.initcall4.init)
+ *(.initcall5.init)
+ *(.initcall6.init)
*(.initcall7.init)
}
__initcall_end = .;
@@ -70,7 +70,7 @@ __init_begin = .;
. = ALIGN(8192);
__init_end = .;
.init.task : { *(init_task) }
-
+
.bss : { *(.bss) } /* BSS */
@@ -84,7 +84,7 @@ __init_begin = .;
}
.crap : {
- /* Stabs debugging sections. */
+ /* Stabs debugging sections. */
*(.stab)
*(.stabstr)
*(.stab.excl)
diff -puN arch/m68k/lib/ashldi3.c~m68k-superfluous-whitespace arch/m68k/lib/ashldi3.c
--- 25/arch/m68k/lib/ashldi3.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/lib/ashldi3.c Thu Apr 22 13:43:13 2004
@@ -20,7 +20,7 @@ Boston, MA 02111-1307, USA. */
#define BITS_PER_UNIT 8
-typedef int SItype __attribute__ ((mode (SI)));
+typedef int SItype __attribute__ ((mode (SI)));
typedef unsigned int USItype __attribute__ ((mode (SI)));
typedef int DItype __attribute__ ((mode (DI)));
typedef int word_type __attribute__ ((mode (__word__)));
diff -puN arch/m68k/lib/ashrdi3.c~m68k-superfluous-whitespace arch/m68k/lib/ashrdi3.c
--- 25/arch/m68k/lib/ashrdi3.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/lib/ashrdi3.c Thu Apr 22 13:43:13 2004
@@ -20,7 +20,7 @@ Boston, MA 02111-1307, USA. */
#define BITS_PER_UNIT 8
-typedef int SItype __attribute__ ((mode (SI)));
+typedef int SItype __attribute__ ((mode (SI)));
typedef unsigned int USItype __attribute__ ((mode (SI)));
typedef int DItype __attribute__ ((mode (DI)));
typedef int word_type __attribute__ ((mode (__word__)));
diff -puN arch/m68k/lib/lshrdi3.c~m68k-superfluous-whitespace arch/m68k/lib/lshrdi3.c
--- 25/arch/m68k/lib/lshrdi3.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/lib/lshrdi3.c Thu Apr 22 13:43:13 2004
@@ -20,7 +20,7 @@ Boston, MA 02111-1307, USA. */
#define BITS_PER_UNIT 8
-typedef int SItype __attribute__ ((mode (SI)));
+typedef int SItype __attribute__ ((mode (SI)));
typedef unsigned int USItype __attribute__ ((mode (SI)));
typedef int DItype __attribute__ ((mode (DI)));
typedef int word_type __attribute__ ((mode (__word__)));
diff -puN arch/m68k/lib/muldi3.c~m68k-superfluous-whitespace arch/m68k/lib/muldi3.c
--- 25/arch/m68k/lib/muldi3.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/lib/muldi3.c Thu Apr 22 13:43:13 2004
@@ -1,4 +1,4 @@
-/* muldi3.c extracted from gcc-2.7.2.3/libgcc2.c and
+/* muldi3.c extracted from gcc-2.7.2.3/libgcc2.c and
gcc-2.7.2.3/longlong.h which is: */
/* Copyright (C) 1989, 1992, 1993, 1994, 1995 Free Software Foundation, Inc.
@@ -33,7 +33,7 @@ Boston, MA 02111-1307, USA. */
umul_ppmm (__w.s.high, __w.s.low, u, v); \
__w.ll; })
-typedef int SItype __attribute__ ((mode (SI)));
+typedef int SItype __attribute__ ((mode (SI)));
typedef unsigned int USItype __attribute__ ((mode (SI)));
typedef int DItype __attribute__ ((mode (DI)));
typedef int word_type __attribute__ ((mode (__word__)));
diff -puN arch/m68k/mac/baboon.c~m68k-superfluous-whitespace arch/m68k/mac/baboon.c
--- 25/arch/m68k/mac/baboon.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/mac/baboon.c Thu Apr 22 13:43:13 2004
@@ -14,9 +14,9 @@
#include <linux/ide.h>
#include <asm/traps.h>
-#include <asm/bootinfo.h>
-#include <asm/macintosh.h>
-#include <asm/macints.h>
+#include <asm/bootinfo.h>
+#include <asm/macintosh.h>
+#include <asm/macints.h>
#include <asm/mac_baboon.h>
/* #define DEBUG_BABOON */
diff -puN arch/m68k/mac/bootparse.c~m68k-superfluous-whitespace arch/m68k/mac/bootparse.c
--- 25/arch/m68k/mac/bootparse.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/mac/bootparse.c Thu Apr 22 13:43:13 2004
@@ -9,114 +9,114 @@
/*
* Booter vars
*/
-
+
int boothowto;
int _boothowto;
-
+
/*
* Called early to parse the environment (passed to us from the booter)
* into a bootinfo struct. Will die as soon as we have our own booter
*/
#define atol(x) simple_strtoul(x,NULL,0)
-
+
void parse_booter(char *env)
{
- char *name;
- char *value;
+ char *name;
+ char *value;
#if 0
- while(0 && *env)
+ while(0 && *env)
#else
- while(*env)
+ while(*env)
#endif
- {
- name=env;
- value=name;
- while(*value!='='&&*value)
- value++;
- if(*value=='=')
- *value++=0;
- env=value;
- while(*env)
- env++;
- env++;
-#if 0
- if(strcmp(name,"VIDEO_ADDR")==0)
- mac_mch.videoaddr=atol(value);
- if(strcmp(name,"ROW_BYTES")==0)
- mac_mch.videorow=atol(value);
- if(strcmp(name,"SCREEN_DEPTH")==0)
- mac_mch.videodepth=atol(value);
- if(strcmp(name,"DIMENSIONS")==0)
- mac_mch.dimensions=atol(value);
-#endif
- if(strcmp(name,"BOOTTIME")==0)
- mac_bi_data.boottime=atol(value);
- if(strcmp(name,"GMTBIAS")==0)
- mac_bi_data.gmtbias=atol(value);
- if(strcmp(name,"BOOTERVER")==0)
- mac_bi_data.bootver=atol(value);
- if(strcmp(name,"MACOS_VIDEO")==0)
- mac_bi_data.videological=atol(value);
- if(strcmp(name,"MACOS_SCC")==0)
- mac_bi_data.sccbase=atol(value);
- if(strcmp(name,"MACHINEID")==0)
- mac_bi_data.id=atol(value);
- if(strcmp(name,"MEMSIZE")==0)
- mac_bi_data.memsize=atol(value);
- if(strcmp(name,"SERIAL_MODEM_FLAGS")==0)
- mac_bi_data.serialmf=atol(value);
- if(strcmp(name,"SERIAL_MODEM_HSKICLK")==0)
- mac_bi_data.serialhsk=atol(value);
- if(strcmp(name,"SERIAL_MODEM_GPICLK")==0)
- mac_bi_data.serialgpi=atol(value);
- if(strcmp(name,"SERIAL_PRINT_FLAGS")==0)
- mac_bi_data.printmf=atol(value);
- if(strcmp(name,"SERIAL_PRINT_HSKICLK")==0)
- mac_bi_data.printhsk=atol(value);
- if(strcmp(name,"SERIAL_PRINT_GPICLK")==0)
- mac_bi_data.printgpi=atol(value);
- if(strcmp(name,"PROCESSOR")==0)
- mac_bi_data.cpuid=atol(value);
- if(strcmp(name,"ROMBASE")==0)
- mac_bi_data.rombase=atol(value);
- if(strcmp(name,"TIMEDBRA")==0)
- mac_bi_data.timedbra=atol(value);
- if(strcmp(name,"ADBDELAY")==0)
- mac_bi_data.adbdelay=atol(value);
- }
+ {
+ name=env;
+ value=name;
+ while(*value!='='&&*value)
+ value++;
+ if(*value=='=')
+ *value++=0;
+ env=value;
+ while(*env)
+ env++;
+ env++;
+#if 0
+ if(strcmp(name,"VIDEO_ADDR")==0)
+ mac_mch.videoaddr=atol(value);
+ if(strcmp(name,"ROW_BYTES")==0)
+ mac_mch.videorow=atol(value);
+ if(strcmp(name,"SCREEN_DEPTH")==0)
+ mac_mch.videodepth=atol(value);
+ if(strcmp(name,"DIMENSIONS")==0)
+ mac_mch.dimensions=atol(value);
+#endif
+ if(strcmp(name,"BOOTTIME")==0)
+ mac_bi_data.boottime=atol(value);
+ if(strcmp(name,"GMTBIAS")==0)
+ mac_bi_data.gmtbias=atol(value);
+ if(strcmp(name,"BOOTERVER")==0)
+ mac_bi_data.bootver=atol(value);
+ if(strcmp(name,"MACOS_VIDEO")==0)
+ mac_bi_data.videological=atol(value);
+ if(strcmp(name,"MACOS_SCC")==0)
+ mac_bi_data.sccbase=atol(value);
+ if(strcmp(name,"MACHINEID")==0)
+ mac_bi_data.id=atol(value);
+ if(strcmp(name,"MEMSIZE")==0)
+ mac_bi_data.memsize=atol(value);
+ if(strcmp(name,"SERIAL_MODEM_FLAGS")==0)
+ mac_bi_data.serialmf=atol(value);
+ if(strcmp(name,"SERIAL_MODEM_HSKICLK")==0)
+ mac_bi_data.serialhsk=atol(value);
+ if(strcmp(name,"SERIAL_MODEM_GPICLK")==0)
+ mac_bi_data.serialgpi=atol(value);
+ if(strcmp(name,"SERIAL_PRINT_FLAGS")==0)
+ mac_bi_data.printmf=atol(value);
+ if(strcmp(name,"SERIAL_PRINT_HSKICLK")==0)
+ mac_bi_data.printhsk=atol(value);
+ if(strcmp(name,"SERIAL_PRINT_GPICLK")==0)
+ mac_bi_data.printgpi=atol(value);
+ if(strcmp(name,"PROCESSOR")==0)
+ mac_bi_data.cpuid=atol(value);
+ if(strcmp(name,"ROMBASE")==0)
+ mac_bi_data.rombase=atol(value);
+ if(strcmp(name,"TIMEDBRA")==0)
+ mac_bi_data.timedbra=atol(value);
+ if(strcmp(name,"ADBDELAY")==0)
+ mac_bi_data.adbdelay=atol(value);
+ }
#if 0 /* XXX: TODO with m68k_mach_* */
- /* Fill in the base stuff */
- boot_info.machtype=MACH_MAC;
- /* Read this from the macinfo we got ! */
+ /* Fill in the base stuff */
+ boot_info.machtype=MACH_MAC;
+ /* Read this from the macinfo we got ! */
/* boot_info.cputype=CPU_68020|FPUB_68881;*/
-/* boot_info.memory[0].addr=0;*/
-/* boot_info.memory[0].size=((mac_bi_data.id>>7)&31)<<20;*/
- boot_info.num_memory=1; /* On a MacII */
- boot_info.ramdisk_size=0; /* For now */
- *boot_info.command_line=0;
+/* boot_info.memory[0].addr=0;*/
+/* boot_info.memory[0].size=((mac_bi_data.id>>7)&31)<<20;*/
+ boot_info.num_memory=1; /* On a MacII */
+ boot_info.ramdisk_size=0; /* For now */
+ *boot_info.command_line=0;
#endif
}
-
+
void print_booter(char *env)
{
- char *name;
- char *value;
- while(*env)
- {
- name=env;
- value=name;
- while(*value!='='&&*value)
- value++;
- if(*value=='=')
- *value++=0;
- env=value;
- while(*env)
- env++;
- env++;
- printk("%s=%s\n", name,value);
- }
+ char *name;
+ char *value;
+ while(*env)
+ {
+ name=env;
+ value=name;
+ while(*value!='='&&*value)
+ value++;
+ if(*value=='=')
+ *value++=0;
+ env=value;
+ while(*env)
+ env++;
+ env++;
+ printk("%s=%s\n", name,value);
+ }
}
-
+
diff -puN arch/m68k/mac/config.c~m68k-superfluous-whitespace arch/m68k/mac/config.c
--- 25/arch/m68k/mac/config.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/mac/config.c Thu Apr 22 13:43:13 2004
@@ -176,7 +176,7 @@ int __init mac_parse_bootinfo(const stru
/*
* Flip into 24bit mode for an instant - flushes the L2 cache card. We
- * have to disable interrupts for this. Our IRQ handlers will crap
+ * have to disable interrupts for this. Our IRQ handlers will crap
* themselves if they take an IRQ in 24bit mode!
*/
@@ -232,10 +232,10 @@ void __init config_mac(void)
/*
* Determine hardware present
*/
-
+
mac_identify();
mac_report_hardware();
-
+
/* AFAIK only the IIci takes a cache card. The IIfx has onboard
cache ... someone needs to figure out how to tell if it's on or
not. */
@@ -252,21 +252,21 @@ void __init config_mac(void)
#ifdef OLD_NUBUS_CODE
nubus_sweep_video();
#endif
-}
+}
/*
- * Macintosh Table: hardcoded model configuration data.
+ * Macintosh Table: hardcoded model configuration data.
*
- * Much of this was defined by Alan, based on who knows what docs.
- * I've added a lot more, and some of that was pure guesswork based
- * on hardware pages present on the Mac web site. Possibly wildly
+ * Much of this was defined by Alan, based on who knows what docs.
+ * I've added a lot more, and some of that was pure guesswork based
+ * on hardware pages present on the Mac web site. Possibly wildly
* inaccurate, so look here if a new Mac model won't run. Example: if
* a Mac crashes immediately after the VIA1 registers have been dumped
- * to the screen, it probably died attempting to read DirB on a RBV.
+ * to the screen, it probably died attempting to read DirB on a RBV.
* Meaning it should have MAC_VIA_IIci here :-)
*/
-
+
struct mac_model *macintosh_config;
EXPORT_SYMBOL(macintosh_config);
@@ -288,9 +288,9 @@ static struct mac_model mac_data_table[]
/*
* Original MacII hardware
- *
+ *
*/
-
+
{
.ident = MAC_MODEL_II,
.name = "II",
@@ -324,7 +324,7 @@ static struct mac_model mac_data_table[]
.scc_type = MAC_SCC_II,
.nubus_type = MAC_NUBUS
},
-
+
/*
* Weirdified MacII hardware - all subtley different. Gee thanks
* Apple. All these boxes seem to have VIA2 in a different place to
@@ -373,7 +373,7 @@ static struct mac_model mac_data_table[]
.scc_type = MAC_SCC_II,
.nubus_type = MAC_NUBUS
},
-
+
/*
* Classic models (guessing: similar to SE/30 ?? Nope, similar to LC ...)
*/
@@ -398,7 +398,7 @@ static struct mac_model mac_data_table[]
/*
* Some Mac LC machines. Basically the same as the IIci, ADB like IIsi
*/
-
+
{
.ident = MAC_MODEL_LC,
.name = "LC",
@@ -426,15 +426,15 @@ static struct mac_model mac_data_table[]
},
/*
- * Quadra. Video is at 0xF9000000, via is like a MacII. We label it differently
- * as some of the stuff connected to VIA2 seems different. Better SCSI chip and
- * onboard ethernet using a NatSemi SONIC except the 660AV and 840AV which use an
+ * Quadra. Video is at 0xF9000000, via is like a MacII. We label it differently
+ * as some of the stuff connected to VIA2 seems different. Better SCSI chip and
+ * onboard ethernet using a NatSemi SONIC except the 660AV and 840AV which use an
* AMD 79C940 (MACE).
* The 700, 900 and 950 have some I/O chips in the wrong place to
* confuse us. The 840AV has a SCSI location of its own (same as
* the 660AV).
- */
-
+ */
+
{
.ident = MAC_MODEL_Q605,
.name = "Quadra 605",
@@ -528,7 +528,7 @@ static struct mac_model mac_data_table[]
.nubus_type = MAC_NUBUS
},
- /*
+ /*
* Performa - more LC type machines
*/
@@ -816,7 +816,7 @@ void mac_identify(void)
{
struct mac_model *m;
- /* Penguin data useful? */
+ /* Penguin data useful? */
int model = mac_bi_data.id;
if (!model) {
/* no bootinfo model id -> NetBSD booter was used! */
@@ -825,7 +825,7 @@ void mac_identify(void)
printk (KERN_WARNING "No bootinfo model ID, using cpuid instead (hey, use Penguin!)\n");
}
- macintosh_config = mac_data_table;
+ macintosh_config = mac_data_table;
for (m = macintosh_config ; m->ident != -1 ; m++) {
if (m->ident == model) {
macintosh_config = m;
@@ -846,19 +846,19 @@ void mac_identify(void)
* Report booter data:
*/
printk (KERN_DEBUG " Penguin bootinfo data:\n");
- printk (KERN_DEBUG " Video: addr 0x%lx row 0x%lx depth %lx dimensions %ld x %ld\n",
- mac_bi_data.videoaddr, mac_bi_data.videorow,
- mac_bi_data.videodepth, mac_bi_data.dimensions & 0xFFFF,
- mac_bi_data.dimensions >> 16);
+ printk (KERN_DEBUG " Video: addr 0x%lx row 0x%lx depth %lx dimensions %ld x %ld\n",
+ mac_bi_data.videoaddr, mac_bi_data.videorow,
+ mac_bi_data.videodepth, mac_bi_data.dimensions & 0xFFFF,
+ mac_bi_data.dimensions >> 16);
printk (KERN_DEBUG " Videological 0x%lx phys. 0x%lx, SCC at 0x%lx \n",
- mac_bi_data.videological, mac_orig_videoaddr,
- mac_bi_data.sccbase);
+ mac_bi_data.videological, mac_orig_videoaddr,
+ mac_bi_data.sccbase);
printk (KERN_DEBUG " Boottime: 0x%lx GMTBias: 0x%lx \n",
- mac_bi_data.boottime, mac_bi_data.gmtbias);
+ mac_bi_data.boottime, mac_bi_data.gmtbias);
printk (KERN_DEBUG " Machine ID: %ld CPUid: 0x%lx memory size: 0x%lx \n",
- mac_bi_data.id, mac_bi_data.cpuid, mac_bi_data.memsize);
+ mac_bi_data.id, mac_bi_data.cpuid, mac_bi_data.memsize);
#if 0
- printk ("Ramdisk: addr 0x%lx size 0x%lx\n",
+ printk ("Ramdisk: addr 0x%lx size 0x%lx\n",
m68k_ramdisk.addr, m68k_ramdisk.size);
#endif
diff -puN arch/m68k/mac/debug.c~m68k-superfluous-whitespace arch/m68k/mac/debug.c
--- 25/arch/m68k/mac/debug.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/mac/debug.c Thu Apr 22 13:43:13 2004
@@ -8,7 +8,7 @@
* Atari debugging and serial console stuff
*
* Assembled of parts of former atari/config.c 97-12-18 by Roman Hodek
- *
+ *
* This file is subject to the terms and conditions of the GNU General Public
* License. See the file COPYING in the main directory of this archive
* for more details.
@@ -43,7 +43,7 @@ extern void mac_serial_print(const char
#define DEBUG_SERIAL
/*
- * These two auxiliary debug functions should go away ASAP. Only usage:
+ * These two auxiliary debug functions should go away ASAP. Only usage:
* before the console output is up (after head.S come some other crucial
* setup routines :-) it permits writing 'data' to the screen as bit patterns
* (good luck reading those). Helped to figure that the bootinfo contained
@@ -77,9 +77,9 @@ void mac_debugging_short(int pos, short
/* calculate current offset */
pengoffset=(unsigned char *)(mac_videobase+(150+line*2)*mac_rowbytes)
+80*peng;
-
+
pptr=pengoffset;
-
+
for(i=0;i<8*sizeof(short);i++) /* # of bits */
{
/* value mask for bit i, reverse order */
@@ -112,12 +112,12 @@ void mac_debugging_long(int pos, long ad
/* printk("debug: #%ld !\n", addr); */
return;
}
-
+
pengoffset=(unsigned char *)(mac_videobase+(150+line*2)*mac_rowbytes)
+80*peng;
-
+
pptr=pengoffset;
-
+
for(i=0;i<8*sizeof(long);i++) /* # of bits */
{
*pptr++ = (addr & ( 1 << (8*sizeof(long)-i-1) ) ? 0xFF : 0x00);
@@ -270,7 +270,7 @@ void mac_scca_console_write (struct cons
for( i = 60*uSEC; i > 0; --i ) \
barrier(); \
} while(0)
-
+
#ifndef CONFIG_SERIAL_CONSOLE
static void __init mac_init_scc_port( int cflag, int port )
#else
@@ -285,17 +285,17 @@ void mac_init_scc_port( int cflag, int p
static int clksrc_table[9] =
/* reg 11: 0x50 = BRG, 0x00 = RTxC, 0x28 = TRxC */
- { 0x50, 0x50, 0x50, 0x50, 0x50, 0x50, 0x50, 0x00, 0x00 };
+ { 0x50, 0x50, 0x50, 0x50, 0x50, 0x50, 0x50, 0x00, 0x00 };
static int clkmode_table[9] =
/* reg 4: 0x40 = x16, 0x80 = x32, 0xc0 = x64 */
- { 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0xc0, 0x80 };
+ { 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0xc0, 0x80 };
static int div_table[9] =
/* reg12 (BRG low) */
- { 94, 62, 46, 22, 10, 4, 1, 0, 0 };
+ { 94, 62, 46, 22, 10, 4, 1, 0, 0 };
int baud = cflag & CBAUD;
int clksrc, clkmode, div, reg3, reg5;
-
+
if (cflag & CBAUDEX)
baud += B38400;
if (baud < B1200 || baud > B38400+2)
diff -puN arch/m68k/mac/iop.c~m68k-superfluous-whitespace arch/m68k/mac/iop.c
--- 25/arch/m68k/mac/iop.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/mac/iop.c Thu Apr 22 13:43:13 2004
@@ -113,9 +113,9 @@
#include <linux/proc_fs.h>
#include <linux/interrupt.h>
-#include <asm/bootinfo.h>
-#include <asm/macintosh.h>
-#include <asm/macints.h>
+#include <asm/bootinfo.h>
+#include <asm/macintosh.h>
+#include <asm/macints.h>
#include <asm/mac_iop.h>
#include <asm/mac_oss.h>
@@ -485,7 +485,7 @@ static void iop_handle_recv(uint iop_num
/*
* Send a message
- *
+ *
* The message is placed at the end of the send queue. Afterwards if the
* channel is idle we force an immediate send of the next message in the
* queue.
@@ -537,7 +537,7 @@ void iop_upload_code(uint iop_num, __u8
if ((iop_num >= NUM_IOPS) || !iop_base[iop_num]) return;
iop_loadaddr(iop_base[iop_num], shared_ram_start);
-
+
while (code_len--) {
iop_base[iop_num]->ram_data = *code_start++;
}
@@ -553,7 +553,7 @@ void iop_download_code(uint iop_num, __u
if ((iop_num >= NUM_IOPS) || !iop_base[iop_num]) return;
iop_loadaddr(iop_base[iop_num], shared_ram_start);
-
+
while (code_len--) {
*code_start++ = iop_base[iop_num]->ram_data;
}
@@ -571,7 +571,7 @@ __u8 *iop_compare_code(uint iop_num, __u
if ((iop_num >= NUM_IOPS) || !iop_base[iop_num]) return code_start;
iop_loadaddr(iop_base[iop_num], shared_ram_start);
-
+
while (code_len--) {
if (*code_start != iop_base[iop_num]->ram_data) {
return code_start;
@@ -666,12 +666,12 @@ int iop_dump_one_iop(char *buf, int iop_
iop_chan_state(iop_readb(iop, IOP_ADDR_RECV_STATE+i)),
iop_listeners[iop_num][i].handler?
iop_listeners[iop_num][i].devname : "");
-
+
}
len += sprintf(buf+len, "\n");
return len;
}
-
+
static int iop_get_proc_info(char *buf, char **start, off_t pos, int count)
{
int len, cnt;
diff -puN arch/m68k/mac/macboing.c~m68k-superfluous-whitespace arch/m68k/mac/macboing.c
--- 25/arch/m68k/mac/macboing.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/mac/macboing.c Thu Apr 22 13:43:13 2004
@@ -1,7 +1,7 @@
/*
* Mac bong noise generator. Note - we ought to put a boingy noise
* here 8)
- *
+ *
* ----------------------------------------------------------------------
* 16.11.98:
* rewrote some functions, added support for Enhanced ASC (Quadras)
@@ -22,8 +22,8 @@ static int mac_asc_inited;
static __u8 mac_asc_wave_tab[ 0x800 ];
/*
- * Alan's original sine table; needs interpolating to 0x800
- * (hint: interpolate or hardwire [0 -> Pi/2[, it's symmetric)
+ * Alan's original sine table; needs interpolating to 0x800
+ * (hint: interpolate or hardwire [0 -> Pi/2[, it's symmetric)
*/
static const signed char sine_data[] = {
0, 39, 75, 103, 121, 127, 121, 103, 75, 39,
@@ -35,16 +35,16 @@ static const signed char sine_data[] = {
*/
static volatile __u8* mac_asc_regs = ( void* )0x50F14000;
-/*
- * sample rate; is this a good default value?
+/*
+ * sample rate; is this a good default value?
*/
-static unsigned long mac_asc_samplespersec = 11050;
+static unsigned long mac_asc_samplespersec = 11050;
static int mac_bell_duration;
static unsigned long mac_bell_phase; /* 0..2*Pi -> 0..0x800 (wavetable size) */
static unsigned long mac_bell_phasepersample;
/*
- * some function protos
+ * some function protos
*/
static void mac_init_asc( void );
static void mac_nosound( unsigned long );
@@ -67,11 +67,11 @@ static void mac_init_asc( void )
{
int i;
- /*
- * do some machine specific initialization
+ /*
+ * do some machine specific initialization
* BTW:
* the NetBSD Quadra patch identifies the Enhanced Apple Sound Chip via
- * mac_asc_regs[ 0x800 ] & 0xF0 != 0
+ * mac_asc_regs[ 0x800 ] & 0xF0 != 0
* this makes no sense here, because we have to set the default sample
* rate anyway if we want correct frequencies
*/
@@ -83,27 +83,27 @@ static void mac_init_asc( void )
*/
mac_asc_regs = ( void* )0x50010000;
break;
- /*
- * not sure about how correct this list is
- * machines with the EASC enhanced apple sound chip
+ /*
+ * not sure about how correct this list is
+ * machines with the EASC enhanced apple sound chip
*/
case MAC_MODEL_Q630:
case MAC_MODEL_P475:
mac_special_bell = mac_quadra_start_bell;
mac_asc_samplespersec = 22150;
- break;
+ break;
case MAC_MODEL_C660:
case MAC_MODEL_Q840:
/*
* The Quadra 660AV and 840AV use the "Singer" custom ASIC for sound I/O.
- * It appears to be similar to the "AWACS" custom ASIC in the Power Mac
- * [678]100. Because Singer and AWACS may have a similar hardware
- * interface, this would imply that the code in drivers/sound/dmasound.c
+ * It appears to be similar to the "AWACS" custom ASIC in the Power Mac
+ * [678]100. Because Singer and AWACS may have a similar hardware
+ * interface, this would imply that the code in drivers/sound/dmasound.c
* for AWACS could be used as a basis for Singer support. All we have to
- * do is figure out how to do DMA on the 660AV/840AV through the PSC and
+ * do is figure out how to do DMA on the 660AV/840AV through the PSC and
* figure out where the Singer hardware sits in memory. (I'd look in the
- * vicinity of the AWACS location in a Power Mac [678]100 first, or the
- * current location of the Apple Sound Chip--ASC--in other Macs.) The
+ * vicinity of the AWACS location in a Power Mac [678]100 first, or the
+ * current location of the Apple Sound Chip--ASC--in other Macs.) The
* Power Mac [678]100 info can be found in MkLinux Mach kernel sources.
*
* Quoted from Apple's Tech Info Library, article number 16405:
@@ -111,7 +111,7 @@ static void mac_init_asc( void )
* Macintosh models have 16-bit audio input and output capability
* because of the AT&T DSP3210 hardware circuitry and the 16-bit Singer
* codec circuitry in the AVs. The Audio Waveform Amplifier and
- * Converter (AWAC) chip in the Power Macintosh performs the same
+ * Converter (AWAC) chip in the Power Macintosh performs the same
* 16-bit I/O functionality. The PowerBook 500 series computers
* support 16-bit stereo output, but only mono input."
*
@@ -139,8 +139,8 @@ static void mac_init_asc( void )
break;
}
- /*
- * init the wave table with a simple triangular wave
+ /*
+ * init the wave table with a simple triangular wave
* A sine wave would sure be nicer here ...
*/
for ( i = 0; i < 0x400; i++ )
@@ -149,15 +149,15 @@ static void mac_init_asc( void )
mac_asc_wave_tab[ i + 0x400 ] = 0xFF - i / 4;
}
mac_asc_inited = 1;
-}
+}
/*
- * Called to make noise; current single entry to the boing driver.
+ * Called to make noise; current single entry to the boing driver.
* Does the job for simple ASC, calls other routines else.
* XXX Fixme:
- * Should be split into asc_mksound, easc_mksound, av_mksound and
- * function pointer set in mac_init_asc which would be called at
- * init time.
+ * Should be split into asc_mksound, easc_mksound, av_mksound and
+ * function pointer set in mac_init_asc which would be called at
+ * init time.
* _This_ is rather ugly ...
*/
void mac_mksound( unsigned int freq, unsigned int length )
@@ -192,7 +192,7 @@ void mac_mksound( unsigned int freq, uns
del_timer( &mac_sound_timer );
for ( i = 0; i < 0x800; i++ )
- mac_asc_regs[ i ] = 0;
+ mac_asc_regs[ i ] = 0;
for ( i = 0; i < 0x800; i++ )
mac_asc_regs[ i ] = mac_asc_wave_tab[ i ];
@@ -218,7 +218,7 @@ void mac_mksound( unsigned int freq, uns
static void mac_nosound( unsigned long ignored )
{
mac_asc_regs[ ASC_ENABLE ] = 0;
-}
+}
/*
* EASC entry; init EASC, don't load wavetable, schedule 'start whining'.
@@ -237,7 +237,7 @@ static void mac_quadra_start_bell( unsig
mac_bell_duration = length;
mac_bell_phase = 0;
mac_bell_phasepersample = ( freq * sizeof( mac_asc_wave_tab ) ) / mac_asc_samplespersec;
- /* this is reasonably big for small frequencies */
+ /* this is reasonably big for small frequencies */
local_irq_save(flags);
@@ -247,11 +247,11 @@ static void mac_quadra_start_bell( unsig
/* set up the ASC registers */
if ( mac_asc_regs[ 0x801 ] != 1 )
{
- /* select mono mode */
+ /* select mono mode */
mac_asc_regs[ 0x807 ] = 0;
/* select sampled sound mode */
mac_asc_regs[ 0x802 ] = 0;
- /* ??? */
+ /* ??? */
mac_asc_regs[ 0x801 ] = 1;
mac_asc_regs[ 0x803 ] |= 0x80;
mac_asc_regs[ 0x803 ] &= 0x7F;
@@ -266,12 +266,12 @@ static void mac_quadra_start_bell( unsig
/*
* EASC 'start/continue whining'; I'm not sure why the above function didn't
- * already load the wave table, or at least call this one...
+ * already load the wave table, or at least call this one...
* This piece keeps reloading the wave table until done.
*/
static void mac_quadra_ring_bell( unsigned long ignored )
{
- int i, count = mac_asc_samplespersec / HZ;
+ int i, count = mac_asc_samplespersec / HZ;
__u32 flags;
/*
@@ -282,7 +282,7 @@ static void mac_quadra_ring_bell( unsign
*/
local_irq_save(flags);
-
+
del_timer( &mac_sound_timer );
if ( mac_bell_duration-- > 0 )
@@ -297,7 +297,7 @@ static void mac_quadra_ring_bell( unsign
}
else
mac_asc_regs[ 0x801 ] = 0;
-
+
local_irq_restore(flags);
}
@@ -306,4 +306,4 @@ static void mac_quadra_ring_bell( unsign
*/
static void mac_av_start_bell( unsigned int freq, unsigned int length, unsigned int volume )
{
-}
+}
diff -puN arch/m68k/mac/macints.c~m68k-superfluous-whitespace arch/m68k/mac/macints.c
--- 25/arch/m68k/mac/macints.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/mac/macints.c Thu Apr 22 13:43:13 2004
@@ -2,8 +2,8 @@
* Macintosh interrupts
*
* General design:
- * In contrary to the Amiga and Atari platforms, the Mac hardware seems to
- * exclusively use the autovector interrupts (the 'generic level0-level7'
+ * In contrary to the Amiga and Atari platforms, the Mac hardware seems to
+ * exclusively use the autovector interrupts (the 'generic level0-level7'
* interrupts with exception vectors 0x19-0x1f). The following interrupt levels
* are used:
* 1 - VIA1
@@ -248,7 +248,7 @@ void mac_init_IRQ(void)
printk("Done.\n");
#endif /* SHUTUP_SONIC */
- /*
+ /*
* Now register the handlers for the master IRQ handlers
* at levels 1-7. Most of the work is done elsewhere.
*/
@@ -496,7 +496,7 @@ int mac_irq_pending( unsigned int irq )
* FIXME: You can register interrupts on nonexistent source (ie PSC4 on a
* non-PSC machine). We should return -EINVAL in those cases.
*/
-
+
int mac_request_irq(unsigned int irq,
irqreturn_t (*handler)(int, void *, struct pt_regs *),
unsigned long flags, const char *devname, void *dev_id)
@@ -533,7 +533,7 @@ int mac_request_irq(unsigned int irq,
return 0;
}
-
+
/*
* Removes an interrupt service routine from an interrupt source.
*/
@@ -661,7 +661,7 @@ static volatile int nmi_hold;
irqreturn_t mac_nmi_handler(int irq, void *dev_id, struct pt_regs *fp)
{
int i;
- /*
+ /*
* generate debug output on NMI switch if 'debug' kernel option given
* (only works with Penguin!)
*/
@@ -691,7 +691,7 @@ irqreturn_t mac_nmi_handler(int irq, voi
fp->d0, fp->d1, fp->d2, fp->d3);
printk("d4: %08lx d5: %08lx a0: %08lx a1: %08lx\n",
fp->d4, fp->d5, fp->a0, fp->a1);
-
+
if (STACK_MAGIC != *(unsigned long *)current->kernel_stack_page)
printk("Corrupted stack page\n");
printk("Process %s (pid: %d, stackpage=%08lx)\n",
diff -puN arch/m68k/mac/misc.c~m68k-superfluous-whitespace arch/m68k/mac/misc.c
--- 25/arch/m68k/mac/misc.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/mac/misc.c Thu Apr 22 13:43:13 2004
@@ -1,5 +1,5 @@
/*
- * Miscellaneous Mac68K-specific stuff
+ * Miscellaneous Mac68K-specific stuff
*/
#include <linux/config.h>
@@ -67,7 +67,7 @@ static void adb_write_time(long data)
volatile struct adb_request req;
data += RTC_OFFSET;
-
+
adb_request((struct adb_request *) &req, NULL,
ADBREQ_RAW|ADBREQ_SYNC,
6, CUDA_PACKET, CUDA_SET_TIME,
@@ -324,7 +324,7 @@ void pmu_restart(void)
adb_request(NULL, NULL, ADBREQ_RAW|ADBREQ_SYNC,
3, PMU_PACKET, PMU_SET_INTR_MASK,
PMU_INT_ADB|PMU_INT_TICK);
-
+
adb_request(NULL, NULL, ADBREQ_RAW|ADBREQ_SYNC,
2, PMU_PACKET, PMU_RESET);
}
@@ -477,7 +477,7 @@ void mac_reset(void)
".chip 68030\n\t"
"lea %/pc@(1f),%/a0\n\t"
"addl %0,%/a0\n\t"/* fixup target address and stack ptr */
- "addl %0,%/sp\n\t"
+ "addl %0,%/sp\n\t"
"pflusha\n\t"
"jmp %/a0@\n\t" /* jump into physical memory */
"0:.long 0\n\t" /* a constant zero. */
@@ -494,7 +494,7 @@ void mac_reset(void)
"movec %/a0, %/cacr\n\t" /* flush i&d caches */
"movew #0x2700,%/sr\n\t" /* set up status register */
"movel %1@(0x0),%/a0\n\t"/* load interrupt stack pointer */
- "movec %/a0, %/isp\n\t"
+ "movec %/a0, %/isp\n\t"
"movel %1@(0x4),%/a0\n\t" /* load reset vector */
"reset\n\t" /* reset external devices */
"jmp %/a0@\n\t" /* jump to the reset vector */
@@ -579,7 +579,7 @@ static void unmktime(unsigned long time,
return;
}
-/*
+/*
* Read/write the hardware clock.
*/
diff -puN arch/m68k/mac/oss.c~m68k-superfluous-whitespace arch/m68k/mac/oss.c
--- 25/arch/m68k/mac/oss.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/mac/oss.c Thu Apr 22 13:43:13 2004
@@ -20,9 +20,9 @@
#include <linux/delay.h>
#include <linux/init.h>
-#include <asm/bootinfo.h>
-#include <asm/machw.h>
-#include <asm/macintosh.h>
+#include <asm/bootinfo.h>
+#include <asm/machw.h>
+#include <asm/macintosh.h>
#include <asm/macints.h>
#include <asm/mac_via.h>
#include <asm/mac_oss.h>
@@ -91,7 +91,7 @@ void __init oss_nubus_init(void)
* Handle miscellaneous OSS interrupts. Right now that's just sound
* and SCSI; everything else is routed to its own autovector IRQ.
*/
-
+
irqreturn_t oss_irq(int irq, void *dev_id, struct pt_regs *regs)
{
int events;
@@ -100,7 +100,7 @@ irqreturn_t oss_irq(int irq, void *dev_i
if (!events)
return IRQ_NONE;
-#ifdef DEBUG_IRQS
+#ifdef DEBUG_IRQS
if ((console_loglevel == 10) && !(events & OSS_IP_SCSI)) {
printk("oss_irq: irq %d events = 0x%04X\n", irq,
(int) oss->irq_pending);
diff -puN arch/m68k/mac/psc.c~m68k-superfluous-whitespace arch/m68k/mac/psc.c
--- 25/arch/m68k/mac/psc.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/mac/psc.c Thu Apr 22 13:43:13 2004
@@ -20,9 +20,9 @@
#include <linux/init.h>
#include <asm/traps.h>
-#include <asm/bootinfo.h>
-#include <asm/macintosh.h>
-#include <asm/macints.h>
+#include <asm/bootinfo.h>
+#include <asm/macintosh.h>
+#include <asm/macints.h>
#include <asm/mac_psc.h>
#define DEBUG_PSC
diff -puN arch/m68k/mac/via.c~m68k-superfluous-whitespace arch/m68k/mac/via.c
--- 25/arch/m68k/mac/via.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/mac/via.c Thu Apr 22 13:43:13 2004
@@ -26,10 +26,10 @@
#include <linux/ide.h>
#include <asm/traps.h>
-#include <asm/bootinfo.h>
-#include <asm/macintosh.h>
+#include <asm/bootinfo.h>
+#include <asm/macintosh.h>
#include <asm/macints.h>
-#include <asm/machw.h>
+#include <asm/machw.h>
#include <asm/mac_via.h>
#include <asm/mac_psc.h>
@@ -93,7 +93,7 @@ void __init via_init(void)
/* IIci, IIsi, IIvx, IIvi (P6xx), LC series */
- case MAC_VIA_IIci:
+ case MAC_VIA_IIci:
via1 = (void *) VIA1_BASE;
if (macintosh_config->ident == MAC_MODEL_IIFX) {
via2 = NULL;
@@ -166,7 +166,7 @@ void __init via_init(void)
via1[vT2CH] = 0;
via1[vACR] &= 0x3F;
- /*
+ /*
* SE/30: disable video IRQ
* XXX: testing for SE/30 VBL
*/
@@ -174,8 +174,8 @@ void __init via_init(void)
if (macintosh_config->ident == MAC_MODEL_SE30) {
via1[vDirB] |= 0x40;
via1[vBufB] |= 0x40;
- }
-
+ }
+
/*
* Set the RTC bits to a known state: all lines to outputs and
* RTC disabled (yes that's 0 to enable and 1 to disable).
@@ -243,7 +243,7 @@ void __init via_init(void)
*/
void __init via_init_clock(irqreturn_t (*func)(int, void *, struct pt_regs *))
-{
+{
via1[vACR] |= 0x40;
via1[vT1LL] = MAC_CLOCK_LOW;
via1[vT1LH] = MAC_CLOCK_HIGH;
@@ -537,7 +537,7 @@ void via_irq_enable(int irq) {
/* But not on PowerBooks, that's ADB... */
if ((macintosh_config->adb_type != MAC_ADB_PB1) &&
(macintosh_config->adb_type != MAC_ADB_PB2)) {
- switch(macintosh_config->ident)
+ switch(macintosh_config->ident)
{
case MAC_MODEL_II:
case MAC_MODEL_IIX:
diff -puN arch/m68k/Makefile~m68k-superfluous-whitespace arch/m68k/Makefile
--- 25/arch/m68k/Makefile~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/Makefile Thu Apr 22 13:43:13 2004
@@ -56,7 +56,7 @@ ifndef CONFIG_SUN3
head-y := arch/m68k/kernel/head.o
else
head-y := arch/m68k/kernel/sun3-head.o
-endif
+endif
core-y += arch/m68k/kernel/ arch/m68k/mm/
libs-y += arch/m68k/lib/
diff -puN arch/m68k/math-emu/fp_arith.c~m68k-superfluous-whitespace arch/m68k/math-emu/fp_arith.c
--- 25/arch/m68k/math-emu/fp_arith.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/math-emu/fp_arith.c Thu Apr 22 13:43:13 2004
@@ -458,7 +458,7 @@ static void fp_roundint(struct fp_ext *d
return;
/* infinities and zeroes */
- if (IS_INF(dest) || IS_ZERO(dest))
+ if (IS_INF(dest) || IS_ZERO(dest))
return;
/* first truncate the lower bits */
diff -puN arch/m68k/math-emu/fp_cond.S~m68k-superfluous-whitespace arch/m68k/math-emu/fp_cond.S
--- 25/arch/m68k/math-emu/fp_cond.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/math-emu/fp_cond.S Thu Apr 22 13:43:13 2004
@@ -105,10 +105,10 @@ fp_fscc:
| decode addressing mode
fp_decode_addr_mode
- .long fp_data, fp_fdbcc
- .long fp_indirect, fp_postinc
- .long fp_predecr, fp_disp16
- .long fp_extmode0, fp_extmode1
+ .long fp_data, fp_fdbcc
+ .long fp_indirect, fp_postinc
+ .long fp_predecr, fp_disp16
+ .long fp_extmode0, fp_extmode1
| addressing mode: data register direct
fp_data:
diff -puN arch/m68k/math-emu/fp_log.c~m68k-superfluous-whitespace arch/m68k/math-emu/fp_log.c
--- 25/arch/m68k/math-emu/fp_log.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/math-emu/fp_log.c Thu Apr 22 13:43:13 2004
@@ -48,7 +48,7 @@ fp_fsqrt(struct fp_ext *dest, struct fp_
/*
* sqrt(m) * 2^(p) , if e = 2*p
- * sqrt(m*2^e) =
+ * sqrt(m*2^e) =
* sqrt(2*m) * 2^(p) , if e = 2*p + 1
*
* So we use the last bit of the exponent to decide wether to
@@ -80,7 +80,7 @@ fp_fsqrt(struct fp_ext *dest, struct fp_
* which has a null point on x = sqrt(r).
*
* It gives:
- * x' := x - f(x)/f'(x)
+ * x' := x - f(x)/f'(x)
* = x - (x^2 -r)/(2*x)
* = x - (x - r/x)/2
* = (2*x - x + r/x)/2
diff -puN arch/m68k/math-emu/fp_scan.S~m68k-superfluous-whitespace arch/m68k/math-emu/fp_scan.S
--- 25/arch/m68k/math-emu/fp_scan.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/math-emu/fp_scan.S Thu Apr 22 13:43:13 2004
@@ -133,10 +133,10 @@ fp_getsource:
| decode addressing mode for source
fp_decode_addr_mode
- .long fp_data, fp_ill
- .long fp_indirect, fp_postinc
- .long fp_predecr, fp_disp16
- .long fp_extmode0, fp_extmode1
+ .long fp_data, fp_ill
+ .long fp_indirect, fp_postinc
+ .long fp_predecr, fp_disp16
+ .long fp_extmode0, fp_extmode1
| addressing mode: data register direct
fp_data:
diff -puN arch/m68k/math-emu/fp_util.S~m68k-superfluous-whitespace arch/m68k/math-emu/fp_util.S
--- 25/arch/m68k/math-emu/fp_util.S~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/math-emu/fp_util.S Thu Apr 22 13:43:13 2004
@@ -1337,7 +1337,7 @@ fp_finalrounding_single:
jra fp_finaltest
fp_finalrounding_single_fast:
- addq.l #8,%sp
+ addq.l #8,%sp
jsr fp_normalize_ext
jsr fp_normalize_single_fast
jra fp_finaltest
diff -puN arch/m68k/mm/fault.c~m68k-superfluous-whitespace arch/m68k/mm/fault.c
--- 25/arch/m68k/mm/fault.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/mm/fault.c Thu Apr 22 13:43:13 2004
@@ -157,7 +157,7 @@ good_area:
survive:
fault = handle_mm_fault(mm, vma, address, write);
#ifdef DEBUG
- printk("handle_mm_fault returns %d\n",fault);
+ printk("handle_mm_fault returns %d\n",fault);
#endif
switch (fault) {
case 1:
@@ -186,7 +186,7 @@ out_of_memory:
down_read(&mm->mmap_sem);
goto survive;
}
-
+
printk("VM: killing process %s\n", current->comm);
if (user_mode(regs))
do_exit(SIGKILL);
diff -puN arch/m68k/mm/hwtest.c~m68k-superfluous-whitespace arch/m68k/mm/hwtest.c
--- 25/arch/m68k/mm/hwtest.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/mm/hwtest.c Thu Apr 22 13:43:13 2004
@@ -3,9 +3,9 @@
* that it was also in drivers/nubus/nubus.c and I wanted to
* use it in hp300/config.c, so it seemed sensible to pull it
* out into its own file.
- *
+ *
* The test is for use when trying to read a hardware register
- * that isn't present would cause a bus error. We set up a
+ * that isn't present would cause a bus error. We set up a
* temporary handler so that this doesn't kill the kernel.
*
* There is a test-by-reading and a test-by-writing; I present
@@ -37,7 +37,7 @@ int hwreg_present( volatile void *regp )
"movec %4,%/vbr\n\t"
"movel %/sp,%1\n\t"
"moveq #0,%0\n\t"
- "tstb %3@\n\t"
+ "tstb %3@\n\t"
"nop\n\t"
"moveq #1,%0\n"
"Lberr1:\n\t"
@@ -50,7 +50,7 @@ int hwreg_present( volatile void *regp )
return( ret );
}
EXPORT_SYMBOL(hwreg_present);
-
+
/* Basically the same, but writes a value into a word register, protected
* by a bus error handler. Returns 1 if successful, 0 otherwise.
*/
@@ -67,7 +67,7 @@ int hwreg_write( volatile void *regp, un
"movec %4,%/vbr\n\t"
"movel %/sp,%1\n\t"
"moveq #0,%0\n\t"
- "movew %5,%3@\n\t"
+ "movew %5,%3@\n\t"
"nop \n\t" /* If this nop isn't present, 'ret' may already be
* loaded with 1 at the time the bus error
* happens! */
diff -puN arch/m68k/mm/init.c~m68k-superfluous-whitespace arch/m68k/mm/init.c
--- 25/arch/m68k/mm/init.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/mm/init.c Thu Apr 22 13:43:13 2004
@@ -109,7 +109,7 @@ void __init mem_init(void)
continue;
}
}
-
+
#ifndef CONFIG_SUN3
/* insert pointer tables allocated so far into the tablelist */
init_pointer_table((unsigned long)kernel_pg_dir);
diff -puN arch/m68k/mm/memory.c~m68k-superfluous-whitespace arch/m68k/mm/memory.c
--- 25/arch/m68k/mm/memory.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/mm/memory.c Thu Apr 22 13:43:13 2004
@@ -298,7 +298,7 @@ void cache_clear (unsigned long paddr, i
: "d0");
#ifdef CONFIG_M68K_L2_CACHE
if(mach_l2_flush)
- mach_l2_flush(0);
+ mach_l2_flush(0);
#endif
}
@@ -350,7 +350,7 @@ void cache_push (unsigned long paddr, in
: "d0");
#ifdef CONFIG_M68K_L2_CACHE
if(mach_l2_flush)
- mach_l2_flush(1);
+ mach_l2_flush(1);
#endif
}
@@ -387,7 +387,7 @@ static unsigned long virt_to_phys_slow(u
unsigned long mmusr;
set_fs(get_ds());
-
+
asm volatile (".chip 68040\n\t"
"ptestr (%1)\n\t"
"movec %%mmusr, %0\n\t"
diff -puN arch/m68k/mm/motorola.c~m68k-superfluous-whitespace arch/m68k/mm/motorola.c
--- 25/arch/m68k/mm/motorola.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/mm/motorola.c Thu Apr 22 13:43:13 2004
@@ -2,9 +2,9 @@
* linux/arch/m68k/motorola.c
*
* Routines specific to the Motorola MMU, originally from:
- * linux/arch/m68k/init.c
+ * linux/arch/m68k/init.c
* which are Copyright (C) 1995 Hamish Macdonald
- *
+ *
* Moved 8/20/1999 Sam Creasey
*/
@@ -99,7 +99,7 @@ static pmd_t * __init kernel_ptr_table(v
return last_pgtable;
}
-static unsigned long __init
+static unsigned long __init
map_chunk (unsigned long addr, long size)
{
#define PTRTREESIZE (256*1024)
diff -puN arch/m68k/mm/sun3kmap.c~m68k-superfluous-whitespace arch/m68k/mm/sun3kmap.c
--- 25/arch/m68k/mm/sun3kmap.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/mm/sun3kmap.c Thu Apr 22 13:43:13 2004
@@ -26,7 +26,7 @@ extern void print_pte_vaddr(unsigned lon
extern void mmu_emu_map_pmeg (int context, int vaddr);
-static inline void do_page_mapin(unsigned long phys, unsigned long virt,
+static inline void do_page_mapin(unsigned long phys, unsigned long virt,
unsigned long type)
{
unsigned long pte;
@@ -44,11 +44,11 @@ static inline void do_page_mapin(unsigne
}
-static inline void do_pmeg_mapin(unsigned long phys, unsigned long virt,
+static inline void do_pmeg_mapin(unsigned long phys, unsigned long virt,
unsigned long type, int pages)
{
- if(sun3_get_segmap(virt & ~SUN3_PMEG_MASK) == SUN3_INVALID_PMEG)
+ if(sun3_get_segmap(virt & ~SUN3_PMEG_MASK) == SUN3_INVALID_PMEG)
mmu_emu_map_pmeg(sun3_get_context(), virt);
while(pages) {
@@ -59,7 +59,7 @@ static inline void do_pmeg_mapin(unsigne
}
}
-void *sun3_ioremap(unsigned long phys, unsigned long size,
+void *sun3_ioremap(unsigned long phys, unsigned long size,
unsigned long type)
{
struct vm_struct *area;
@@ -79,7 +79,7 @@ void *sun3_ioremap(unsigned long phys, u
return NULL;
#ifdef SUN3_KMAP_DEBUG
- printk("ioremap: got virt %p size %lx(%lx)\n",
+ printk("ioremap: got virt %p size %lx(%lx)\n",
area->addr, size, area->size);
#endif
@@ -93,39 +93,39 @@ void *sun3_ioremap(unsigned long phys, u
seg_pages = (SUN3_PMEG_SIZE - (virt & SUN3_PMEG_MASK)) / PAGE_SIZE;
if(seg_pages > pages)
seg_pages = pages;
-
+
do_pmeg_mapin(phys, virt, type, seg_pages);
pages -= seg_pages;
phys += seg_pages * PAGE_SIZE;
virt += seg_pages * PAGE_SIZE;
}
-
+
return (void *)ret;
}
-
-
+
+
void *__ioremap(unsigned long phys, unsigned long size, int cache)
{
-
+
return sun3_ioremap(phys, size, SUN3_PAGE_TYPE_IO);
-
+
}
void iounmap(void *addr)
{
- vfree((void *)(PAGE_MASK & (unsigned long)addr));
+ vfree((void *)(PAGE_MASK & (unsigned long)addr));
}
/* sun3_map_test(addr, val) -- Reads a byte from addr, storing to val,
* trapping the potential read fault. Returns 0 if the access faulted,
* 1 on success.
- *
+ *
* This function is primarily used to check addresses on the VME bus.
*
* Mucking with the page fault handler seems a little hackish to me, but
- * SunOS, NetBSD, and Mach all implemented this check in such a manner,
+ * SunOS, NetBSD, and Mach all implemented this check in such a manner,
* so I figure we're allowed.
*/
int sun3_map_test(unsigned long addr, char *val)
@@ -151,6 +151,6 @@ int sun3_map_test(unsigned long addr, ch
"_sun3_map_test_end:\n"
: "=a"(val), "=r"(ret)
: "a"(addr));
-
+
return ret;
}
diff -puN arch/m68k/mm/sun3mmu.c~m68k-superfluous-whitespace arch/m68k/mm/sun3mmu.c
--- 25/arch/m68k/mm/sun3mmu.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/mm/sun3mmu.c Thu Apr 22 13:43:13 2004
@@ -1,4 +1,4 @@
-/*
+/*
* linux/arch/m68k/mm/sun3mmu.c
*
* Implementations of mm routines specific to the sun3 MMU.
@@ -64,12 +64,12 @@ void __init paging_init(void)
size = num_pages * sizeof(pte_t);
size = (size + PAGE_SIZE) & ~(PAGE_SIZE-1);
-
+
next_pgtable = (unsigned long)alloc_bootmem_pages(size);
bootmem_end = (next_pgtable + size + PAGE_SIZE) & PAGE_MASK;
/* Map whole memory from PAGE_OFFSET (0x0E000000) */
- pg_dir += PAGE_OFFSET >> PGDIR_SHIFT;
+ pg_dir += PAGE_OFFSET >> PGDIR_SHIFT;
while (address < (unsigned long)high_memory) {
pg_table = (pte_t *) __pa (next_pgtable);
@@ -95,7 +95,7 @@ void __init paging_init(void)
/* memory sizing is a hack stolen from motorola.c.. hope it works for us */
zones_size[0] = ((unsigned long)high_memory - PAGE_OFFSET) >> PAGE_SHIFT;
zones_size[1] = 0;
-
+
free_area_init(zones_size);
}
diff -puN arch/m68k/mvme147/config.c~m68k-superfluous-whitespace arch/m68k/mvme147/config.c
--- 25/arch/m68k/mvme147/config.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/mvme147/config.c Thu Apr 22 13:43:13 2004
@@ -120,8 +120,8 @@ void __init config_mvme147(void)
static irqreturn_t mvme147_timer_int (int irq, void *dev_id, struct pt_regs *fp)
{
- m147_pcc->t1_int_cntrl = PCC_TIMER_INT_CLR;
- m147_pcc->t1_int_cntrl = PCC_INT_ENAB|PCC_LEVEL_TIMER1;
+ m147_pcc->t1_int_cntrl = PCC_TIMER_INT_CLR;
+ m147_pcc->t1_int_cntrl = PCC_INT_ENAB|PCC_LEVEL_TIMER1;
return tick_handler(irq, dev_id, fp);
}
@@ -129,16 +129,16 @@ static irqreturn_t mvme147_timer_int (in
void mvme147_sched_init (irqreturn_t (*timer_routine)(int, void *, struct pt_regs *))
{
tick_handler = timer_routine;
- request_irq (PCC_IRQ_TIMER1, mvme147_timer_int,
+ request_irq (PCC_IRQ_TIMER1, mvme147_timer_int,
IRQ_FLG_REPLACE, "timer 1", NULL);
-
+
/* Init the clock with a value */
/* our clock goes off every 6.25us */
m147_pcc->t1_preload = PCC_TIMER_PRELOAD;
- m147_pcc->t1_cntrl = 0x0; /* clear timer */
- m147_pcc->t1_cntrl = 0x3; /* start timer */
+ m147_pcc->t1_cntrl = 0x0; /* clear timer */
+ m147_pcc->t1_cntrl = 0x3; /* start timer */
m147_pcc->t1_int_cntrl = PCC_TIMER_INT_CLR; /* clear pending ints */
- m147_pcc->t1_int_cntrl = PCC_INT_ENAB|PCC_LEVEL_TIMER1;
+ m147_pcc->t1_int_cntrl = PCC_INT_ENAB|PCC_LEVEL_TIMER1;
}
/* This is always executed with interrupts disabled. */
diff -puN arch/m68k/mvme16x/mvme16x_ksyms.c~m68k-superfluous-whitespace arch/m68k/mvme16x/mvme16x_ksyms.c
--- 25/arch/m68k/mvme16x/mvme16x_ksyms.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/mvme16x/mvme16x_ksyms.c Thu Apr 22 13:43:13 2004
@@ -2,5 +2,5 @@
#include <linux/types.h>
#include <asm/ptrace.h>
#include <asm/mvme16xhw.h>
-
+
EXPORT_SYMBOL(mvme16x_config);
diff -puN arch/m68k/mvme16x/rtc.c~m68k-superfluous-whitespace arch/m68k/mvme16x/rtc.c
--- 25/arch/m68k/mvme16x/rtc.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/mvme16x/rtc.c Thu Apr 22 13:43:13 2004
@@ -43,7 +43,7 @@ static int rtc_ioctl(struct inode *inode
{
volatile MK48T08ptr_t rtc = (MK48T08ptr_t)MVME_RTC_BASE;
unsigned long flags;
- struct rtc_time wtime;
+ struct rtc_time wtime;
switch (cmd) {
case RTC_RD_TIME: /* Read the time/date from RTC */
@@ -101,7 +101,7 @@ static int rtc_ioctl(struct inode *inode
if (yrs >= 2070)
return -EINVAL;
-
+
local_irq_save(flags);
rtc->ctrl = RTC_WRITE;
diff -puN arch/m68k/q40/config.c~m68k-superfluous-whitespace arch/m68k/q40/config.c
--- 25/arch/m68k/q40/config.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/q40/config.c Thu Apr 22 13:43:13 2004
@@ -158,7 +158,7 @@ static unsigned int serports[]={0x3f8,0x
void q40_disable_irqs(void)
{
unsigned i,j;
-
+
j=0;
while((i=serports[j++])) outb(0,i+UART_IER);
master_outb(0,EXT_ENABLE_REG);
@@ -169,16 +169,16 @@ void __init config_q40(void)
{
mach_sched_init = q40_sched_init;
- mach_init_IRQ = q40_init_IRQ;
- mach_gettimeoffset = q40_gettimeoffset;
- mach_hwclk = q40_hwclk;
+ mach_init_IRQ = q40_init_IRQ;
+ mach_gettimeoffset = q40_gettimeoffset;
+ mach_hwclk = q40_hwclk;
mach_get_ss = q40_get_ss;
mach_get_rtc_pll = q40_get_rtc_pll;
mach_set_rtc_pll = q40_set_rtc_pll;
mach_set_clock_mmss = q40_set_clock_mmss;
mach_reset = q40_reset;
- mach_free_irq = q40_free_irq;
+ mach_free_irq = q40_free_irq;
mach_process_int = q40_process_int;
mach_get_irq_list = show_q40_interrupts;
mach_request_irq = q40_request_irq;
@@ -203,9 +203,9 @@ void __init config_q40(void)
q40_disable_irqs();
/* no DMA at all, but ide-scsi requires it.. make sure
- * all physical RAM fits into the boundary - otherwise
+ * all physical RAM fits into the boundary - otherwise
* allocator may play costly and useless tricks */
- mach_max_dma_address = 1024*1024*1024;
+ mach_max_dma_address = 1024*1024*1024;
/* useful for early debugging stages - writes kernel messages into SRAM */
if (!strncmp( m68k_debug_device,"mem",3 ))
@@ -285,7 +285,7 @@ int q40_hwclk(int op, struct rtc_time *t
t->tm_sec = bcd2bin (Q40_RTC_SECS);
Q40_RTC_CTRL &= ~(Q40_RTC_READ);
-
+
if (t->tm_year < 70)
t->tm_year += 100;
t->tm_wday = bcd2bin(Q40_RTC_DOW)-1;
@@ -318,7 +318,7 @@ int q40_set_clock_mmss (unsigned long no
if ((rtc_minutes < real_minutes
? real_minutes - rtc_minutes
: rtc_minutes - real_minutes) < 30)
- {
+ {
Q40_RTC_CTRL |= Q40_RTC_WRITE;
Q40_RTC_MINS = bin2bcd(real_minutes);
Q40_RTC_SECS = bin2bcd(real_seconds);
diff -puN arch/m68k/q40/Makefile~m68k-superfluous-whitespace arch/m68k/q40/Makefile
--- 25/arch/m68k/q40/Makefile~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/q40/Makefile Thu Apr 22 13:43:13 2004
@@ -2,4 +2,4 @@
# Makefile for Linux arch/m68k/q40 source directory
#
-obj-y := config.o q40ints.o
+obj-y := config.o q40ints.o
diff -puN arch/m68k/q40/q40ints.c~m68k-superfluous-whitespace arch/m68k/q40/q40ints.c
--- 25/arch/m68k/q40/q40ints.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/q40/q40ints.c Thu Apr 22 13:43:13 2004
@@ -30,14 +30,14 @@
#include <asm/q40_master.h>
#include <asm/q40ints.h>
-/*
- * Q40 IRQs are defined as follows:
+/*
+ * Q40 IRQs are defined as follows:
* 3,4,5,6,7,10,11,14,15 : ISA dev IRQs
* 16-31: reserved
* 32 : keyboard int
* 33 : frame int (50/200 Hz periodic timer)
* 34 : sample int (10/20 KHz periodic timer)
- *
+ *
*/
extern int ints_inited;
@@ -122,7 +122,7 @@ int q40_request_irq(unsigned int irq,
case 12: case 13:
printk("%s: ISA IRQ %d from %s not implemented by HW\n", __FUNCTION__, irq, devname);
return -ENXIO;
- case 11:
+ case 11:
printk("warning IRQ 10 and 11 not distinguishable\n");
irq=10;
default:
@@ -131,7 +131,7 @@ int q40_request_irq(unsigned int irq,
if (irq<Q40_IRQ_SAMPLE)
{
- if (irq_tab[irq].dev_id != NULL)
+ if (irq_tab[irq].dev_id != NULL)
{
printk("%s: IRQ %d from %s is not replaceable\n",
__FUNCTION__, irq, irq_tab[irq].devname);
@@ -176,13 +176,13 @@ void q40_free_irq(unsigned int irq, void
default:
;
}
-
+
if (irq<Q40_IRQ_SAMPLE)
{
if (irq_tab[irq].dev_id != dev_id)
printk("%s: Removing probably wrong IRQ %d from %s\n",
__FUNCTION__, irq, irq_tab[irq].devname);
-
+
irq_tab[irq].handler = q40_defhand;
irq_tab[irq].flags = 0;
irq_tab[irq].dev_id = NULL;
@@ -205,7 +205,7 @@ irqreturn_t q40_process_int (int level,
return IRQ_HANDLED;
}
-/*
+/*
* this stuff doesn't really belong here..
*/
@@ -267,10 +267,10 @@ void q40_sched_init (irqreturn_t (*timer
}
-/*
- * tables to translate bits into IRQ numbers
+/*
+ * tables to translate bits into IRQ numbers
* it is a good idea to order the entries by priority
- *
+ *
*/
struct IRQ_TABLE{ unsigned mask; int irq ;};
@@ -319,7 +319,7 @@ irqreturn_t q40_irq2_handler (int vec, v
mir=master_inb(IIRQ_REG);
if (mir&Q40_IRQ_FRAME_MASK) {
irq_tab[Q40_IRQ_FRAME].count++;
- irq_tab[Q40_IRQ_FRAME].handler(Q40_IRQ_FRAME,irq_tab[Q40_IRQ_FRAME].dev_id,fp);
+ irq_tab[Q40_IRQ_FRAME].handler(Q40_IRQ_FRAME,irq_tab[Q40_IRQ_FRAME].dev_id,fp);
master_outb(-1,FRAME_CLEAR_REG);
}
if ((mir&Q40_IRQ_SER_MASK) || (mir&Q40_IRQ_EXT_MASK)) {
@@ -356,15 +356,15 @@ irqreturn_t q40_irq2_handler (int vec, v
#endif
goto iirq;
}
- irq_tab[irq].count++;
+ irq_tab[irq].count++;
irq_tab[irq].state |= IRQ_INPROGRESS;
irq_tab[irq].handler(irq,irq_tab[irq].dev_id,fp);
irq_tab[irq].state &= ~IRQ_INPROGRESS;
-
+
/* naively enable everything, if that fails than */
/* this function will be reentered immediately thus */
/* getting another chance to disable the IRQ */
-
+
if ( disabled ) {
#ifdef IP_USE_DISABLE
if (irq>4){
@@ -379,9 +379,9 @@ irqreturn_t q40_irq2_handler (int vec, v
return IRQ_HANDLED;
}
}
- if (mer && ccleirq>0 && !aliased_irq)
+ if (mer && ccleirq>0 && !aliased_irq)
printk("ISA interrupt from unknown source? EIRQ_REG = %x\n",mer),ccleirq--;
- }
+ }
iirq:
mir=master_inb(IIRQ_REG);
/* should test whether keyboard irq is really enabled, doing it in defhand */
@@ -399,10 +399,10 @@ int show_q40_interrupts (struct seq_file
for (i = 0; i <= Q40_IRQ_MAX; i++) {
if (irq_tab[i].count)
seq_printf(p, "%sIRQ %02d: %8d %s%s\n",
- (i<=15) ? "ISA-" : " " ,
+ (i<=15) ? "ISA-" : " " ,
i, irq_tab[i].count,
irq_tab[i].devname[0] ? irq_tab[i].devname : "?",
- irq_tab[i].handler == q40_defhand ?
+ irq_tab[i].handler == q40_defhand ?
" (now unassigned)" : "");
}
return 0;
@@ -440,7 +440,7 @@ void q40_enable_irq (unsigned int irq)
{
mext_disabled--;
if (mext_disabled>0)
- printk("q40_enable_irq : nested disable/enable\n");
+ printk("q40_enable_irq : nested disable/enable\n");
if (mext_disabled==0)
master_outb(1,EXT_ENABLE_REG);
}
diff -puN arch/m68k/q40/README~m68k-superfluous-whitespace arch/m68k/q40/README
--- 25/arch/m68k/q40/README~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/q40/README Thu Apr 22 13:43:13 2004
@@ -9,18 +9,18 @@ and mirrors.
Hints to documentation usually refer to the linux source tree in
/usr/src/linux/Documentation unless URL given.
-It seems IRQ unmasking can't be safely done on a Q40. IRQ probing
+It seems IRQ unmasking can't be safely done on a Q40. IRQ probing
is not implemented - do not try it! (See below)
For a list of kernel command-line options read the documentation for the
particular device drivers.
The floppy imposes a very high interrupt load on the CPU, approx 30K/s.
-When something blocks interrupts (HD) it will lose some of them, so far
+When something blocks interrupts (HD) it will lose some of them, so far
this is not known to have caused any data loss. On highly loaded systems
-it can make the floppy very slow or practically stop. Other Q40 OS' simply
+it can make the floppy very slow or practically stop. Other Q40 OS' simply
poll the floppy for this reason - something that can't be done in Linux.
-Only possible cure is getting a 82072 controller with fifo instead of
+Only possible cure is getting a 82072 controller with fifo instead of
the 8272A.
drivers used by the Q40, apart from the very obvious (console etc.):
@@ -28,7 +28,7 @@ drivers used by the Q40, apart from the
serial.c # normal PC driver - any speed
lp.c # printer driver
genrtc.c # RTC
- char/joystick/* # most of this should work, not
+ char/joystick/* # most of this should work, not
# in default config.in
block/q40ide.c # startup for ide
ide* # see Documentation/ide.txt
@@ -41,30 +41,30 @@ drivers used by the Q40, apart from the
sound/dmasound_core.c
dmasound_q40.c
-Various other PC drivers can be enabled simply by adding them to
+Various other PC drivers can be enabled simply by adding them to
arch/m68k/config.in, especially 8 bit devices should be without any
-problems. For cards using 16bit io/mem more care is required, like
+problems. For cards using 16bit io/mem more care is required, like
checking byte order issues, hacking memcpy_*_io etc.
Debugging
=========
-Upon startup the kernel will usually output "ABCQGHIJ" into the SRAM,
-preceded by the booter signature. This is a trace just in case something
-went wrong during earliest setup stages of head.S.
-**Changed** to preserve SRAM contents by default, this is only done when
-requested - SRAM must start with '%LX$' signature to do this. '-d' option
+Upon startup the kernel will usually output "ABCQGHIJ" into the SRAM,
+preceded by the booter signature. This is a trace just in case something
+went wrong during earliest setup stages of head.S.
+**Changed** to preserve SRAM contents by default, this is only done when
+requested - SRAM must start with '%LX$' signature to do this. '-d' option
to 'lxx' loader enables this.
SRAM can also be used as additional console device, use debug=mem.
-This will save kernel startup msgs into SRAM, the screen will display
+This will save kernel startup msgs into SRAM, the screen will display
only the penguin - and shell prompt if it gets that far..
Unfortunately only 2000 bytes are available.
Serial console works and can also be used for debugging, see loader_txt
-Most problems seem to be caused by fawlty or badly configured io-cards or
+Most problems seem to be caused by fawlty or badly configured io-cards or
hard drives anyway.
Make sure to configure the parallel port as SPP and remove IRQ/DMA jumpers
for first testing. The Q40 does not support DMA and may have trouble with
@@ -74,7 +74,7 @@ parallel ports version of interrupts.
Q40 Hardware Description
========================
-This is just an overview, see asm-m68k/* for details ask if you have any
+This is just an overview, see asm-m68k/* for details ask if you have any
questions.
The Q40 consists of a 68040@40 MHz, 1MB video RAM, up to 32MB RAM, AT-style
@@ -82,16 +82,16 @@ keyboard interface, 1 Programmable LED,
shadow ROM.
The Q60 has any of 68060 or 68LC060 and up to 128 MB RAM.
-Most interfacing like floppy, IDE, serial and parallel ports is done via ISA
-slots. The ISA io and mem range is mapped (sparse&byteswapped!) into separate
+Most interfacing like floppy, IDE, serial and parallel ports is done via ISA
+slots. The ISA io and mem range is mapped (sparse&byteswapped!) into separate
regions of the memory.
-The main interrupt register IIRQ_REG will indicate whether an IRQ was internal
+The main interrupt register IIRQ_REG will indicate whether an IRQ was internal
or from some ISA devices, EIRQ_REG can distinguish up to 8 ISA IRQs.
The Q40 custom chip is programmable to provide 2 periodic timers:
- 50 or 200 Hz - level 2, !!THIS CANT BE DISABLED!!
- - 10 or 20 KHz - level 4, used for dma-sound
-
+ - 10 or 20 KHz - level 4, used for dma-sound
+
Linux uses the 200 Hz interrupt for timer and beep by default.
@@ -112,7 +112,7 @@ q40ints.c now contains a trivial hack fo
because only irq's 4-15 can be disabled - and only all of them at once.
Thus disable_irq() can effectively block the machine if the driver goes
asleep.
-One thing to keep in mind when hacking around the interrupt code is
+One thing to keep in mind when hacking around the interrupt code is
that there is no way to find out which IRQ caused a request, [EI]IRQ_REG
displays current state of the various IRQ lines.
@@ -123,11 +123,11 @@ q40 receives AT make/break codes from th
the PC scancodes x86 Linux uses. So by theory every national keyboard should
work just by loading the appropriate x86 keytable - see any national-HOWTO.
-Unfortunately the AT->PC translation isn't quite trivial and even worse, my
-documentation of it is absolutely minimal - thus some exotic keys may not
+Unfortunately the AT->PC translation isn't quite trivial and even worse, my
+documentation of it is absolutely minimal - thus some exotic keys may not
behave exactly as expected.
-There is still hope that it can be fixed completely though. If you encounter
+There is still hope that it can be fixed completely though. If you encounter
problems, email me ideally this:
- exact keypress/release sequence
- 'showkey -s' run on q40, non-X session
diff -puN arch/m68k/sun3/config.c~m68k-superfluous-whitespace arch/m68k/sun3/config.c
--- 25/arch/m68k/sun3/config.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/sun3/config.c Thu Apr 22 13:43:13 2004
@@ -42,19 +42,19 @@ extern void sun3_get_model (char* model)
extern void idprom_init (void);
extern int sun3_hwclk(int set, struct rtc_time *t);
-volatile char* clock_va;
+volatile char* clock_va;
extern volatile unsigned char* sun3_intreg;
extern unsigned long availmem;
unsigned long num_pages;
static int sun3_get_hardware_list(char *buffer)
{
-
+
int len = 0;
len += sprintf(buffer + len, "PROM Revision:\t%s\n",
romvec->pv_monid);
-
+
return len;
}
@@ -71,14 +71,14 @@ void __init sun3_init(void)
clock_va = (char *) 0xfe06000; /* dark */
sun3_intreg = (unsigned char *) 0xfe0a000; /* magic */
sun3_disable_interrupts();
-
+
prom_init((void *)LINUX_OPPROM_BEGVM);
-
+
GET_CONTROL_BYTE(AC_SENABLE,enable_register);
- enable_register |= 0x50; /* Enable FPU */
+ enable_register |= 0x50; /* Enable FPU */
SET_CONTROL_BYTE(AC_SENABLE,enable_register);
GET_CONTROL_BYTE(AC_SENABLE,enable_register);
-
+
/* This code looks suspicious, because it doesn't subtract
memory belonging to the kernel from the available space */
@@ -122,7 +122,7 @@ void __init sun3_bootmem_alloc(unsigned
/* align start/end to page boundaries */
memory_start = ((memory_start + (PAGE_SIZE-1)) & PAGE_MASK);
memory_end = memory_end & PAGE_MASK;
-
+
start_page = __pa(memory_start) >> PAGE_SHIFT;
num_pages = __pa(memory_end) >> PAGE_SHIFT;
@@ -134,7 +134,7 @@ void __init sun3_bootmem_alloc(unsigned
free_bootmem(__pa(availmem), memory_end - (availmem));
}
-
+
void __init config_sun3(void)
{
@@ -145,13 +145,13 @@ void __init config_sun3(void)
/* Subtract kernel memory from available memory */
- mach_sched_init = sun3_sched_init;
+ mach_sched_init = sun3_sched_init;
mach_init_IRQ = sun3_init_IRQ;
mach_default_handler = &sun3_default_handler;
mach_request_irq = sun3_request_irq;
mach_free_irq = sun3_free_irq;
- enable_irq = sun3_enable_irq;
- disable_irq = sun3_disable_irq;
+ enable_irq = sun3_enable_irq;
+ disable_irq = sun3_disable_irq;
mach_process_int = sun3_process_int;
mach_get_irq_list = show_sun3_interrupts;
mach_reset = sun3_reboot;
@@ -161,7 +161,7 @@ void __init config_sun3(void)
mach_halt = sun3_halt;
mach_get_hardware_list = sun3_get_hardware_list;
#if defined(CONFIG_DUMMY_CONSOLE)
- conswitchp = &dummy_con;
+ conswitchp = &dummy_con;
#endif
memory_start = ((((int)&_end) + 0x2000) & ~0x1fff);
@@ -170,7 +170,7 @@ void __init config_sun3(void)
m68k_num_memory=1;
m68k_memory[0].size=*(romvec->pv_sun3mem);
-
+
sun3_bootmem_alloc(memory_start, memory_end);
}
@@ -179,7 +179,7 @@ void __init sun3_sched_init(irqreturn_t
sun3_disable_interrupts();
intersil_clock->cmd_reg=(INTERSIL_RUN|INTERSIL_INT_DISABLE|INTERSIL_24H_MODE);
intersil_clock->int_reg=INTERSIL_HZ_100_MASK;
- intersil_clear();
+ intersil_clear();
sun3_enable_irq(5);
intersil_clock->cmd_reg=(INTERSIL_RUN|INTERSIL_INT_ENABLE|INTERSIL_24H_MODE);
sun3_enable_interrupts();
diff -puN arch/m68k/sun3/dvma.c~m68k-superfluous-whitespace arch/m68k/sun3/dvma.c
--- 25/arch/m68k/sun3/dvma.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/sun3/dvma.c Thu Apr 22 13:43:13 2004
@@ -24,13 +24,13 @@ inline unsigned long dvma_page(unsigned
unsigned long pte;
unsigned long j;
pte_t ptep;
-
+
j = *(volatile unsigned long *)kaddr;
*(volatile unsigned long *)kaddr = j;
ptep = pfn_pte(virt_to_pfn(kaddr), PAGE_KERNEL);
pte = pte_val(ptep);
-// printk("dvma_remap: addr %lx -> %lx pte %08lx len %x\n",
+// printk("dvma_remap: addr %lx -> %lx pte %08lx len %x\n",
// kaddr, vaddr, pte, len);
if(ptelist[(vaddr & 0xff000) >> PAGE_SHIFT] != pte) {
sun3_put_pte(vaddr, pte);
@@ -41,7 +41,7 @@ inline unsigned long dvma_page(unsigned
}
-int dvma_map_iommu(unsigned long kaddr, unsigned long baddr,
+int dvma_map_iommu(unsigned long kaddr, unsigned long baddr,
int len)
{
@@ -51,7 +51,7 @@ int dvma_map_iommu(unsigned long kaddr,
vaddr = dvma_btov(baddr);
end = vaddr + len;
-
+
while(vaddr < end) {
dvma_page(kaddr, vaddr);
kaddr += PAGE_SIZE;
diff -puN arch/m68k/sun3/idprom.c~m68k-superfluous-whitespace arch/m68k/sun3/idprom.c
--- 25/arch/m68k/sun3/idprom.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/sun3/idprom.c Thu Apr 22 13:43:13 2004
@@ -67,7 +67,7 @@ static void __init display_system_type(u
prom_getproperty(prom_root_node, "banner-name",
sysname, sizeof(sysname));
printk("TYPE: %s\n", sysname);
-#endif
+#endif
}
return;
}
@@ -83,7 +83,7 @@ void sun3_get_model(unsigned char* model
for (i = 0; i < NUM_SUN_MACHINES; i++) {
if(Sun_Machines[i].id_machtype == idprom->id_machtype) {
- strcpy(model, Sun_Machines[i].name);
+ strcpy(model, Sun_Machines[i].name);
return;
}
}
diff -puN arch/m68k/sun3/intersil.c~m68k-superfluous-whitespace arch/m68k/sun3/intersil.c
--- 25/arch/m68k/sun3/intersil.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/sun3/intersil.c Thu Apr 22 13:43:13 2004
@@ -26,7 +26,7 @@
/* does this need to be implemented? */
unsigned long sun3_gettimeoffset(void)
-{
+{
return 1;
}
diff -puN arch/m68k/sun3/leds.c~m68k-superfluous-whitespace arch/m68k/sun3/leds.c
--- 25/arch/m68k/sun3/leds.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/sun3/leds.c Thu Apr 22 13:43:13 2004
@@ -5,9 +5,9 @@
void sun3_leds(unsigned char byte)
{
unsigned char dfc;
-
+
GET_DFC(dfc);
SET_DFC(FC_CONTROL);
- SET_CONTROL_BYTE(AC_LEDS,byte);
+ SET_CONTROL_BYTE(AC_LEDS,byte);
SET_DFC(dfc);
}
diff -puN arch/m68k/sun3/mmu_emu.c~m68k-superfluous-whitespace arch/m68k/sun3/mmu_emu.c
--- 25/arch/m68k/sun3/mmu_emu.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/sun3/mmu_emu.c Thu Apr 22 13:43:13 2004
@@ -125,12 +125,12 @@ void mmu_emu_init(unsigned long bootmem_
{
unsigned long seg, num;
int i,j;
-
+
memset(rom_pages, 0, sizeof(rom_pages));
memset(pmeg_vaddr, 0, sizeof(pmeg_vaddr));
memset(pmeg_alloc, 0, sizeof(pmeg_alloc));
memset(pmeg_ctx, 0, sizeof(pmeg_ctx));
-
+
/* pmeg align the end of bootmem, adding another pmeg,
* later bootmem allocations will likely need it */
bootmem_end = (bootmem_end + (2 * SUN3_PMEG_SIZE)) & ~SUN3_PMEG_MASK;
@@ -148,7 +148,7 @@ void mmu_emu_init(unsigned long bootmem_
/* liberate all existing mappings in the rest of kernel space */
for(seg = bootmem_end; seg < 0x0f800000; seg += SUN3_PMEG_SIZE) {
i = sun3_get_segmap(seg);
-
+
if(!pmeg_alloc[i]) {
#ifdef DEBUG_MMU_EMU
printk("freed: ");
@@ -179,13 +179,13 @@ void mmu_emu_init(unsigned long bootmem_
pmeg_alloc[sun3_get_segmap(seg)] = 2;
}
}
-
+
dvma_init();
-
-
+
+
/* blank everything below the kernel, and we've got the base
mapping to start all the contexts off with... */
- for(seg = 0; seg < PAGE_OFFSET; seg += SUN3_PMEG_SIZE)
+ for(seg = 0; seg < PAGE_OFFSET; seg += SUN3_PMEG_SIZE)
sun3_put_segmap(seg, SUN3_INVALID_PMEG);
set_fs(MAKE_MM_SEG(3));
@@ -195,7 +195,7 @@ void mmu_emu_init(unsigned long bootmem_
(*(romvec->pv_setctxt))(j, (void *)seg, i);
}
set_fs(KERNEL_DS);
-
+
}
/* erase the mappings for a dead context. Uses the pg_dir for hints
@@ -207,9 +207,9 @@ void clear_context(unsigned long context
{
unsigned char oldctx;
unsigned long i;
-
+
if(context) {
- if(!ctx_alloc[context])
+ if(!ctx_alloc[context])
panic("clear_context: context not allocated\n");
ctx_alloc[context]->context = SUN3_INVALID_CONTEXT;
@@ -229,7 +229,7 @@ void clear_context(unsigned long context
pmeg_vaddr[i] = 0;
}
}
-
+
sun3_put_context(oldctx);
}
@@ -239,7 +239,7 @@ void clear_context(unsigned long context
sure it could be much more intellegent... but it gets the job done
for now without much overhead in making it's decision. */
/* todo: come up with optimized scheme for flushing contexts */
-unsigned long get_free_context(struct mm_struct *mm)
+unsigned long get_free_context(struct mm_struct *mm)
{
unsigned long new = 1;
static unsigned char next_to_die = 1;
@@ -259,7 +259,7 @@ unsigned long get_free_context(struct mm
break;
}
// check to make sure one was really free...
- if(new == CONTEXTS_NUM)
+ if(new == CONTEXTS_NUM)
panic("get_free_context: failed to find free context");
}
@@ -307,7 +307,7 @@ printk("mmu_emu_map_pmeg: pmeg %x to con
if(vaddr >= PAGE_OFFSET) {
/* map kernel pmegs into all contexts */
unsigned char i;
-
+
for(i = 0; i < CONTEXTS_NUM; i++) {
sun3_put_context(i);
sun3_put_segmap (vaddr, curr_pmeg);
@@ -315,7 +315,7 @@ printk("mmu_emu_map_pmeg: pmeg %x to con
sun3_put_context(context);
pmeg_alloc[curr_pmeg] = 2;
pmeg_ctx[curr_pmeg] = 0;
-
+
}
else {
pmeg_alloc[curr_pmeg] = 1;
@@ -326,7 +326,7 @@ printk("mmu_emu_map_pmeg: pmeg %x to con
pmeg_vaddr[curr_pmeg] = vaddr;
/* Set hardware mapping and clear the old PTE entries. */
- for (i=0; i<SUN3_PMEG_SIZE; i+=SUN3_PTE_SIZE)
+ for (i=0; i<SUN3_PMEG_SIZE; i+=SUN3_PTE_SIZE)
sun3_put_pte (vaddr + i, SUN3_PAGE_SYSTEM);
/* Consider a different one next time. */
@@ -361,7 +361,7 @@ int mmu_emu_handle_fault (unsigned long
context = 0;
} else {
context = current->mm->context;
- if(kernel_fault)
+ if(kernel_fault)
crp = swapper_pg_dir;
else
crp = current->mm->pgd;
@@ -390,11 +390,11 @@ int mmu_emu_handle_fault (unsigned long
pte = (pte_t *) __va ((unsigned long)(pte + offset));
/* Make sure this is a valid page */
- if (!(pte_val (*pte) & SUN3_PAGE_VALID))
+ if (!(pte_val (*pte) & SUN3_PAGE_VALID))
return 0;
/* Make sure there's a pmeg allocated for the page */
- if (sun3_get_segmap (vaddr&~SUN3_PMEG_MASK) == SUN3_INVALID_PMEG)
+ if (sun3_get_segmap (vaddr&~SUN3_PMEG_MASK) == SUN3_INVALID_PMEG)
mmu_emu_map_pmeg (context, vaddr);
/* Write the pte value to hardware MMU */
@@ -409,7 +409,7 @@ int mmu_emu_handle_fault (unsigned long
if (pte_val (*pte) & SUN3_PAGE_WRITEABLE)
pte_val (*pte) |= (SUN3_PAGE_ACCESSED
| SUN3_PAGE_MODIFIED);
- else
+ else
return 0; /* Write-protect error. */
} else
pte_val (*pte) |= SUN3_PAGE_ACCESSED;
diff -puN arch/m68k/sun3/prom/init.c~m68k-superfluous-whitespace arch/m68k/sun3/prom/init.c
--- 25/arch/m68k/sun3/prom/init.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/sun3/prom/init.c Thu Apr 22 13:43:13 2004
@@ -73,7 +73,7 @@ void __init prom_init(struct linux_romve
if((prom_root_node == 0) || (prom_root_node == -1))
prom_halt();
- if((((unsigned long) prom_nodeops) == 0) ||
+ if((((unsigned long) prom_nodeops) == 0) ||
(((unsigned long) prom_nodeops) == -1))
prom_halt();
diff -puN arch/m68k/sun3/sun3dvma.c~m68k-superfluous-whitespace arch/m68k/sun3/sun3dvma.c
--- 25/arch/m68k/sun3/sun3dvma.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/sun3/sun3dvma.c Thu Apr 22 13:43:13 2004
@@ -52,21 +52,21 @@ static unsigned long dvma_frees;
static unsigned long long dvma_alloc_bytes;
static unsigned long long dvma_free_bytes;
-static void print_use(void)
+static void print_use(void)
{
-
+
int i;
int j = 0;
printk("dvma entry usage:\n");
-
+
for(i = 0; i < IOMMU_TOTAL_ENTRIES; i++) {
if(!iommu_use[i])
continue;
-
+
j++;
- printk("dvma entry: %08lx len %08lx\n",
+ printk("dvma entry: %08lx len %08lx\n",
( i << DVMA_PAGE_SHIFT) + DVMA_START,
iommu_use[i]);
}
@@ -74,28 +74,28 @@ static void print_use(void)
printk("%d entries in use total\n", j);
printk("allocation/free calls: %lu/%lu\n", dvma_allocs, dvma_frees);
- printk("allocation/free bytes: %Lx/%Lx\n", dvma_alloc_bytes,
+ printk("allocation/free bytes: %Lx/%Lx\n", dvma_alloc_bytes,
dvma_free_bytes);
}
static void print_holes(struct list_head *holes)
{
-
+
struct list_head *cur;
struct hole *hole;
printk("listing dvma holes\n");
list_for_each(cur, holes) {
hole = list_entry(cur, struct hole, list);
-
+
if((hole->start == 0) && (hole->end == 0) && (hole->size == 0))
continue;
-
+
printk("hole: start %08lx end %08lx size %08lx\n", hole->start, hole->end, hole->size);
}
-
+
printk("end of hole listing...\n");
-
+
}
#endif /* DVMA_DEBUG */
@@ -106,7 +106,7 @@ static inline int refill(void)
struct hole *prev = NULL;
struct list_head *cur;
int ret = 0;
-
+
list_for_each(cur, &hole_list) {
hole = list_entry(cur, struct hole, list);
@@ -114,7 +114,7 @@ static inline int refill(void)
prev = hole;
continue;
}
-
+
if(hole->end == prev->start) {
hole->size += prev->size;
hole->end = prev->end;
@@ -122,12 +122,12 @@ static inline int refill(void)
list_add(&(prev->list), &hole_cache);
ret++;
}
-
+
}
return ret;
}
-
+
static inline struct hole *rmcache(void)
{
struct hole *ret;
@@ -148,7 +148,7 @@ static inline struct hole *rmcache(void)
static inline unsigned long get_baddr(int len, unsigned long align)
{
-
+
struct list_head *cur;
struct hole *hole;
@@ -166,11 +166,11 @@ static inline unsigned long get_baddr(in
hole = list_entry(cur, struct hole, list);
- if(align > DVMA_PAGE_SIZE)
+ if(align > DVMA_PAGE_SIZE)
newlen = len + ((hole->end - len) & (align-1));
else
newlen = len;
-
+
if(hole->size > newlen) {
hole->end -= newlen;
hole->size -= newlen;
@@ -200,7 +200,7 @@ static inline unsigned long get_baddr(in
static inline int free_baddr(unsigned long baddr)
{
-
+
unsigned long len;
struct hole *hole;
struct list_head *cur;
@@ -219,7 +219,7 @@ static inline int free_baddr(unsigned lo
list_for_each(cur, &hole_list) {
hole = list_entry(cur, struct hole, list);
-
+
if(hole->end == baddr) {
hole->end += len;
hole->size += len;
@@ -233,21 +233,21 @@ static inline int free_baddr(unsigned lo
}
hole = rmcache();
-
+
hole->start = baddr;
hole->end = baddr + len;
hole->size = len;
-
+
// list_add_tail(&(hole->list), cur);
list_add(&(hole->list), cur);
-
+
return 0;
-
+
}
void dvma_init(void)
{
-
+
struct hole *hole;
int i;
@@ -255,14 +255,14 @@ void dvma_init(void)
INIT_LIST_HEAD(&hole_cache);
/* prepare the hole cache */
- for(i = 0; i < 64; i++)
+ for(i = 0; i < 64; i++)
list_add(&(initholes[i].list), &hole_cache);
-
+
hole = rmcache();
hole->start = DVMA_START;
hole->end = DVMA_END;
hole->size = DVMA_SIZE;
-
+
list_add(&(hole->list), &hole_list);
memset(iommu_use, 0, sizeof(iommu_use));
@@ -291,7 +291,7 @@ inline unsigned long dvma_map_align(unsi
}
#ifdef DEBUG
- printk("dvma_map request %08lx bytes from %08lx\n",
+ printk("dvma_map request %08lx bytes from %08lx\n",
len, kaddr);
#endif
off = kaddr & ~DVMA_PAGE_MASK;
@@ -309,7 +309,7 @@ inline unsigned long dvma_map_align(unsi
if(!dvma_map_iommu(kaddr, baddr, len))
return (baddr + off);
-
+
printk("dvma_map failed kaddr %lx baddr %lx len %x\n", kaddr, baddr, len);
BUG();
return 0;
@@ -318,14 +318,14 @@ inline unsigned long dvma_map_align(unsi
void dvma_unmap(void *baddr)
{
unsigned long addr;
-
+
addr = (unsigned long)baddr;
/* check if this is a vme mapping */
if(!(addr & 0x00f00000))
addr |= 0xf00000;
-
+
free_baddr(addr);
-
+
return;
}
diff -puN arch/m68k/sun3/sun3ints.c~m68k-superfluous-whitespace arch/m68k/sun3/sun3ints.c
--- 25/arch/m68k/sun3/sun3ints.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/sun3/sun3ints.c Thu Apr 22 13:43:13 2004
@@ -28,7 +28,7 @@ void sun3_disable_interrupts(void)
void sun3_enable_interrupts(void)
{
sun3_enable_irq(0);
-}
+}
int led_pattern[8] = {
~(0x80), ~(0x01),
@@ -67,7 +67,7 @@ inline void sun3_do_irq(int irq, struct
static irqreturn_t sun3_int7(int irq, void *dev_id, struct pt_regs *fp)
{
sun3_do_irq(irq,fp);
- if(!(kstat_cpu(0).irqs[SYS_IRQS + irq] % 2000))
+ if(!(kstat_cpu(0).irqs[SYS_IRQS + irq] % 2000))
sun3_leds(led_pattern[(kstat_cpu(0).irqs[SYS_IRQS+irq]%16000)
/2000]);
return IRQ_HANDLED;
@@ -125,7 +125,7 @@ int show_sun3_interrupts(struct seq_file
for(i = 0; i < (SUN3_INT_VECS-1); i++) {
if(sun3_vechandler[i] != NULL) {
- seq_printf(p, "vec %3d: %10u %s\n", i+64,
+ seq_printf(p, "vec %3d: %10u %s\n", i+64,
vec_ints[i],
(vec_names[i]) ? vec_names[i] :
"sun3_vechandler");
@@ -166,12 +166,12 @@ void sun3_init_IRQ(void)
dev_names[i], NULL);
}
- for(i = 0; i < 192; i++)
+ for(i = 0; i < 192; i++)
sun3_vechandler[i] = NULL;
-
+
sun3_vechandler[191] = sun3_vec255;
}
-
+
int sun3_request_irq(unsigned int irq, irqreturn_t (*handler)(int, void *, struct pt_regs *),
unsigned long flags, const char *devname, void *dev_id)
{
@@ -181,11 +181,11 @@ int sun3_request_irq(unsigned int irq, i
printk("sun3_request_irq: request for irq %d -- already taken!\n", irq);
return 1;
}
-
+
sun3_inthandler[irq] = handler;
dev_ids[irq] = dev_id;
dev_names[irq] = devname;
-
+
/* setting devname would be nice */
cpu_request_irq(irq, sun3_default_handler[irq], 0, devname,
NULL);
@@ -205,7 +205,7 @@ int sun3_request_irq(unsigned int irq, i
vec_ids[vec] = dev_id;
vec_names[vec] = devname;
vec_ints[vec] = 0;
-
+
return 0;
}
}
@@ -214,16 +214,16 @@ int sun3_request_irq(unsigned int irq, i
return 1;
}
-
+
void sun3_free_irq(unsigned int irq, void *dev_id)
{
if(irq < SYS_IRQS) {
- if(sun3_inthandler[irq] == NULL)
+ if(sun3_inthandler[irq] == NULL)
panic("sun3_free_int: attempt to free unused irq %d\n", irq);
if(dev_ids[irq] != dev_id)
panic("sun3_free_int: incorrect dev_id for irq %d\n", irq);
-
+
sun3_inthandler[irq] = NULL;
return;
} else if((irq >= 64) && (irq <= 255)) {
@@ -234,12 +234,12 @@ void sun3_free_irq(unsigned int irq, voi
panic("sun3_free_int: attempt to free unused vector %d\n", irq);
if(vec_ids[irq] != dev_id)
panic("sun3_free_int: incorrect dev_id for vec %d\n", irq);
-
+
sun3_vechandler[vec] = NULL;
return;
} else {
panic("sun3_free_irq: invalid irq %d\n", irq);
- }
+ }
}
irqreturn_t sun3_process_int(int irq, struct pt_regs *regs)
@@ -249,7 +249,7 @@ irqreturn_t sun3_process_int(int irq, st
int vec;
vec = irq - 64;
- if(sun3_vechandler[vec] == NULL)
+ if(sun3_vechandler[vec] == NULL)
panic ("bad interrupt vector %d received\n",irq);
vec_ints[vec]++;
diff -puN arch/m68k/sun3x/config.c~m68k-superfluous-whitespace arch/m68k/sun3x/config.c
--- 25/arch/m68k/sun3x/config.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/sun3x/config.c Thu Apr 22 13:43:13 2004
@@ -33,12 +33,12 @@ void sun3_leds(unsigned int i)
static int sun3x_get_hardware_list(char *buffer)
{
-
+
int len = 0;
len += sprintf(buffer + len, "PROM Revision:\t%s\n",
romvec->pv_monid);
-
+
return len;
}
@@ -62,7 +62,7 @@ void __init config_sun3x(void)
mach_request_irq = sun3_request_irq;
mach_free_irq = sun3_free_irq;
mach_process_int = sun3_process_int;
-
+
mach_gettimeoffset = sun3x_gettimeoffset;
mach_reset = sun3x_reboot;
@@ -73,7 +73,7 @@ void __init config_sun3x(void)
sun3_intreg = (unsigned char *)SUN3X_INTREG;
/* only the serial console is known to work anyway... */
-#if 0
+#if 0
switch (*(unsigned char *)SUN3X_EEPROM_CONS) {
case 0x10:
serial_console = 1;
diff -puN arch/m68k/sun3x/dvma.c~m68k-superfluous-whitespace arch/m68k/sun3x/dvma.c
--- 25/arch/m68k/sun3x/dvma.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/sun3x/dvma.c Thu Apr 22 13:43:13 2004
@@ -1,11 +1,11 @@
/*
* Virtual DMA allocation
*
- * (C) 1999 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
+ * (C) 1999 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
*
- * 11/26/2000 -- disabled the existing code because it didn't work for
- * me in 2.4. Replaced with a significantly more primitive version
- * similar to the sun3 code. the old functionality was probably more
+ * 11/26/2000 -- disabled the existing code because it didn't work for
+ * me in 2.4. Replaced with a significantly more primitive version
+ * similar to the sun3 code. the old functionality was probably more
* desirable, but.... -- Sam Creasey (sammy@oh.verio.com)
*
*/
@@ -42,8 +42,8 @@
static volatile unsigned long *iommu_pte = (unsigned long *)SUN3X_IOMMU;
-#define dvma_entry_paddr(index) (iommu_pte[index] & IOMMU_ADDR_MASK)
-#define dvma_entry_vaddr(index,paddr) ((index << DVMA_PAGE_SHIFT) | \
+#define dvma_entry_paddr(index) (iommu_pte[index] & IOMMU_ADDR_MASK)
+#define dvma_entry_vaddr(index,paddr) ((index << DVMA_PAGE_SHIFT) | \
(paddr & (DVMA_PAGE_SIZE-1)))
#if 0
#define dvma_entry_set(index,addr) (iommu_pte[index] = \
@@ -80,7 +80,7 @@ void dvma_print (unsigned long dvma_addr
/* create a virtual mapping for a page assigned within the IOMMU
so that the cpu can reach it easily */
-inline int dvma_map_cpu(unsigned long kaddr,
+inline int dvma_map_cpu(unsigned long kaddr,
unsigned long vaddr, int len)
{
pgd_t *pgd;
@@ -97,7 +97,7 @@ inline int dvma_map_cpu(unsigned long ka
kaddr, vaddr);
#endif
pgd = pgd_offset_k(vaddr);
-
+
do {
pmd_t *pmd;
unsigned long end2;
@@ -107,7 +107,7 @@ inline int dvma_map_cpu(unsigned long ka
goto out;
}
- if((end & PGDIR_MASK) > (vaddr & PGDIR_MASK))
+ if((end & PGDIR_MASK) > (vaddr & PGDIR_MASK))
end2 = (vaddr + (PGDIR_SIZE-1)) & PGDIR_MASK;
else
end2 = end;
@@ -121,7 +121,7 @@ inline int dvma_map_cpu(unsigned long ka
goto out;
}
- if((end2 & PMD_MASK) > (vaddr & PMD_MASK))
+ if((end2 & PMD_MASK) > (vaddr & PMD_MASK))
end3 = (vaddr + (PMD_SIZE-1)) & PMD_MASK;
else
end3 = end2;
@@ -131,17 +131,17 @@ inline int dvma_map_cpu(unsigned long ka
printk("mapping %08lx phys to %08lx\n",
__pa(kaddr), vaddr);
#endif
- set_pte(pte, pfn_pte(virt_to_pfn(kaddr),
+ set_pte(pte, pfn_pte(virt_to_pfn(kaddr),
PAGE_KERNEL));
pte++;
kaddr += PAGE_SIZE;
vaddr += PAGE_SIZE;
} while(vaddr < end3);
-
+
} while(vaddr < end2);
} while(vaddr < end);
-
+
flush_tlb_all();
out:
@@ -150,13 +150,13 @@ inline int dvma_map_cpu(unsigned long ka
inline int dvma_map_iommu(unsigned long kaddr, unsigned long baddr,
- int len)
+ int len)
{
unsigned long end, index;
index = baddr >> DVMA_PAGE_SHIFT;
end = ((baddr+len) >> DVMA_PAGE_SHIFT);
-
+
if(len & ~DVMA_PAGE_MASK)
end++;
@@ -169,12 +169,12 @@ inline int dvma_map_iommu(unsigned long
iommu_pte[index] |= IOMMU_FULL_BLOCK;
// dvma_entry_inc(index);
-
+
kaddr += DVMA_PAGE_SIZE;
}
-#ifdef DEBUG
- for(index = (baddr >> DVMA_PAGE_SHIFT); index < end; index++)
+#ifdef DEBUG
+ for(index = (baddr >> DVMA_PAGE_SHIFT); index < end; index++)
dvma_print(index << DVMA_PAGE_SHIFT);
#endif
return 0;
@@ -185,17 +185,17 @@ void dvma_unmap_iommu(unsigned long badd
{
int index, end;
-
-
+
+
index = baddr >> DVMA_PAGE_SHIFT;
end = (DVMA_PAGE_ALIGN(baddr+len) >> DVMA_PAGE_SHIFT);
-
+
for(; index < end ; index++) {
#ifdef DEBUG
printk("freeing bus mapping %08x\n", index << DVMA_PAGE_SHIFT);
#endif
#if 0
- if(!dvma_entry_use(index))
+ if(!dvma_entry_use(index))
printk("dvma_unmap freeing unused entry %04x\n",
index);
else
diff -puN arch/m68k/sun3x/prom.c~m68k-superfluous-whitespace arch/m68k/sun3x/prom.c
--- 25/arch/m68k/sun3x/prom.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/sun3x/prom.c Thu Apr 22 13:43:13 2004
@@ -119,13 +119,13 @@ void sun3x_prom_init(void)
* XXX this is futile since we restore the vbr first - oops
*/
vectors[VEC_TRAP14] = sun3x_prom_abort;
-
+
/* If debug=prom was specified, start the debug console */
if (!strcmp(m68k_debug_device, "prom"))
register_console(&sun3x_debug);
-
+
}
/* some prom functions to export */
@@ -159,7 +159,7 @@ prom_get_idprom(char *idbuf, int num_byt
int i;
/* make a copy of the idprom structure */
- for(i = 0; i < num_bytes; i++)
+ for(i = 0; i < num_bytes; i++)
idbuf[i] = ((char *)SUN3X_IDPROM)[i];
return idbuf[0];
diff -puN arch/m68k/sun3x/time.c~m68k-superfluous-whitespace arch/m68k/sun3x/time.c
--- 25/arch/m68k/sun3x/time.c~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/arch/m68k/sun3x/time.c Thu Apr 22 13:43:13 2004
@@ -39,12 +39,12 @@
int sun3x_hwclk(int set, struct rtc_time *t)
{
- volatile struct mostek_dt *h =
+ volatile struct mostek_dt *h =
(struct mostek_dt *)(SUN3X_EEPROM+M_CONTROL);
unsigned long flags;
local_irq_save(flags);
-
+
if(set) {
h->csr |= C_WRITE;
h->sec = BIN2BCD(t->tm_sec);
@@ -85,16 +85,16 @@ static void sun3x_timer_tick(int irq, vo
/* Clear the pending interrupt - pulse the enable line low */
disable_irq(5);
enable_irq(5);
-
+
vector(irq, NULL, regs);
}
#endif
void __init sun3x_sched_init(irqreturn_t (*vector)(int, void *, struct pt_regs *))
{
-
+
sun3_disable_interrupts();
-
+
/* Pulse enable low to get the clock started */
sun3_disable_irq(5);
diff -puN include/asm-m68k/amigahw.h~m68k-superfluous-whitespace include/asm-m68k/amigahw.h
--- 25/include/asm-m68k/amigahw.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/amigahw.h Thu Apr 22 13:43:13 2004
@@ -252,8 +252,8 @@ struct CUSTOM {
#define DMAF_ALL (0x01FF)
struct CIA {
- unsigned char pra; char pad0[0xff];
- unsigned char prb; char pad1[0xff];
+ unsigned char pra; char pad0[0xff];
+ unsigned char prb; char pad1[0xff];
unsigned char ddra; char pad2[0xff];
unsigned char ddrb; char pad3[0xff];
unsigned char talo; char pad4[0xff];
@@ -263,10 +263,10 @@ struct CIA {
unsigned char todlo; char pad8[0xff];
unsigned char todmid; char pad9[0xff];
unsigned char todhi; char pada[0x1ff];
- unsigned char sdr; char padb[0xff];
- unsigned char icr; char padc[0xff];
- unsigned char cra; char padd[0xff];
- unsigned char crb; char pade[0xff];
+ unsigned char sdr; char padb[0xff];
+ unsigned char icr; char padc[0xff];
+ unsigned char cra; char padd[0xff];
+ unsigned char crb; char pade[0xff];
};
#define zTwoBase (0x80000000)
@@ -319,7 +319,7 @@ struct tod3000 {
unsigned int :28, year2:4; /* lower digit */
unsigned int :28, year1:4; /* upper digit */
unsigned int :28, cntrl1:4; /* control-byte 1 */
- unsigned int :28, cntrl2:4; /* control-byte 2 */
+ unsigned int :28, cntrl2:4; /* control-byte 2 */
unsigned int :28, cntrl3:4; /* control-byte 3 */
};
#define TOD3000_CNTRL1_HOLD 0
@@ -341,7 +341,7 @@ struct tod2000 {
unsigned int :28, year1:4; /* upper digit */
unsigned int :28, weekday:4;
unsigned int :28, cntrl1:4; /* control-byte 1 */
- unsigned int :28, cntrl2:4; /* control-byte 2 */
+ unsigned int :28, cntrl2:4; /* control-byte 2 */
unsigned int :28, cntrl3:4; /* control-byte 3 */
};
diff -puN include/asm-m68k/apollodma.h~m68k-superfluous-whitespace include/asm-m68k/apollodma.h
--- 25/include/asm-m68k/apollodma.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/apollodma.h Thu Apr 22 13:43:13 2004
@@ -32,7 +32,7 @@
* - page registers for 5-7 don't use data bit 0, represent 128K pages
* - page registers for 0-3 use bit 0, represent 64K pages
*
- * DMA transfers are limited to the lower 16MB of _physical_ memory.
+ * DMA transfers are limited to the lower 16MB of _physical_ memory.
* Note that addresses loaded into registers must be _physical_ addresses,
* not logical addresses (which may differ if paging is active).
*
@@ -42,7 +42,7 @@
* | ... | | ... | | ... |
* | ... | | ... | | ... |
* | ... | | ... | | ... |
- * P7 ... P0 A7 ... A0 A7 ... A0
+ * P7 ... P0 A7 ... A0 A7 ... A0
* | Page | Addr MSB | Addr LSB | (DMA registers)
*
* Address mapping for channels 5-7:
@@ -51,7 +51,7 @@
* | ... | \ \ ... \ \ \ ... \ \
* | ... | \ \ ... \ \ \ ... \ (not used)
* | ... | \ \ ... \ \ \ ... \
- * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
+ * P7 ... P1 (0) A7 A6 ... A0 A7 A6 ... A0
* | Page | Addr MSB | Addr LSB | (DMA registers)
*
* Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
@@ -60,7 +60,7 @@
*
* Transfer count (_not # bytes_) is limited to 64K, represented as actual
* count - 1 : 64K => 0xFFFF, 1 => 0x0000. Thus, count is always 1 or more,
- * and up to 128K bytes may be transferred on channels 5-7 in one operation.
+ * and up to 128K bytes may be transferred on channels 5-7 in one operation.
*
*/
@@ -232,7 +232,7 @@ static __inline__ int get_dma_residue(un
count = 1 + dma_inb(io_port);
count += dma_inb(io_port) << 8;
-
+
return (dmanr<=3)? count : (count<<1);
}
diff -puN include/asm-m68k/apollohw.h~m68k-superfluous-whitespace include/asm-m68k/apollohw.h
--- 25/include/asm-m68k/apollohw.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/apollohw.h Thu Apr 22 13:43:13 2004
@@ -4,7 +4,7 @@
#define _ASMm68k_APOLLOHW_H_
/*
- apollo models
+ apollo models
*/
extern u_long apollo_model;
@@ -16,8 +16,8 @@ extern u_long apollo_model;
#define APOLLO_DN4000 (4)
#define APOLLO_DN4500 (5)
-/*
- see scn2681 data sheet for more info.
+/*
+ see scn2681 data sheet for more info.
member names are read_write.
*/
@@ -96,7 +96,7 @@ extern u_long timer_physaddr;
#define cpuctrl (*(volatile unsigned int *)(IO_BASE + cpuctrl_physaddr))
#define pica (IO_BASE + pica_physaddr)
#define picb (IO_BASE + picb_physaddr)
-#define timer (IO_BASE + timer_physaddr)
+#define timer (IO_BASE + timer_physaddr)
#define addr_xlat_map ((unsigned short *)(IO_BASE + 0x17000))
#define isaIO2mem(x) (((((x) & 0x3f8) << 7) | (((x) & 0xfc00) >> 6) | ((x) & 0x7)) + 0x40000 + IO_BASE)
diff -puN include/asm-m68k/atafdreg.h~m68k-superfluous-whitespace include/asm-m68k/atafdreg.h
--- 25/include/asm-m68k/atafdreg.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/atafdreg.h Thu Apr 22 13:43:13 2004
@@ -65,7 +65,7 @@
/* PSG Port A Bit Nr 0 .. Side Sel .. 0 -> Side 1 1 -> Side 2 */
#define DSKSIDE (0x01)
-
+
#define DSKDRVNONE (0x06)
#define DSKDRV0 (0x02)
#define DSKDRV1 (0x04)
diff -puN include/asm-m68k/atari_acsi.h~m68k-superfluous-whitespace include/asm-m68k/atari_acsi.h
--- 25/include/asm-m68k/atari_acsi.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/atari_acsi.h Thu Apr 22 13:43:13 2004
@@ -27,7 +27,7 @@ extern unsigned long phys_acsi_buffer;
#define DMA_LONG_WRITE(data,mode) \
do { \
- *((unsigned long *)&dma_wd.fdc_acces_seccount) = \
+ *((unsigned long *)&dma_wd.fdc_acces_seccount) = \
((data)<<16) | (mode); \
} while(0)
diff -puN include/asm-m68k/atarihw.h~m68k-superfluous-whitespace include/asm-m68k/atarihw.h
--- 25/include/asm-m68k/atarihw.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/atarihw.h Thu Apr 22 13:43:13 2004
@@ -53,7 +53,7 @@ extern int atari_dont_touch_floppy_selec
#define ATARI_SWITCH_OVSC_SND6 (ATARI_SWITCH_SND6 << ATARI_SWITCH_OVSC_SHIFT)
#define ATARI_SWITCH_OVSC_SND7 (ATARI_SWITCH_SND7 << ATARI_SWITCH_OVSC_SHIFT)
#define ATARI_SWITCH_OVSC_MASK 0xffff0000
-
+
/*
* Define several Hardware-Chips for indication so that for the ATARI we do
* no longer decide whether it is a Falcon or other machine . It's just
@@ -151,8 +151,8 @@ static inline void dma_cache_maintenance
}
-/*
-** Shifter
+/*
+** Shifter
*/
#define ST_LOW 0
#define ST_MID 1
@@ -161,22 +161,22 @@ static inline void dma_cache_maintenance
#define TT_MID 4
#define TT_HIGH 6
-#define SHF_BAS (0xffff8200)
-struct SHIFTER
+#define SHF_BAS (0xffff8200)
+struct SHIFTER
{
- u_char pad1;
+ u_char pad1;
u_char bas_hi;
u_char pad2;
u_char bas_md;
u_char pad3;
u_char volatile vcounthi;
- u_char pad4;
- u_char volatile vcountmid;
- u_char pad5;
- u_char volatile vcountlow;
- u_char volatile syncmode;
- u_char pad6;
- u_char pad7;
+ u_char pad4;
+ u_char volatile vcountmid;
+ u_char pad5;
+ u_char volatile vcountlow;
+ u_char volatile syncmode;
+ u_char pad6;
+ u_char pad7;
u_char bas_lo;
};
# define shifter ((*(volatile struct SHIFTER *)SHF_BAS))
@@ -186,7 +186,7 @@ struct SHIFTER_F030
{
u_short off_next;
u_short scn_width;
- };
+ };
# define shifter_f030 ((*(volatile struct SHIFTER_F030 *)SHF_FBAS))
@@ -278,9 +278,9 @@ struct VIDEL {
/*
** DMA/WD1772 Disk Controller
- */
-
-#define FWD_BAS (0xffff8604)
+ */
+
+#define FWD_BAS (0xffff8604)
struct DMA_WD
{
u_short fdc_acces_seccount;
@@ -364,9 +364,9 @@ struct TT_5380 {
#define tt_scsi_regp ((volatile char *)TT_5380_BAS)
-/*
+/*
** Falcon DMA Sound Subsystem
- */
+ */
#define MATRIX_BASE (0xffff8930)
struct MATRIX
@@ -419,8 +419,8 @@ struct BLITTER
u_short src_x_inc;
u_short src_y_inc;
u_long src_address;
- u_short endmask1;
- u_short endmask2;
+ u_short endmask1;
+ u_short endmask2;
u_short endmask3;
u_short dst_x_inc;
u_short dst_y_inc;
@@ -430,7 +430,7 @@ struct BLITTER
u_short hlf_op_reg;
u_short log_op_reg;
u_short lin_nm_reg;
- u_short skew_reg;
+ u_short skew_reg;
};
# define blitter ((*(volatile struct BLITTER *)BLT_BAS))
@@ -438,7 +438,7 @@ struct BLITTER
/*
** SCC Z8530
*/
-
+
#define SCC_BAS (0xffff8c81)
struct SCC
{
@@ -462,7 +462,7 @@ struct SCC
#define tt_scc_dma ((*(volatile struct TT_DMA *)TT_SCC_DMA_BAS))
/*
-** VIDEL Palette Register
+** VIDEL Palette Register
*/
#define FPL_BAS (0xffff9800)
@@ -487,7 +487,7 @@ struct DSP56K_HOST_INTERFACE {
#define DSP56K_ICR_HM0 0x20
#define DSP56K_ICR_HM1 0x40
#define DSP56K_ICR_INIT 0x80
-
+
u_char cvr;
#define DSP56K_CVR_HV_MASK 0x1f
#define DSP56K_CVR_HC 0x80
@@ -500,7 +500,7 @@ struct DSP56K_HOST_INTERFACE {
#define DSP56K_ISR_HF3 0x10
#define DSP56K_ISR_DMA 0x40
#define DSP56K_ISR_HREQ 0x80
-
+
u_char ivr;
union {
@@ -510,11 +510,11 @@ struct DSP56K_HOST_INTERFACE {
} data;
};
#define dsp56k_host_interface ((*(volatile struct DSP56K_HOST_INTERFACE *)DSP56K_HOST_INTERFACE_BASE))
-
+
/*
** MFP 68901
*/
-
+
#define MFP_BAS (0xfffffa01)
struct MFP
{
@@ -649,7 +649,7 @@ struct TT_RTC {
#define ACIA_IRQ (1<<7) /* Interrupt Request */
#define ACIA_BAS (0xfffffc00)
-struct ACIA
+struct ACIA
{
u_char key_ctrl;
u_char char_dummy1;
@@ -686,17 +686,17 @@ struct TT_DMASND {
u_char pad11[12];
u_char track_select; /* Falcon */
u_char mode;
- u_char pad12[14];
- /* Falcon only: */
- u_short cbar_src;
- u_short cbar_dst;
- u_char ext_div;
- u_char int_div;
- u_char rec_track_select;
- u_char dac_src;
- u_char adc_src;
- u_char input_gain;
- u_short output_atten;
+ u_char pad12[14];
+ /* Falcon only: */
+ u_short cbar_src;
+ u_short cbar_dst;
+ u_char ext_div;
+ u_char int_div;
+ u_char rec_track_select;
+ u_char dac_src;
+ u_char adc_src;
+ u_char input_gain;
+ u_short output_atten;
};
# define tt_dmasnd ((*(volatile struct TT_DMASND *)TT_DMASND_BAS))
@@ -721,7 +721,7 @@ struct TT_DMASND {
#define DMASND_MODE_12KHZ 0x01
#define DMASND_MODE_25KHZ 0x02
#define DMASND_MODE_50KHZ 0x03
-
+
#define DMASNDSetBase(bufstart) \
do { \
diff -puN include/asm-m68k/atariints.h~m68k-superfluous-whitespace include/asm-m68k/atariints.h
--- 25/include/asm-m68k/atariints.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/atariints.h Thu Apr 22 13:43:13 2004
@@ -59,8 +59,8 @@
/* ST-MFP interrupts */
#define IRQ_MFP_BUSY (8)
#define IRQ_MFP_DCD (9)
-#define IRQ_MFP_CTS (10)
-#define IRQ_MFP_GPU (11)
+#define IRQ_MFP_CTS (10)
+#define IRQ_MFP_GPU (11)
#define IRQ_MFP_TIMD (12)
#define IRQ_MFP_TIMC (13)
#define IRQ_MFP_ACIA (14)
@@ -81,7 +81,7 @@
#define IRQ_TT_MFP_IO0 (24)
#define IRQ_TT_MFP_IO1 (25)
#define IRQ_TT_MFP_SCC (26)
-#define IRQ_TT_MFP_RI (27)
+#define IRQ_TT_MFP_RI (27)
#define IRQ_TT_MFP_TIMD (28)
#define IRQ_TT_MFP_TIMC (29)
#define IRQ_TT_MFP_DRVRDY (30)
@@ -122,7 +122,7 @@
static inline int get_mfp_bit( unsigned irq, int type )
{ unsigned char mask, *reg;
-
+
mask = 1 << (irq & 7);
reg = (unsigned char *)&mfp.int_en_a + type*4 +
((irq & 8) >> 2) + (((irq-8) & 16) << 3);
@@ -132,7 +132,7 @@ static inline int get_mfp_bit( unsigned
static inline void set_mfp_bit( unsigned irq, int type )
{ unsigned char mask, *reg;
-
+
mask = 1 << (irq & 7);
reg = (unsigned char *)&mfp.int_en_a + type*4 +
((irq & 8) >> 2) + (((irq-8) & 16) << 3);
@@ -143,7 +143,7 @@ static inline void set_mfp_bit( unsigned
static inline void clear_mfp_bit( unsigned irq, int type )
{ unsigned char mask, *reg;
-
+
mask = ~(1 << (irq & 7));
reg = (unsigned char *)&mfp.int_en_a + type*4 +
((irq & 8) >> 2) + (((irq-8) & 16) << 3);
diff -puN include/asm-m68k/atari_SCCserial.h~m68k-superfluous-whitespace include/asm-m68k/atari_SCCserial.h
--- 25/include/asm-m68k/atari_SCCserial.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/atari_SCCserial.h Thu Apr 22 13:43:13 2004
@@ -20,7 +20,7 @@
/* baud_bases for the common clocks in the Atari. These are the real
* frequencies divided by 16.
*/
-
+
#define SCC_BAUD_BASE_TIMC 19200 /* 0.3072 MHz from TT-MFP, Timer C */
#define SCC_BAUD_BASE_BCLK 153600 /* 2.4576 MHz */
#define SCC_BAUD_BASE_PCLK4 229500 /* 3.6720 MHz */
diff -puN include/asm-m68k/bitops.h~m68k-superfluous-whitespace include/asm-m68k/bitops.h
--- 25/include/asm-m68k/bitops.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/bitops.h Thu Apr 22 13:43:13 2004
@@ -51,7 +51,7 @@ static inline int __generic_test_and_set
__constant_set_bit(nr, vaddr) : \
__generic_set_bit(nr, vaddr))
-#define __set_bit(nr,vaddr) set_bit(nr,vaddr)
+#define __set_bit(nr,vaddr) set_bit(nr,vaddr)
static inline void __constant_set_bit(int nr, volatile unsigned long *vaddr)
{
diff -puN include/asm-m68k/bootinfo.h~m68k-superfluous-whitespace include/asm-m68k/bootinfo.h
--- 25/include/asm-m68k/bootinfo.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/bootinfo.h Thu Apr 22 13:43:13 2004
@@ -141,11 +141,11 @@ struct bi_record {
#define BI_MAC_GMTBIAS 0x8008 /* Mac GMT timezone offset */
#define BI_MAC_MEMSIZE 0x8009 /* Mac RAM size (sanity check) */
#define BI_MAC_CPUID 0x800a /* Mac CPU type (sanity check) */
-#define BI_MAC_ROMBASE 0x800b /* Mac system ROM base address */
+#define BI_MAC_ROMBASE 0x800b /* Mac system ROM base address */
/*
- * Macintosh hardware profile data - unused, see macintosh.h for
- * resonable type values
+ * Macintosh hardware profile data - unused, see macintosh.h for
+ * resonable type values
*/
#define BI_MAC_VIA1BASE 0x8010 /* Mac VIA1 base address (always present) */
@@ -176,7 +176,7 @@ struct bi_record {
#ifndef __ASSEMBLY__
-struct mac_booter_data
+struct mac_booter_data
{
unsigned long videoaddr;
unsigned long videorow;
@@ -202,7 +202,7 @@ struct mac_booter_data
unsigned long timedbra;
};
-extern struct mac_booter_data
+extern struct mac_booter_data
mac_bi_data;
#endif
diff -puN include/asm-m68k/cacheflush.h~m68k-superfluous-whitespace include/asm-m68k/cacheflush.h
--- 25/include/asm-m68k/cacheflush.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/cacheflush.h Thu Apr 22 13:43:13 2004
@@ -45,7 +45,7 @@ extern void cache_push_v(unsigned long v
/* cache code */
#define FLUSH_I_AND_D (0x00000808)
-#define FLUSH_I (0x00000008)
+#define FLUSH_I (0x00000008)
/* This is needed whenever the virtual mapping of the current
process changes. */
@@ -95,14 +95,14 @@ static inline void flush_cache_range(str
unsigned long start,
unsigned long end)
{
- if (vma->vm_mm == current->mm)
+ if (vma->vm_mm == current->mm)
__flush_cache_030();
}
static inline void flush_cache_page(struct vm_area_struct *vma,
unsigned long vmaddr)
{
- if (vma->vm_mm == current->mm)
+ if (vma->vm_mm == current->mm)
__flush_cache_030();
}
diff -puN include/asm-m68k/checksum.h~m68k-superfluous-whitespace include/asm-m68k/checksum.h
--- 25/include/asm-m68k/checksum.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/checksum.h Thu Apr 22 13:43:13 2004
@@ -115,7 +115,7 @@ ip_compute_csum(unsigned char * buff, in
#define _HAVE_ARCH_IPV6_CSUM
static __inline__ unsigned short int
csum_ipv6_magic(struct in6_addr *saddr, struct in6_addr *daddr,
- __u32 len, unsigned short proto, unsigned int sum)
+ __u32 len, unsigned short proto, unsigned int sum)
{
register unsigned long tmp;
__asm__("addl %2@,%0\n\t"
diff -puN include/asm-m68k/delay.h~m68k-superfluous-whitespace include/asm-m68k/delay.h
--- 25/include/asm-m68k/delay.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/delay.h Thu Apr 22 13:43:13 2004
@@ -22,7 +22,7 @@ extern void __bad_udelay(void);
* lookup table, really, as the multiplications take much too long with
* short delays. This is a "reasonable" implementation, though (and the
* first constant multiplications gets optimized away if the delay is
- * a constant)
+ * a constant)
*/
static inline void __const_udelay(unsigned long xloops)
{
diff -puN include/asm-m68k/dvma.h~m68k-superfluous-whitespace include/asm-m68k/dvma.h
--- 25/include/asm-m68k/dvma.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/dvma.h Thu Apr 22 13:43:13 2004
@@ -2,7 +2,7 @@
* include/asm-m68k/dma.h
*
* Copyright 1995 (C) David S. Miller (davem@caip.rutgers.edu)
- *
+ *
* Hacked to fit Sun3x needs by Thomas Bogendoerfer
*/
@@ -16,15 +16,15 @@
#define DVMA_PAGE_MASK (~(DVMA_PAGE_SIZE-1))
#define DVMA_PAGE_ALIGN(addr) (((addr)+DVMA_PAGE_SIZE-1)&DVMA_PAGE_MASK)
-extern void dvma_init(void);
-extern int dvma_map_iommu(unsigned long kaddr, unsigned long baddr,
+extern void dvma_init(void);
+extern int dvma_map_iommu(unsigned long kaddr, unsigned long baddr,
int len);
#define dvma_malloc(x) dvma_malloc_align(x, 0)
#define dvma_map(x, y) dvma_map_align(x, y, 0)
#define dvma_map_vme(x, y) (dvma_map(x, y) & 0xfffff)
#define dvma_map_align_vme(x, y, z) (dvma_map_align (x, y, z) & 0xfffff)
-extern unsigned long dvma_map_align(unsigned long kaddr, int len,
+extern unsigned long dvma_map_align(unsigned long kaddr, int len,
int align);
extern void *dvma_malloc_align(unsigned long len, unsigned long align);
@@ -44,7 +44,7 @@ extern void dvma_free(void *vaddr);
#define IOMMU_TOTAL_ENTRIES 128
#define IOMMU_ENTRIES 120
-/* empirical kludge -- dvma regions only seem to work right on 0x10000
+/* empirical kludge -- dvma regions only seem to work right on 0x10000
byte boundaries */
#define DVMA_REGION_SIZE 0x10000
#define DVMA_ALIGN(addr) (((addr)+DVMA_REGION_SIZE-1) & \
@@ -84,7 +84,7 @@ extern int dvma_map_cpu(unsigned long ka
-/* everything below this line is specific to dma used for the onboard
+/* everything below this line is specific to dma used for the onboard
ESP scsi on sun3x */
/* Structure to describe the current status of DMA registers on the Sparc */
diff -puN include/asm-m68k/entry.h~m68k-superfluous-whitespace include/asm-m68k/entry.h
--- 25/include/asm-m68k/entry.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/entry.h Thu Apr 22 13:43:13 2004
@@ -40,7 +40,7 @@
/* portable version */
#define ALLOWINT (~0x700)
#define MAX_NOINT_IPL 0
-#endif /* machine compilation types */
+#endif /* machine compilation types */
#ifdef __ASSEMBLY__
diff -puN include/asm-m68k/floppy.h~m68k-superfluous-whitespace include/asm-m68k/floppy.h
--- 25/include/asm-m68k/floppy.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/floppy.h Thu Apr 22 13:43:13 2004
@@ -122,9 +122,9 @@ static int m68k_floppy_init(void)
{
use_virtual_dma =1;
can_use_virtual_dma = 1;
-
-
- if (MACH_IS_Q40)
+
+
+ if (MACH_IS_Q40)
return 0x3f0;
else if(MACH_IS_SUN3X)
return sun3xflop_init();
@@ -192,7 +192,7 @@ asmlinkage irqreturn_t floppy_hardint(in
#undef TRACE_FLPY_INT
#define NO_FLOPPY_ASSEMBLER
-#ifdef TRACE_FLPY_INT
+#ifdef TRACE_FLPY_INT
static int calls=0;
static int bytes=0;
static int dma_wait=0;
@@ -214,10 +214,10 @@ asmlinkage irqreturn_t floppy_hardint(in
/* serve 1st byte fast: */
st=1;
- for(lcount=virtual_dma_count, lptr=virtual_dma_addr;
+ for(lcount=virtual_dma_count, lptr=virtual_dma_addr;
lcount; lcount--, lptr++) {
st=inb(virtual_dma_port+4) & 0xa0 ;
- if(st != 0xa0)
+ if(st != 0xa0)
break;
if(virtual_dma_mode)
outb_p(*lptr, virtual_dma_port+5);
@@ -239,7 +239,7 @@ asmlinkage irqreturn_t floppy_hardint(in
virtual_dma_residue += virtual_dma_count;
virtual_dma_count=0;
#ifdef TRACE_FLPY_INT
- printk("count=%x, residue=%x calls=%d bytes=%d dma_wait=%d\n",
+ printk("count=%x, residue=%x calls=%d bytes=%d dma_wait=%d\n",
virtual_dma_count, virtual_dma_residue, calls, bytes,
dma_wait);
calls = 0;
diff -puN include/asm-m68k/hwtest.h~m68k-superfluous-whitespace include/asm-m68k/hwtest.h
--- 25/include/asm-m68k/hwtest.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/hwtest.h Thu Apr 22 13:43:13 2004
@@ -2,12 +2,12 @@
* see arch/m68k/mm/hwtest.c.
* -- PMM <pmaydell@chiark.greenend.org.uk> 05/1998
*
- * Removed __init from decls. We might want them in modules, and
+ * Removed __init from decls. We might want them in modules, and
* the code is tiny anyway. 16/5/98 pb
*/
#ifndef __ASM_HWTEST_H
-#define __ASM_HWTEST_H
+#define __ASM_HWTEST_H
extern int hwreg_present(volatile void *regp);
extern int hwreg_write(volatile void *regp, unsigned short val);
diff -puN include/asm-m68k/ide.h~m68k-superfluous-whitespace include/asm-m68k/ide.h
--- 25/include/asm-m68k/ide.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/ide.h Thu Apr 22 13:43:13 2004
@@ -3,7 +3,7 @@
*
* Copyright (C) 1994-1996 Linus Torvalds & authors
*/
-
+
/* Copyright(c) 1996 Kars de Jong */
/* Based on the ide driver from 1.2.13pl8 */
diff -puN include/asm-m68k/intersil.h~m68k-superfluous-whitespace include/asm-m68k/intersil.h
--- 25/include/asm-m68k/intersil.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/intersil.h Thu Apr 22 13:43:13 2004
@@ -17,7 +17,7 @@
/* bit 4 */
#define INTERSIL_INT_ENABLE 0x10
#define INTERSIL_INT_DISABLE 0x00
-
+
/* bit 5 */
#define INTERSIL_MODE_NORMAL 0x00
#define INTERSIL_MODE_TEST 0x20
diff -puN include/asm-m68k/io.h~m68k-superfluous-whitespace include/asm-m68k/io.h
--- 25/include/asm-m68k/io.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/io.h Thu Apr 22 13:43:13 2004
@@ -1,5 +1,5 @@
/*
- * linux/include/asm-m68k/io.h
+ * linux/include/asm-m68k/io.h
*
* 4/1/00 RZ: - rewritten to avoid clashes between ISA/PCI and other
* IO access
@@ -62,7 +62,7 @@ extern unsigned long gg2_isa_base;
#ifndef MULTI_ISA
#define MULTI_ISA 0
-#else
+#else
#undef MULTI_ISA
#define MULTI_ISA 1
#endif
@@ -76,7 +76,7 @@ extern unsigned long gg2_isa_base;
#ifndef MULTI_ISA
#define MULTI_ISA 0
-#else
+#else
#undef MULTI_ISA
#define MULTI_ISA 1
#endif
@@ -101,7 +101,7 @@ extern unsigned long gg2_isa_base;
#if defined(CONFIG_AMIGA_PCMCIA) && !defined(MULTI_ISA)
#define ISA_TYPE AG_ISA
#define ISA_SEX 1
-#endif
+#endif
#if defined(CONFIG_GG2) && !defined(MULTI_ISA)
#define ISA_TYPE GG2_ISA
#define ISA_SEX 0
@@ -229,7 +229,7 @@ static inline void isa_delay(void)
#endif /* CONFIG_ISA */
-#if defined(CONFIG_ISA) && !defined(CONFIG_PCI)
+#if defined(CONFIG_ISA) && !defined(CONFIG_PCI)
#define inb isa_inb
#define inb_p isa_inb_p
#define outb isa_outb
@@ -273,8 +273,8 @@ static inline void isa_delay(void)
#else
/*
- * kernel with both ISA and PCI compiled in, those have
- * conflicting defs for in/out. Simply consider port < 1024
+ * kernel with both ISA and PCI compiled in, those have
+ * conflicting defs for in/out. Simply consider port < 1024
* ISA and everything else PCI. read,write not defined
* in this case
*/
diff -puN include/asm-m68k/ipc.h~m68k-superfluous-whitespace include/asm-m68k/ipc.h
--- 25/include/asm-m68k/ipc.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/ipc.h Thu Apr 22 13:43:13 2004
@@ -1,7 +1,7 @@
#ifndef __m68k_IPC_H__
#define __m68k_IPC_H__
-/*
+/*
* These are used to wrap system calls on m68k.
*
* See arch/m68k/kernel/sys_m68k.c for ugly details..
diff -puN include/asm-m68k/irq.h~m68k-superfluous-whitespace include/asm-m68k/irq.h
--- 25/include/asm-m68k/irq.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/irq.h Thu Apr 22 13:43:13 2004
@@ -64,7 +64,7 @@ static __inline__ int irq_canonicalize(i
* All interrupt handling is actually machine specific so it is better
* to use function pointers, as used by the Sparc port, and select the
* interrupt handling functions when initializing the kernel. This way
- * we save some unnecessary overhead at run-time.
+ * we save some unnecessary overhead at run-time.
* 01/11/97 - Jes
*/
diff -puN include/asm-m68k/mac_asc.h~m68k-superfluous-whitespace include/asm-m68k/mac_asc.h
--- 25/include/asm-m68k/mac_asc.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/mac_asc.h Thu Apr 22 13:43:13 2004
@@ -1,14 +1,14 @@
/*
- * Apple Sound Chip
+ * Apple Sound Chip
*/
-
+
#ifndef __ASM_MAC_ASC_H
#define __ASM_MAC_ASC_H
/*
* ASC offsets and controls
*/
-
+
#define ASC_BUF_BASE 0x00 /* RAM buffer offset */
#define ASC_BUF_SIZE 0x800
@@ -23,5 +23,5 @@
#define ASC_VOLUME 0x806
#define ASC_CHAN 0x807 /* ??? */
-
+
#endif
diff -puN include/asm-m68k/machw.h~m68k-superfluous-whitespace include/asm-m68k/machw.h
--- 25/include/asm-m68k/machw.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/machw.h Thu Apr 22 13:43:13 2004
@@ -51,7 +51,7 @@ struct MAC_5380 {
/*
** SCC Z8530
*/
-
+
#define MAC_SCC_BAS (0x50F04000)
struct MAC_SCC
{
diff -puN include/asm-m68k/macintosh.h~m68k-superfluous-whitespace include/asm-m68k/macintosh.h
--- 25/include/asm-m68k/macintosh.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/macintosh.h Thu Apr 22 13:43:13 2004
@@ -7,11 +7,11 @@
/*
* Apple Macintoshisms
*/
-
+
extern void mac_reset(void);
extern void mac_poweroff(void);
extern void mac_init_IRQ(void);
-extern int mac_request_irq (unsigned int, irqreturn_t (*)(int, void *,
+extern int mac_request_irq (unsigned int, irqreturn_t (*)(int, void *,
struct pt_regs *),
unsigned long, const char *, void *);
extern void mac_free_irq(unsigned int, void *);
@@ -30,7 +30,7 @@ extern void mac_boom(int);
/*
* Floppy driver magic hook - probably shouldnt be here
*/
-
+
extern void via1_set_head(int);
extern void parse_booter(char *ptr);
@@ -39,7 +39,7 @@ extern void print_booter(char *ptr);
/*
* Macintosh Table
*/
-
+
struct mac_model
{
short ident;
@@ -81,7 +81,7 @@ struct mac_model
#define MAC_SCC_QUADRA 3
#define MAC_SCC_PSC 4
-#define MAC_ETHER_NONE 0
+#define MAC_ETHER_NONE 0
#define MAC_ETHER_SONIC 1
#define MAC_ETHER_MACE 2
@@ -91,7 +91,7 @@ struct mac_model
/*
* Gestalt numbers
*/
-
+
#define MAC_MODEL_II 6
#define MAC_MODEL_IIX 7
#define MAC_MODEL_IICX 8
@@ -113,7 +113,7 @@ struct mac_model
#define MAC_MODEL_PB180 33
#define MAC_MODEL_PB160 34
#define MAC_MODEL_Q800 35 /* aka: WGS80 */
-#define MAC_MODEL_Q650 36
+#define MAC_MODEL_Q650 36
#define MAC_MODEL_LCII 37 /* aka: P400/405/410/430 */
#define MAC_MODEL_PB250 38
#define MAC_MODEL_IIVI 44
@@ -148,5 +148,5 @@ struct mac_model
#define MAC_MODEL_PB150 115
extern struct mac_model *macintosh_config;
-
+
#endif
diff -puN include/asm-m68k/macints.h~m68k-superfluous-whitespace include/asm-m68k/macints.h
--- 25/include/asm-m68k/macints.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/macints.h Thu Apr 22 13:43:13 2004
@@ -52,7 +52,7 @@
#define NUM_MAC_SOURCES 72
-/*
+/*
* clean way to separate IRQ into its source and index
*/
@@ -74,7 +74,7 @@
#define IRQ_VIA1_0 (8) /* one second int. */
#define IRQ_VIA1_1 (9) /* VBlank int. */
#define IRQ_MAC_VBL IRQ_VIA1_1
-#define IRQ_VIA1_2 (10) /* ADB SR shifts complete */
+#define IRQ_VIA1_2 (10) /* ADB SR shifts complete */
#define IRQ_MAC_ADB IRQ_VIA1_2
#define IRQ_MAC_ADB_SR IRQ_VIA1_2
#define IRQ_VIA1_3 (11) /* ADB SR CB2 ?? */
@@ -92,7 +92,7 @@
#define IRQ_MAC_SCSIDRQ IRQ_VIA2_0
#define IRQ_VIA2_1 (17)
#define IRQ_MAC_NUBUS IRQ_VIA2_1
-#define IRQ_VIA2_2 (18)
+#define IRQ_VIA2_2 (18)
#define IRQ_VIA2_3 (19)
#define IRQ_MAC_SCSI IRQ_VIA2_3
#define IRQ_VIA2_4 (20)
@@ -108,7 +108,7 @@
#define IRQ_PSC3_3 (27)
/* Level 4 (SCC) interrupts */
-#define IRQ_SCC (32)
+#define IRQ_SCC (32)
#define IRQ_SCCA (33)
#define IRQ_SCCB (34)
#if 0 /* FIXME: are there multiple interrupt conditions on the SCC ?? */
diff -puN include/asm-m68k/mac_oss.h~m68k-superfluous-whitespace include/asm-m68k/mac_oss.h
--- 25/include/asm-m68k/mac_oss.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/mac_oss.h Thu Apr 22 13:43:13 2004
@@ -3,7 +3,7 @@
*
* This is used in place of VIA2 on the IIfx.
*/
-
+
#define OSS_BASE (0x50f1a000)
/*
diff -puN include/asm-m68k/mac_psc.h~m68k-superfluous-whitespace include/asm-m68k/mac_psc.h
--- 25/include/asm-m68k/mac_psc.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/mac_psc.h Thu Apr 22 13:43:13 2004
@@ -23,7 +23,7 @@
* continuously, although how you keep the buffer filled in this scenario is
* not understood as there seems to be only one input and one output buffer
* pointer.
- *
+ *
* Much of this was extrapolated from what was known about the Ethernet
* registers and subsequently confirmed using MacsBug (ie by pinging the
* machine with easy-to-find patterns and looking for them in the DMA
@@ -43,7 +43,7 @@
* To access a particular set of registers, add 0xn0 to the base
* where n = 3,4,5 or 6.
*/
-
+
#define pIFRbase 0x100
#define pIERbase 0x104
@@ -76,9 +76,9 @@
#define PSC_SET0 0x00
#define PSC_SET1 0x10
-#define PSC_SCSI_ADDR 0x1000 /* confirmed */
-#define PSC_SCSI_LEN 0x1004 /* confirmed */
-#define PSC_SCSI_CMD 0x1008 /* confirmed */
+#define PSC_SCSI_ADDR 0x1000 /* confirmed */
+#define PSC_SCSI_LEN 0x1004 /* confirmed */
+#define PSC_SCSI_CMD 0x1008 /* confirmed */
#define PSC_ENETRD_ADDR 0x1020 /* confirmed */
#define PSC_ENETRD_LEN 0x1024 /* confirmed */
#define PSC_ENETRD_CMD 0x1028 /* confirmed */
@@ -214,7 +214,7 @@ extern int psc_present;
/*
* Access functions
*/
-
+
static inline void psc_write_byte(int offset, __u8 data)
{
*((volatile __u8 *)(psc + offset)) = data;
diff -puN include/asm-m68k/mac_via.h~m68k-superfluous-whitespace include/asm-m68k/mac_via.h
--- 25/include/asm-m68k/mac_via.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/mac_via.h Thu Apr 22 13:43:13 2004
@@ -5,7 +5,7 @@
* via them as are assorted bits and bobs - eg rtc, adb. The picture
* is a bit incomplete as the Mac documentation doesn't cover this well
*/
-
+
#ifndef _ASM_MAC_VIA_H_
#define _ASM_MAC_VIA_H_
@@ -21,7 +21,7 @@
#define VIA1_BASE (0x50F00000)
#define VIA2_BASE (0x50F02000)
#define RBV_BASE (0x50F26000)
-
+
/*
* Not all of these are true post MacII I think.
* CSA: probably the ones CHRP marks as 'unused' change purposes
@@ -34,9 +34,9 @@
* VIA1A_vSccWrReq not available and that VIA1A_vSync has moved to an IOP.
* Also, "All of the functionality of VIA2 has been moved to other chips".
*/
-
+
#define VIA1A_vSccWrReq 0x80 /* SCC write. (input)
- * [CHRP] SCC WREQ: Reflects the state of the
+ * [CHRP] SCC WREQ: Reflects the state of the
* Wait/Request pins from the SCC.
* [Macintosh Family Hardware]
* as CHRP on SE/30,II,IIx,IIcx,IIci.
@@ -93,7 +93,7 @@
#define VIA1A_CPUID1 0x04 /* CPU id bit 0 on RBV, others */
#define VIA1A_CPUID2 0x10 /* CPU id bit 0 on RBV, others */
#define VIA1A_CPUID3 0x40 /* CPU id bit 0 on RBV, others */
-
+
/* Info on VIA1B is from Macintosh Family Hardware & MkLinux.
* CHRP offers no info. */
#define VIA1B_vSound 0x80 /* Sound enable (for compatibility with
@@ -123,7 +123,7 @@
#define EVRB_SFTWRID 0x80 /* Software Interrupt ReQuest */
/*
- * VIA2 A register is the interrupt lines raised off the nubus
+ * VIA2 A register is the interrupt lines raised off the nubus
* slots.
* The below info is from 'Macintosh Family Hardware.'
* MkLinux calls the 'IIci internal video IRQ' below the 'RBV slot 0 irq.'
@@ -131,7 +131,7 @@
* defines the 'Video IRQ' as 0x40 for the 'EVR' VIA work-alike.
* Perhaps OSS uses vRAM1 and vRAM2 for ADB.
*/
-
+
#define VIA2A_vRAM1 0x80 /* RAM size bit 1 (IIci: reserved) */
#define VIA2A_vRAM0 0x40 /* RAM size bit 0 (IIci: internal video IRQ) */
#define VIA2A_vIRQE 0x20 /* IRQ from slot $E */
@@ -148,11 +148,11 @@
* 1 0 4 Mbit
* 1 1 16 Mbit
*/
-
+
/*
* Register B has the fun stuff in it
*/
-
+
#define VIA2B_vVBL 0x80 /* VBL output to VIA1 (60.15Hz) driven by
* timer T1.
* on IIci, parity test: 0=test mode.
@@ -184,11 +184,11 @@
* right bit in the VIA chip (6522 Versatile Interface Adapter).
* [CSA: don't know which one this is, but it's one of 'em!]
*/
-
+
/*
* 6522 registers - see databook.
* CSA: Assignments for VIA1 confirmed from CHRP spec.
- */
+ */
/* partial address decode. 0xYYXX : XX part for RBV, YY part for VIA */
/* Note: 15 VIA regs, 8 RBV regs */
@@ -217,7 +217,7 @@
* decode the bottom eight -- so vBufB | rBufB will always get you BufB */
/* CSA: in fact, only bits 0,1, and 4 seem to be decoded.
* BUT note the values for rIER and rIFR, where the top 8 bits *do* seem
- * to matter. In fact *all* of the top 8 bits seem to matter;
+ * to matter. In fact *all* of the top 8 bits seem to matter;
* setting rIER=0x1813 and rIFR=0x1803 doesn't work, either.
* Perhaps some sort of 'compatibility mode' is built-in? [21-May-1999]
*/
diff -puN include/asm-m68k/md.h~m68k-superfluous-whitespace include/asm-m68k/md.h
--- 25/include/asm-m68k/md.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/md.h Thu Apr 22 13:43:13 2004
@@ -1,8 +1,8 @@
/* $Id: md.h,v 1.1 1997/12/15 15:12:04 jj Exp $
- * md.h: High speed xor_block operation for RAID4/5
+ * md.h: High speed xor_block operation for RAID4/5
*
*/
-
+
#ifndef __ASM_MD_H
#define __ASM_MD_H
diff -puN include/asm-m68k/mmu_context.h~m68k-superfluous-whitespace include/asm-m68k/mmu_context.h
--- 25/include/asm-m68k/mmu_context.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/mmu_context.h Thu Apr 22 13:43:13 2004
@@ -124,7 +124,7 @@ static inline void get_mmu_context(struc
mm->context = get_free_context(mm);
}
-/* flush context if allocated... */
+/* flush context if allocated... */
static inline void destroy_context(struct mm_struct *mm)
{
if(mm->context != SUN3_INVALID_CONTEXT)
@@ -150,5 +150,5 @@ static inline void activate_mm(struct mm
activate_context(next_mm);
}
-#endif
+#endif
#endif
diff -puN include/asm-m68k/motorola_pgtable.h~m68k-superfluous-whitespace include/asm-m68k/motorola_pgtable.h
--- 25/include/asm-m68k/motorola_pgtable.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/motorola_pgtable.h Thu Apr 22 13:43:13 2004
@@ -217,7 +217,7 @@ static inline pmd_t *pmd_offset(pgd_t *d
return (pmd_t *)__pgd_page(*dir) + ((address >> PMD_SHIFT) & (PTRS_PER_PMD-1));
}
-/* Find an entry in the third-level page table.. */
+/* Find an entry in the third-level page table.. */
static inline pte_t *pte_offset_kernel(pmd_t *pmdp, unsigned long address)
{
return (pte_t *)__pmd_page(*pmdp) + ((address >> PAGE_SHIFT) & (PTRS_PER_PTE - 1));
diff -puN include/asm-m68k/msgbuf.h~m68k-superfluous-whitespace include/asm-m68k/msgbuf.h
--- 25/include/asm-m68k/msgbuf.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/msgbuf.h Thu Apr 22 13:43:13 2004
@@ -1,7 +1,7 @@
#ifndef _M68K_MSGBUF_H
#define _M68K_MSGBUF_H
-/*
+/*
* The msqid64_ds structure for m68k architecture.
* Note extra padding because this structure is passed back and forth
* between kernel and user space.
diff -puN include/asm-m68k/mvme147hw.h~m68k-superfluous-whitespace include/asm-m68k/mvme147hw.h
--- 25/include/asm-m68k/mvme147hw.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/mvme147hw.h Thu Apr 22 13:43:13 2004
@@ -21,7 +21,7 @@ typedef struct {
struct pcc_regs {
- volatile u_long dma_tadr;
+ volatile u_long dma_tadr;
volatile u_long dma_dadr;
volatile u_long dma_bcr;
volatile u_long dma_hr;
diff -puN include/asm-m68k/mvme16xhw.h~m68k-superfluous-whitespace include/asm-m68k/mvme16xhw.h
--- 25/include/asm-m68k/mvme16xhw.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/mvme16xhw.h Thu Apr 22 13:43:13 2004
@@ -65,7 +65,7 @@ typedef struct {
#define MVME_SCC_PCLK 10000000
#define MVME162_IRQ_TYPE_PRIO 0
-
+
#define MVME167_IRQ_PRN 0x54
#define MVME16x_IRQ_I596 0x57
#define MVME16x_IRQ_SCSI 0x55
diff -puN include/asm-m68k/openprom.h~m68k-superfluous-whitespace include/asm-m68k/openprom.h
--- 25/include/asm-m68k/openprom.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/openprom.h Thu Apr 22 13:43:13 2004
@@ -91,92 +91,92 @@ struct linux_bootargs_v2 {
#if defined(CONFIG_SUN3) || defined(CONFIG_SUN3X)
struct linux_romvec {
- char *pv_initsp;
+ char *pv_initsp;
int (*pv_startmon)(void);
- int *diagberr;
+ int *diagberr;
struct linux_arguments_v0 **pv_v0bootargs;
- unsigned *pv_sun3mem;
+ unsigned *pv_sun3mem;
unsigned char (*pv_getchar)(void);
int (*pv_putchar)(int ch);
- int (*pv_nbgetchar)(void);
+ int (*pv_nbgetchar)(void);
int (*pv_nbputchar)(int ch);
- unsigned char *pv_echo;
+ unsigned char *pv_echo;
unsigned char *pv_insource;
unsigned char *pv_outsink;
- int (*pv_getkey)(void);
+ int (*pv_getkey)(void);
int (*pv_initgetkey)(void);
unsigned int *pv_translation;
- unsigned char *pv_keybid;
- int *pv_screen_x;
- int *pv_screen_y;
- struct keybuf *pv_keybuf;
+ unsigned char *pv_keybid;
+ int *pv_screen_x;
+ int *pv_screen_y;
+ struct keybuf *pv_keybuf;
char *pv_monid;
- /*
- * Frame buffer output and terminal emulation
+ /*
+ * Frame buffer output and terminal emulation
*/
- int (*pv_fbwritechar)(char);
- int *pv_fbaddr;
- char **pv_font;
- int (*pv_fbwritestr)(char);
+ int (*pv_fbwritechar)(char);
+ int *pv_fbaddr;
+ char **pv_font;
+ int (*pv_fbwritestr)(char);
void (*pv_reboot)(char *bootstr);
- /*
- * Line input and parsing
+ /*
+ * Line input and parsing
*/
- unsigned char *pv_linebuf;
- unsigned char **pv_lineptr;
- int *pv_linesize;
- int (*pv_getline)(void);
- unsigned char (*pv_getnextchar)(void);
- unsigned char (*pv_peeknextchar)(void);
- int *pv_fbthere;
- int (*pv_getnum)(void);
+ unsigned char *pv_linebuf;
+ unsigned char **pv_lineptr;
+ int *pv_linesize;
+ int (*pv_getline)(void);
+ unsigned char (*pv_getnextchar)(void);
+ unsigned char (*pv_peeknextchar)(void);
+ int *pv_fbthere;
+ int (*pv_getnum)(void);
void (*pv_printf)(const char *fmt, ...);
int (*pv_printhex)(void);
- unsigned char *pv_leds;
- int (*pv_setleds)(void);
+ unsigned char *pv_leds;
+ int (*pv_setleds)(void);
- /*
+ /*
* Non-maskable interrupt (nmi) information
- */
+ */
int (*pv_nmiaddr)(void);
int (*pv_abortentry)(void);
- int *pv_nmiclock;
+ int *pv_nmiclock;
int *pv_fbtype;
- /*
- * Assorted other things
+ /*
+ * Assorted other things
*/
unsigned pv_romvers;
- struct globram *pv_globram;
- char *pv_kbdzscc;
+ struct globram *pv_globram;
+ char *pv_kbdzscc;
+
+ int *pv_keyrinit;
+ unsigned char *pv_keyrtick;
+ unsigned *pv_memoryavail;
+ long *pv_resetaddr;
+ long *pv_resetmap;
- int *pv_keyrinit;
- unsigned char *pv_keyrtick;
- unsigned *pv_memoryavail;
- long *pv_resetaddr;
- long *pv_resetmap;
-
- void (*pv_halt)(void);
- unsigned char *pv_memorybitmap;
+ void (*pv_halt)(void);
+ unsigned char *pv_memorybitmap;
#ifdef CONFIG_SUN3
void (*pv_setctxt)(int ctxt, char *va, int pmeg);
- void (*pv_vector_cmd)(void);
+ void (*pv_vector_cmd)(void);
int dummy1z;
int dummy2z;
int dummy3z;
diff -puN include/asm-m68k/oplib.h~m68k-superfluous-whitespace include/asm-m68k/oplib.h
--- 25/include/asm-m68k/oplib.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/oplib.h Thu Apr 22 13:43:13 2004
@@ -244,7 +244,7 @@ extern void prom_getstring(int node, cha
/* Does the passed node have the given "name"? YES=1 NO=0 */
extern int prom_nodematch(int thisnode, char *name);
-/* Puts in buffer a prom name in the form name@x,y or name (x for which_io
+/* Puts in buffer a prom name in the form name@x,y or name (x for which_io
* and y for first regs phys address
*/
extern int prom_getname(int node, char *buf, int buflen);
@@ -272,7 +272,7 @@ extern int prom_node_has_property(int no
*/
extern int prom_setprop(int node, char *prop_name, char *prop_value,
int value_size);
-
+
extern int prom_pathtoinode(char *path);
extern int prom_inst2pkg(int);
@@ -290,8 +290,8 @@ extern void prom_adjust_ranges(struct li
extern void prom_apply_obio_ranges(struct linux_prom_registers *obioregs, int nregs);
/* Apply ranges of any prom node (and optionally parent node as well) to registers. */
-extern void prom_apply_generic_ranges(int node, int parent,
+extern void prom_apply_generic_ranges(int node, int parent,
struct linux_prom_registers *sbusregs, int nregs);
-
+
#endif /* !(__SPARC_OPLIB_H) */
diff -puN include/asm-m68k/page.h~m68k-superfluous-whitespace include/asm-m68k/page.h
--- 25/include/asm-m68k/page.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/page.h Thu Apr 22 13:43:13 2004
@@ -25,9 +25,9 @@
#else
#define THREAD_SIZE PAGE_SIZE
#endif
-
+
#ifndef __ASSEMBLY__
-
+
#define get_user_page(vaddr) __get_free_page(GFP_KERNEL)
#define free_user_page(page, addr) free_page(addr)
@@ -80,7 +80,7 @@ static inline void clear_page(void *page
#endif
#define clear_user_page(addr, vaddr, page) \
- do { clear_page(addr); \
+ do { clear_page(addr); \
flush_dcache_page(page); \
} while (0)
#define copy_user_page(to, from, vaddr, page) \
diff -puN include/asm-m68k/page_offset.h~m68k-superfluous-whitespace include/asm-m68k/page_offset.h
--- 25/include/asm-m68k/page_offset.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/page_offset.h Thu Apr 22 13:43:13 2004
@@ -4,6 +4,6 @@
#ifndef CONFIG_SUN3
#define PAGE_OFFSET_RAW 0x00000000
#else
-#define PAGE_OFFSET_RAW 0x0E000000
+#define PAGE_OFFSET_RAW 0x0E000000
#endif
diff -puN include/asm-m68k/q40_master.h~m68k-superfluous-whitespace include/asm-m68k/q40_master.h
--- 25/include/asm-m68k/q40_master.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/q40_master.h Thu Apr 22 13:43:13 2004
@@ -1,5 +1,5 @@
-/*
- * Q40 master Chip Control
+/*
+ * Q40 master Chip Control
* RTC stuff merged for compactnes..
*/
diff -puN include/asm-m68k/raw_io.h~m68k-superfluous-whitespace include/asm-m68k/raw_io.h
--- 25/include/asm-m68k/raw_io.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/raw_io.h Thu Apr 22 13:43:13 2004
@@ -1,5 +1,5 @@
/*
- * linux/include/asm-m68k/raw_io.h
+ * linux/include/asm-m68k/raw_io.h
*
* 10/20/00 RZ: - created from bits of io.h and ide.h to cleanup namespace
*
diff -puN include/asm-m68k/rtc.h~m68k-superfluous-whitespace include/asm-m68k/rtc.h
--- 25/include/asm-m68k/rtc.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/rtc.h Thu Apr 22 13:43:13 2004
@@ -51,7 +51,7 @@ static inline unsigned int get_rtc_ss(vo
return mach_get_ss();
else{
struct rtc_time h;
-
+
get_rtc_time(&h);
return h.tm_sec;
}
diff -puN include/asm-m68k/sembuf.h~m68k-superfluous-whitespace include/asm-m68k/sembuf.h
--- 25/include/asm-m68k/sembuf.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/sembuf.h Thu Apr 22 13:43:13 2004
@@ -1,7 +1,7 @@
#ifndef _M68K_SEMBUF_H
#define _M68K_SEMBUF_H
-/*
+/*
* The semid64_ds structure for m68k architecture.
* Note extra padding because this structure is passed back and forth
* between kernel and user space.
diff -puN include/asm-m68k/serial.h~m68k-superfluous-whitespace include/asm-m68k/serial.h
--- 25/include/asm-m68k/serial.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/serial.h Thu Apr 22 13:43:13 2004
@@ -2,7 +2,7 @@
* include/asm-m68k/serial.h
*
* currently this seems useful only for a Q40,
- * it's an almost exact copy of ../asm-alpha/serial.h
+ * it's an almost exact copy of ../asm-alpha/serial.h
*
*/
@@ -31,7 +31,7 @@
#define ACCENT_FLAGS 0
#define BOCA_FLAGS 0
#endif
-
+
#define STD_SERIAL_PORT_DEFNS \
/* UART CLK PORT IRQ FLAGS */ \
{ 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS }, /* ttyS0 */ \
@@ -42,7 +42,7 @@
#ifdef CONFIG_SERIAL_MANY_PORTS
#define EXTRA_SERIAL_PORT_DEFNS \
- { 0, BASE_BAUD, 0x1A0, 9, FOURPORT_FLAGS }, /* ttyS4 */ \
+ { 0, BASE_BAUD, 0x1A0, 9, FOURPORT_FLAGS }, /* ttyS4 */ \
{ 0, BASE_BAUD, 0x1A8, 9, FOURPORT_FLAGS }, /* ttyS5 */ \
{ 0, BASE_BAUD, 0x1B0, 9, FOURPORT_FLAGS }, /* ttyS6 */ \
{ 0, BASE_BAUD, 0x1B8, 9, FOURPORT_FLAGS }, /* ttyS7 */ \
diff -puN include/asm-m68k/setup.h~m68k-superfluous-whitespace include/asm-m68k/setup.h
--- 25/include/asm-m68k/setup.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/setup.h Thu Apr 22 13:43:13 2004
@@ -248,7 +248,7 @@ extern unsigned long m68k_fputype;
extern unsigned long m68k_mmutype; /* Not really used yet */
#ifdef CONFIG_VME
extern unsigned long vme_brdtype;
-#endif
+#endif
/*
* m68k_is040or060 is != 0 for a '040 or higher;
diff -puN include/asm-m68k/shmbuf.h~m68k-superfluous-whitespace include/asm-m68k/shmbuf.h
--- 25/include/asm-m68k/shmbuf.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/shmbuf.h Thu Apr 22 13:43:13 2004
@@ -1,7 +1,7 @@
#ifndef _M68K_SHMBUF_H
#define _M68K_SHMBUF_H
-/*
+/*
* The shmid64_ds structure for m68k architecture.
* Note extra padding because this structure is passed back and forth
* between kernel and user space.
diff -puN include/asm-m68k/sigcontext.h~m68k-superfluous-whitespace include/asm-m68k/sigcontext.h
--- 25/include/asm-m68k/sigcontext.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/sigcontext.h Thu Apr 22 13:43:13 2004
@@ -2,7 +2,7 @@
#define _ASM_M68k_SIGCONTEXT_H
struct sigcontext {
- unsigned long sc_mask; /* old sigmask */
+ unsigned long sc_mask; /* old sigmask */
unsigned long sc_usp; /* old user stack pointer */
unsigned long sc_d0;
unsigned long sc_d1;
diff -puN include/asm-m68k/signal.h~m68k-superfluous-whitespace include/asm-m68k/signal.h
--- 25/include/asm-m68k/signal.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/signal.h Thu Apr 22 13:43:13 2004
@@ -96,7 +96,7 @@ typedef unsigned long sigset_t;
#define SA_ONESHOT SA_RESETHAND
#define SA_INTERRUPT 0x20000000 /* dummy -- ignored */
-/*
+/*
* sigaltstack controls
*/
#define SS_ONSTACK 1
diff -puN include/asm-m68k/sockios.h~m68k-superfluous-whitespace include/asm-m68k/sockios.h
--- 25/include/asm-m68k/sockios.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/sockios.h Thu Apr 22 13:43:13 2004
@@ -2,7 +2,7 @@
#define __ARCH_M68K_SOCKIOS__
/* Socket-level I/O control calls. */
-#define FIOSETOWN 0x8901
+#define FIOSETOWN 0x8901
#define SIOCSPGRP 0x8902
#define FIOGETOWN 0x8903
#define SIOCGPGRP 0x8904
diff -puN include/asm-m68k/string.h~m68k-superfluous-whitespace include/asm-m68k/string.h
--- 25/include/asm-m68k/string.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/string.h Thu Apr 22 13:43:13 2004
@@ -73,7 +73,7 @@ static inline char * strncat(char *dest,
static inline char * strchr(const char * s, int c)
{
const char ch = c;
-
+
for(; *s != ch; ++s)
if (*s == '\0')
return( NULL );
@@ -85,7 +85,7 @@ static inline char * strchr(const char *
static inline char *strpbrk(const char *cs,const char *ct)
{
const char *sc1,*sc2;
-
+
for( sc1 = cs; *sc1 != '\0'; ++sc1)
for( sc2 = ct; *sc2 != '\0'; ++sc2)
if (*sc1 == *sc2)
diff -puN include/asm-m68k/sun3mmu.h~m68k-superfluous-whitespace include/asm-m68k/sun3mmu.h
--- 25/include/asm-m68k/sun3mmu.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/sun3mmu.h Thu Apr 22 13:43:13 2004
@@ -144,7 +144,7 @@ static inline unsigned char sun3_get_con
SET_SFC(FC_CONTROL);
GET_CONTROL_BYTE(AC_CONTEXT, c);
SET_SFC(sfc);
-
+
return c;
}
@@ -156,7 +156,7 @@ static inline void sun3_put_context(unsi
SET_DFC(FC_CONTROL);
SET_CONTROL_BYTE(AC_CONTEXT, c);
SET_DFC(dfc);
-
+
return;
}
diff -puN include/asm-m68k/sun3_pgalloc.h~m68k-superfluous-whitespace include/asm-m68k/sun3_pgalloc.h
--- 25/include/asm-m68k/sun3_pgalloc.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/sun3_pgalloc.h Thu Apr 22 13:43:13 2004
@@ -1,5 +1,5 @@
/* sun3_pgalloc.h --
- * reorganization around 2.3.39, routines moved from sun3_pgtable.h
+ * reorganization around 2.3.39, routines moved from sun3_pgtable.h
*
*
* 02/27/2002 -- Modified to support "highpte" implementation in 2.5.5 (Sam)
@@ -36,26 +36,26 @@ static inline void __pte_free_tlb(struct
tlb_remove_page(tlb, page);
}
-static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
+static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
unsigned long address)
{
unsigned long page = __get_free_page(GFP_KERNEL|__GFP_REPEAT);
if (!page)
return NULL;
-
+
memset((void *)page, 0, PAGE_SIZE);
return (pte_t *) (page);
}
-static inline struct page *pte_alloc_one(struct mm_struct *mm,
+static inline struct page *pte_alloc_one(struct mm_struct *mm,
unsigned long address)
{
struct page *page = alloc_pages(GFP_KERNEL|__GFP_REPEAT, 0);
if (page == NULL)
return NULL;
-
+
clear_highpage(page);
return page;
diff -puN include/asm-m68k/sun3xflop.h~m68k-superfluous-whitespace include/asm-m68k/sun3xflop.h
--- 25/include/asm-m68k/sun3xflop.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/sun3xflop.h Thu Apr 22 13:43:13 2004
@@ -89,11 +89,11 @@ static void sun3x_82072_fd_outb(unsigned
if(value & 0x10) {
fcr |= (FCR_DSEL0 | FCR_MTRON);
- } else
+ } else
fcr &= ~(FCR_DSEL0 | FCR_MTRON);
-
-
- if(fcr != sun3x_fdc.fcr) {
+
+
+ if(fcr != sun3x_fdc.fcr) {
*(sun3x_fdc.fcr_r) = fcr;
sun3x_fdc.fcr = fcr;
}
@@ -121,7 +121,7 @@ asmlinkage irqreturn_t sun3xflop_hardint
#undef TRACE_FLPY_INT
#define NO_FLOPPY_ASSEMBLER
-#ifdef TRACE_FLPY_INT
+#ifdef TRACE_FLPY_INT
static int calls=0;
static int bytes=0;
static int dma_wait=0;
@@ -142,13 +142,13 @@ asmlinkage irqreturn_t sun3xflop_hardint
register int lcount;
register char *lptr;
- for(lcount=virtual_dma_count, lptr=virtual_dma_addr;
+ for(lcount=virtual_dma_count, lptr=virtual_dma_addr;
lcount; lcount--, lptr++) {
/* st=fd_inb(virtual_dma_port+4) & 0x80 ; */
st = *(sun3x_fdc.status_r);
/* if(st != 0xa0) */
/* break; */
-
+
if((st & 0x80) == 0) {
virtual_dma_count = lcount;
virtual_dma_addr = lptr;
@@ -157,7 +157,7 @@ asmlinkage irqreturn_t sun3xflop_hardint
if((st & 0x20) == 0)
break;
-
+
if(virtual_dma_mode)
/* fd_outb(*lptr, virtual_dma_port+5); */
*(sun3x_fdc.data_r) = *lptr;
@@ -165,7 +165,7 @@ asmlinkage irqreturn_t sun3xflop_hardint
/* *lptr = fd_inb(virtual_dma_port+5); */
*lptr = *(sun3x_fdc.data_r);
}
-
+
virtual_dma_count = lcount;
virtual_dma_addr = lptr;
/* st = fd_inb(virtual_dma_port+4); */
@@ -184,7 +184,7 @@ asmlinkage irqreturn_t sun3xflop_hardint
doing_pdma = 0;
#ifdef TRACE_FLPY_INT
- printk("count=%x, residue=%x calls=%d bytes=%x dma_wait=%d\n",
+ printk("count=%x, residue=%x calls=%d bytes=%x dma_wait=%d\n",
virtual_dma_count, virtual_dma_residue, calls, bytes,
dma_wait);
calls = 0;
@@ -195,7 +195,7 @@ asmlinkage irqreturn_t sun3xflop_hardint
return IRQ_HANDLED;
}
-
+
#ifdef TRACE_FLPY_INT
if(!virtual_dma_count)
dma_wait++;
@@ -232,9 +232,9 @@ static int sun3xflop_init(void)
if(*sun3x_fdc.status_r == 0xff) {
return -1;
}
-
+
*sun3x_fdc.fvr_r = FLOPPY_IRQ;
-
+
*sun3x_fdc.fcr_r = FCR_TC;
udelay(10);
*sun3x_fdc.fcr_r = 0;
@@ -249,7 +249,7 @@ static int sun3xflop_init(void)
static int sun3x_eject(void)
{
if(MACH_IS_SUN3X) {
-
+
sun3x_fdc.fcr |= (FCR_DSEL0 | FCR_EJECT);
*(sun3x_fdc.fcr_r) = sun3x_fdc.fcr;
udelay(10);
diff -puN include/asm-m68k/sun3x.h~m68k-superfluous-whitespace include/asm-m68k/sun3x.h
--- 25/include/asm-m68k/sun3x.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/sun3x.h Thu Apr 22 13:43:13 2004
@@ -20,7 +20,7 @@
#define SUN3X_FDC_FVR 0x6e000800
/* some NVRAM addresses */
-#define SUN3X_EEPROM_CONS (SUN3X_EEPROM + 0x1f)
+#define SUN3X_EEPROM_CONS (SUN3X_EEPROM + 0x1f)
#define SUN3X_EEPROM_PORTA (SUN3X_EEPROM + 0x58)
#define SUN3X_EEPROM_PORTB (SUN3X_EEPROM + 0x60)
diff -puN include/asm-m68k/termios.h~m68k-superfluous-whitespace include/asm-m68k/termios.h
--- 25/include/asm-m68k/termios.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/termios.h Thu Apr 22 13:43:13 2004
@@ -3,7 +3,7 @@
#include <asm/termbits.h>
#include <asm/ioctls.h>
-
+
struct winsize {
unsigned short ws_row;
unsigned short ws_col;
diff -puN include/asm-m68k/thread_info.h~m68k-superfluous-whitespace include/asm-m68k/thread_info.h
--- 25/include/asm-m68k/thread_info.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/thread_info.h Thu Apr 22 13:43:13 2004
@@ -56,7 +56,7 @@ extern int thread_flag_fixme(void);
* - pass TIF_xxxx constants to these functions
*/
-#define __set_tsk_thread_flag(tsk, flag, val) ({ \
+#define __set_tsk_thread_flag(tsk, flag, val) ({ \
switch (flag) { \
case TIF_SIGPENDING: \
tsk->thread.work.sigpending = val; \
diff -puN include/asm-m68k/tlbflush.h~m68k-superfluous-whitespace include/asm-m68k/tlbflush.h
--- 25/include/asm-m68k/tlbflush.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/tlbflush.h Thu Apr 22 13:43:13 2004
@@ -147,7 +147,7 @@ static inline void flush_tlb_mm (struct
seg = sun3_get_segmap(i);
if(seg == SUN3_INVALID_PMEG)
continue;
-
+
sun3_put_segmap(i, SUN3_INVALID_PMEG);
pmeg_alloc[seg] = 0;
pmeg_ctx[seg] = 0;
@@ -155,7 +155,7 @@ static inline void flush_tlb_mm (struct
}
sun3_put_context(oldctx);
-
+
}
/* Flush a single TLB page. In this case, we're limited to flushing a
@@ -174,7 +174,7 @@ static inline void flush_tlb_page (struc
pmeg_alloc[i] = 0;
pmeg_ctx[i] = 0;
pmeg_vaddr[i] = 0;
- sun3_put_segmap (addr, SUN3_INVALID_PMEG);
+ sun3_put_segmap (addr, SUN3_INVALID_PMEG);
}
sun3_put_context(oldctx);
@@ -186,7 +186,7 @@ static inline void flush_tlb_range (stru
{
struct mm_struct *mm = vma->vm_mm;
unsigned char seg, oldctx;
-
+
start &= ~SUN3_PMEG_MASK;
oldctx = sun3_get_context();
@@ -194,7 +194,7 @@ static inline void flush_tlb_range (stru
while(start < end)
{
- if((seg = sun3_get_segmap(start)) == SUN3_INVALID_PMEG)
+ if((seg = sun3_get_segmap(start)) == SUN3_INVALID_PMEG)
goto next;
if(pmeg_ctx[seg] == mm->context) {
pmeg_alloc[seg] = 0;
diff -puN include/asm-m68k/unaligned.h~m68k-superfluous-whitespace include/asm-m68k/unaligned.h
--- 25/include/asm-m68k/unaligned.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/unaligned.h Thu Apr 22 13:43:13 2004
@@ -2,7 +2,7 @@
#define __M68K_UNALIGNED_H
/*
- * The m68k can do unaligned accesses itself.
+ * The m68k can do unaligned accesses itself.
*
* The strange macros are there to make sure these can't
* be misused in a way that makes them not work on other
diff -puN include/asm-m68k/user.h~m68k-superfluous-whitespace include/asm-m68k/user.h
--- 25/include/asm-m68k/user.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/user.h Thu Apr 22 13:43:13 2004
@@ -51,7 +51,7 @@ struct user_regs_struct {
short __fill;
};
-
+
/* When the kernel dumps core, it starts by dumping the user struct -
this will be used by gdb to figure out where the data and stack segments
are within the file, and what virtual addresses to use. */
@@ -72,7 +72,7 @@ struct user{
This is actually the bottom of the stack,
the top of the stack is always found in the
esp register. */
- long int signal; /* Signal that caused the core dump. */
+ long int signal; /* Signal that caused the core dump. */
int reserved; /* No longer used */
struct user_regs_struct *u_ar0;
/* Used by gdb to help find the values for */
diff -puN include/asm-m68k/virtconvert.h~m68k-superfluous-whitespace include/asm-m68k/virtconvert.h
--- 25/include/asm-m68k/virtconvert.h~m68k-superfluous-whitespace Thu Apr 22 13:43:13 2004
+++ 25-akpm/include/asm-m68k/virtconvert.h Thu Apr 22 13:43:13 2004
@@ -31,7 +31,7 @@ static inline unsigned long mm_ptov(unsi
{
return (unsigned long)__va(paddr);
}
-#endif
+#endif
#ifdef CONFIG_SINGLE_MEMORY_CHUNK
static inline unsigned long virt_to_phys(void *vaddr)
_