From: Marcelo Tosatti <marcelo.tosatti@cyclades.com>

On PPC 8xx, the DataTLBMiss handler does not jump directly to the page
fault handler, as was the case in v2.4.  

It instead loads an invalid TLB which causes a subsequent DataTLBError
exception.

The comment on top of it haven't been update to reflect the change, though.

Signed-off-by: Marcelo Tosatti <marcelo.tosatti@cyclades.com>
Signed-off-by: Andrew Morton <akpm@osdl.org>
---

 arch/ppc/kernel/head_8xx.S |   12 +++++-------
 1 files changed, 5 insertions(+), 7 deletions(-)

diff -puN arch/ppc/kernel/head_8xx.S~ppc32-8xx-update-datatlbmiss-exception-comment arch/ppc/kernel/head_8xx.S
--- devel/arch/ppc/kernel/head_8xx.S~ppc32-8xx-update-datatlbmiss-exception-comment	2005-07-25 21:02:06.000000000 -0700
+++ devel-akpm/arch/ppc/kernel/head_8xx.S	2005-07-25 21:02:06.000000000 -0700
@@ -288,13 +288,11 @@ SystemCall:
  * For the MPC8xx, this is a software tablewalk to load the instruction
  * TLB.  It is modelled after the example in the Motorola manual.  The task
  * switch loads the M_TWB register with the pointer to the first level table.
- * If we discover there is no second level table (the value is zero), the
- * plan was to load that into the TLB, which causes another fault into the
- * TLB Error interrupt where we can handle such problems.  However, that did
- * not work, so if we discover there is no second level table, we restore
- * registers and branch to the error exception.  We have to use the MD_xxx
- * registers for the tablewalk because the equivalent MI_xxx registers
- * only perform the attribute functions.
+ * If we discover there is no second level table (value is zero) or if there
+ * is an invalid pte, we load that into the TLB, which causes another fault
+ * into the TLB Error interrupt where we can handle such problems.
+ * We have to use the MD_xxx registers for the tablewalk because the
+ * equivalent MI_xxx registers only perform the attribute functions.
  */
 InstructionTLBMiss:
 #ifdef CONFIG_8xx_CPU6
_